CN113782543B - Pixel array substrate - Google Patents

Abstract

A pixel array substrate includes a plurality of data lines, a plurality of gate lines, a plurality of pixel structures and a plurality of transfer lines. Each pixel structure includes a thin film transistor, a pixel electrode and a bridge element. A plurality of pixel structures are arranged into a plurality of pixel columns. Each data line has opposite first and second sides. The source of the thin film transistor of a pixel structure in a pixel row is electrically connected to the same data line as the source of the thin film transistor of a pixel structure in a next pixel row. The drains of the thin film transistors in the pixel structure of the pixel column and the drains of the thin film transistors in the pixel structure of the next pixel column are located on the first side of the same data line. The pixel electrode of the pixel structure of the pixel column and the pixel electrode of the pixel structure of the next pixel column are respectively located on the second side and the first side of the same data line. The bridging elements of the pixel structure of the pixel row straddle the same data line and a transfer line.

Description

Pixel Array Substrate

technical field

The invention relates to a pixel array substrate.

Background technique

With the development of display technology, people's demand for display devices is no longer satisfied with optical properties such as high resolution, high contrast, and wide viewing angle. People also expect the display device to have an elegant appearance. For example, people expect display devices to have narrow bezels, or even no bezels.

Generally speaking, a display device includes a pixel array disposed in the display area, a data driving circuit disposed below the display area, and a gate driving circuit disposed on the left, right or left and right sides of the display area. In order to reduce the width of the left and right sides of the frame of the display device, both the gate driving circuit and the data driving circuit can be arranged on the lower side of the display area. When the gate driving circuit is disposed on the lower side of the display area, the gate lines extending in the horizontal direction must pass through the transfer lines extending in the vertical direction to be electrically connected to the gate driving circuit. However, when the transfer wire is set in the active area, the transfer wire will inevitably be adjacent to the data line; the coupling effect between the transfer wire and the data line will cause the data signal on the data line to shift, thereby causing the problem of diagonal stripes .

Contents of the invention

The invention provides a pixel array substrate with good performance and high aperture ratio.

The pixel array substrate of the present invention includes a substrate, a plurality of data lines, a plurality of gate lines, a plurality of pixel structures and a plurality of transfer lines. A plurality of data lines are arranged on the base and arranged in a first direction. A plurality of gate lines are disposed on the base and arranged in a second direction, wherein the first direction and the second direction are interlaced. A plurality of pixel structures are disposed on the substrate, wherein each pixel structure includes a thin film transistor, a pixel electrode and a bridge element, and a source electrode and a gate electrode of the thin film transistor are respectively electrically connected to a corresponding data line and a corresponding A gate line, the pixel electrode is arranged outside the drain of the thin film transistor, and the bridging element is electrically connected to the drain of the thin film transistor and the pixel electrode. A plurality of transfer lines are disposed on the base, arranged in a first direction, and electrically connected to a plurality of gate lines. A plurality of pixel structures are arranged into a plurality of pixel columns. A plurality of pixel structures of each pixel row are arranged in a first direction, and a plurality of pixel rows are arranged in a second direction. Each data line has opposite first and second sides. The source of the thin film transistor of a pixel structure in a pixel row is electrically connected to the same data line as the source of the thin film transistor of a pixel structure in a next pixel row. The drains of the thin film transistors in the pixel structure of the pixel column and the drains of the thin film transistors in the pixel structure of the next pixel column are located on the first side of the same data line. The pixel electrode of the pixel structure of the pixel column and the pixel electrode of the pixel structure of the next pixel column are respectively located on the second side and the first side of the same data line. The bridging elements of the pixel structure of the pixel row straddle the same data line and a transfer line.

In an embodiment of the present invention, the above-mentioned pixel array substrate further includes a first insulating layer, a common electrode layer and a second insulating layer. The first insulating layer is disposed on the multiple thin film transistors of the multiple pixel structures. The common electrode layer is disposed on the first insulating layer. The second insulating layer is disposed on the common electrode layer. The bridge element of the pixel structure of the pixel row is disposed on the second insulating layer, and the common electrode layer is disposed between the bridge element of the pixel structure of the pixel row and the transfer line.

In an embodiment of the present invention, the above-mentioned pixel electrodes of the pixel structures of the pixel columns are disposed on the second insulating layer, and the common electrode layer is disposed between the pixel electrodes of the pixel structures of the pixel columns and the transfer lines.

In an embodiment of the present invention, the bridge elements of the pixel structure of the above pixel row are interleaved with the same data line, and the bridge elements of the pixel structure of the next pixel row are arranged outside the same data line and do not overlap the same data line.

In an embodiment of the present invention, the plurality of pixel electrodes of the above-mentioned plurality of pixel structures are arranged into a plurality of pixel electrode rows, and the plurality of pixel electrodes in each pixel electrode row are arranged in the second direction, and the plurality of pixel electrodes The rows are arranged in the first direction; a plurality of pixel electrode rows include a first pixel electrode row and a second pixel electrode row for displaying red and blue respectively; Between the electrode row and the second pixel electrode row.

In an embodiment of the present invention, the plurality of pixel electrodes of the above-mentioned plurality of pixel structures are arranged into a plurality of pixel electrode rows, and the plurality of pixel electrodes in each pixel electrode row are arranged in the second direction, and the plurality of pixel electrodes The rows are arranged in the first direction; the multiple pixel electrode rows include the second electrode pixel row and the third electrode pixel row for displaying blue and green respectively; in the top view of the pixel array substrate, the transfer line is arranged on the second electrode between the pixel row and the third pixel electrode row.

In an embodiment of the present invention, the plurality of pixel structures described above are arranged in a plurality of pixel electrode rows, the plurality of pixel electrodes in each pixel electrode row are arranged in the second direction, and the plurality of pixel electrode rows are arranged in the first direction. Arranged upwards; multiple pixel electrode rows include the first pixel electrode row and the third pixel electrode row for displaying red and green respectively; in the top view of the pixel array substrate, the transfer lines are arranged between the first pixel electrode row and the third pixel between the electrode rows.

In an embodiment of the present invention, the above thin film transistor further includes a semiconductor pattern, two different regions of the semiconductor pattern are electrically connected to the source and the drain, and the semiconductor pattern is disposed between the gate and the substrate.

In an embodiment of the present invention, the above thin film transistor further includes a semiconductor pattern, two different regions of the semiconductor pattern are electrically connected to the source and the drain, and the gate is disposed between the semiconductor pattern and the substrate.

Description of drawings

FIG. 1 is a schematic top view of a pixel array substrate 100 according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a pixel array substrate 100 according to an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of a pixel array substrate 100 according to an embodiment of the present invention.

FIG. 4 is a schematic top view of a pixel array substrate 100A according to an embodiment of the present invention.

FIG. 5 is a schematic top view of a pixel array substrate 100B according to an embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of a pixel array substrate 100B according to an embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of a pixel array substrate 100B according to an embodiment of the present invention.

Explanation of reference signs:

100, 100A, 100B: pixel array substrate

110: base

120: buffer layer

130: gate insulation layer

132, 134, 142, 144: contact window

140: interlayer dielectric layer

150: first insulating layer

160: common electrode layer

170: second insulating layer

182: pixel electrode

182a: Slit

184: Bridge element

190: third insulating layer

C: pixel electrode row

Cr: the first pixel electrode row

Cb: second pixel electrode row

Cg: the third pixel electrode row

DL: data line

GL: gate line

gl: adapter cable

PX: pixel structure

PXA: the first type of pixel structure

PXB: the second type of pixel structure

R, Rn, Rn+1: pixel columns

SM: Shading pattern

T: thin film transistor

Ta: source

Tb: Drain

Tc: gate

Td: semiconductor pattern

x: the first direction

y: the second direction

I-I', II-II', III-III', IV-IV': broken line

Detailed ways

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and description to refer to the same or like parts.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that other elements exist between two elements.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.

FIG. 1 is a schematic top view of a pixel array substrate 100 according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a pixel array substrate 100 according to an embodiment of the present invention. Fig. 2 corresponds to the section line I-I' of Fig. 1 .

FIG. 3 is a schematic cross-sectional view of a pixel array substrate 100 according to an embodiment of the present invention. Fig. 2 corresponds to the section line II-II' of Fig. 1 .

Referring to FIG. 1 , FIG. 2 and FIG. 3 , the pixel array substrate 100 includes a base 110 . In this embodiment, the material of the substrate 110 is glass, for example. However, the present invention is not limited thereto. According to other embodiments, the material of the substrate 110 may also be quartz, organic polymer, or opaque/reflective material (such as: wafer, ceramic, etc.), or other applicable Material.

Referring to FIG. 1 and FIG. 3 , the pixel array substrate 100 further includes a plurality of data lines DL and a plurality of gate lines GL disposed on the base 110 . Referring to FIG. 1 , a plurality of data lines DL are arranged in a first direction x, and a plurality of gate lines GL are arranged in a second direction y, wherein the first direction x and the second direction y intersect. For example, in this embodiment, the first direction x and the second direction y may be perpendicular, but the invention is not limited thereto.

Please refer to FIG. 1 , FIG. 2 and FIG. 3 , in addition, the data lines DL and the gate lines GL belong to different film layers. For example, in this embodiment, the gate line GL can selectively belong to the first metal layer, and the data line DL can selectively belong to the second metal layer, but the invention is not limited thereto.

Based on the consideration of conductivity, in this embodiment, the data lines DL and the gate lines GL are made of metal materials. However, the present invention is not limited thereto. According to other embodiments, the data lines DL and the gate lines GL may also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, and oxynitrides of metal materials. , or stacked layers of metal materials and other conductive materials.

Please refer to FIG. 1 , the pixel array substrate 100 further includes a plurality of pixel structures PX disposed on the base 110 . A plurality of pixel structures PX can be arranged into a plurality of pixel columns R. A plurality of pixel structures PX of each pixel row R are arranged in a first direction x, and a plurality of pixel rows R are arranged in a second direction y.

Please refer to FIG. 1 , each pixel structure PX includes a thin film transistor T, a pixel electrode 182 and a bridge element 184 . 1 and 2, the thin film transistor T includes a source Ta, a drain Tb, a gate Tc, a semiconductor pattern Td, and a gate insulating layer 130. The gate insulating layer 130 is disposed between the gate Tc and the semiconductor pattern Td. Two different regions of the pattern Td are electrically connected to the source Ta and the drain Tb respectively, and the source Ta and the gate Tc are respectively electrically connected to a corresponding data line DL and a corresponding gate line GL. Referring to FIG. 2, in this embodiment, the thin film transistor T may optionally include an interlayer dielectric layer 140, wherein the interlayer dielectric layer 140 is disposed on the gate insulating layer 130 and covers the gate Tc, the source Ta The drain electrode Tb can be electrically connected to two different regions of the semiconductor pattern Td through the plurality of contact windows 142 of the interlayer dielectric layer 140 and the plurality of contact windows 132 of the gate insulating layer 130 . Referring to FIG. 1 , the pixel electrode 182 is disposed outside the drain Tb of the thin film transistor T, and the bridge element 184 is electrically connected to the drain Tb of the thin film transistor T and the pixel electrode 182 .

Referring to FIG. 2 , in this embodiment, the semiconductor pattern Td of the thin film transistor T can be selectively disposed between the gate Tc and the substrate 110 . In other words, the thin film transistor T of this embodiment may be a top gate thin film transistor (top gate TFT), but the present invention is not limited thereto.

In this embodiment, the gate Tc may selectively belong to the first metal layer, and the source Ta and the drain Tb may selectively belong to the second metal layer, but the invention is not limited thereto. In this embodiment, the material of the semiconductor pattern Td is, for example, low temperature polysilicon (LTPS). However, the present invention is not limited thereto. In other embodiments, the material of the semiconductor pattern Td can also be amorphous silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (for example: indium zinc oxide, indium gallium zinc oxide, or other suitable materials, or a combination of the above), or other suitable materials.

Please refer to FIG. 1 and FIG. 2. In this embodiment, the pixel array substrate 100 may optionally include a light-shielding pattern SM and a buffer layer 120. The light-shielding pattern SM is disposed on the base 110. The buffer layer 120 covers the light-shielding pattern SM. The thin film The semiconductor pattern Td of the transistor T can be selectively disposed on the buffer layer 120 and overlapped with the light-shielding pattern SM, but the invention is not limited thereto.

Referring to FIG. 2 , in this embodiment, the pixel array substrate 100 further includes a first insulating layer 150 , a common electrode layer 160 and a second insulating layer 170 . Please refer to FIG. 1 and FIG. 2, the first insulating layer 150 is disposed on a plurality of thin film transistors T of a plurality of pixel structures PX, the common electrode layer 160 is disposed on the first insulating layer 150, and the second insulating layer 170 is disposed on the common electrode. On the layer 160 , the pixel electrode 182 of each pixel structure PX can be disposed on the second insulating layer 170 and have a plurality of slits 182 a , and the plurality of slits 182 a overlap the common electrode layer 160 .

For example, in this embodiment, the common electrode layer 160 can belong to the first transparent conductive layer, which includes metal oxides, such as: indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, Indium germanium zinc oxide, other suitable oxides, or a stacked layer of at least two of the above, but the present invention is not limited thereto; the pixel electrode 182 may belong to the second transparent conductive layer, which includes metal oxide, for example: Indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or stacked layers of at least two of the above, but the present invention is not limited thereto . In addition, in this embodiment, the bridging element 184 and the pixel electrode 182 may belong to the same film layer and be directly connected, but the present invention is not limited thereto.

Referring to FIG. 1 and FIG. 3 , the pixel array substrate 100 further includes a plurality of transfer wires gl disposed on the base 110 . Referring to FIG. 1 , a plurality of transfer lines gl are arranged in a first direction x and are electrically connected to a plurality of gate lines GL arranged in a second direction y.

Please refer to FIG. 1, FIG. 2 and FIG. 3. For example, in this embodiment, multiple gate lines GL can selectively belong to the first metal layer, and multiple transfer lines gl can selectively belong to the second metal layer. layer, an interlayer dielectric layer 140 is provided between the first metal layer and the second metal layer, and the interlayer dielectric layer 140 has a plurality of contact windows 144 (marked in FIG. 1 ), and a plurality of transfer lines gl can pass through the interlayer The plurality of contact windows 144 of the dielectric layer 140 are electrically connected to the plurality of gate lines GL, but the invention is not limited thereto.

Please refer to FIG. 1, each data line DL has an opposite first side (for example: right side) and a second side (for example: left side), the source Ta of the thin film transistor T of a pixel structure PX of a pixel row Rn The source Ta of the thin film transistor T of a pixel structure PX of the next pixel row Rn+1 is electrically connected to the same data line DL, and the drain Tb of the thin film transistor T of the pixel structure PX of the pixel row Rn is connected to the next pixel row The drain Tb of the thin film transistor T of the pixel structure PX of Rn is located on the first side (for example: the right side) of the same data line DL, and the pixel electrode 182 of the pixel structure PX of the pixel row Rn is connected to the pixel of the next pixel row Rn+1. The pixel electrodes 182 of the structure PX are respectively located on the second side (for example: the left side) and the first side (for example: the right side) of the same data line DL, and the bridge element 184 of the pixel structure PX of the pixel row Rn spans the same data line DL. Line DL and a transfer line gl. In short, in this embodiment, the plurality of pixel electrodes 182 of the plurality of pixel structures PX electrically connected to the same data line DL are substantially arranged in a zigzag. Therefore, the aperture ratio of the pixel array substrate 100 can be increased.

1 and 3, in this embodiment, the bridge element 184 of the pixel structure PX of the pixel row Rn is disposed on the second insulating layer 170, and the common electrode layer 160 is disposed on the bridge of the pixel structure PX of the pixel row Rn. Between the element 184 and the transfer line gl. The common electrode layer 160 can be used as a shielding layer to reduce the coupling effect between the transfer line gl and the bridge element 184, and prevent the gate drive signal of the transfer line gl from excessively affecting the potential of the pixel electrode 182 electrically connected to the bridge element 184. . Therefore, the pixel array substrate 100 not only has a high aperture ratio, but also improves the problem of diagonal stripes.

In this embodiment, the pixel electrode 182 of the pixel structure PX of the pixel row Rn is disposed on the second insulating layer 170, and the common electrode layer 160 is disposed between the pixel electrode 182 of the pixel structure PX of the pixel row Rn and the transfer line gl . In other words, the common electrode layer 160 can be a shielding layer between the pixel electrode 182 and the transfer line gl to reduce the influence of the gate driving signal of the transfer line gl on the potential of the pixel electrode 182 .

Referring to FIG. 1, in this embodiment, the bridge element 184 of the pixel structure PX of the pixel row Rn is intersected with the data line DL, and the bridge element 184 of the pixel structure PX of the next pixel row Rn+1 is arranged outside the data line DL and does not overlap the data line DL. In other words, in this embodiment, the plurality of pixel structures PX can be divided into a plurality of first-type pixel structures PXA and a plurality of second-type pixel structures PXB, wherein the bridge element 184 of each first-type pixel structure PXA spans the data line DL, the bridging element 184 of each second-type pixel structure PXB does not cross the data line DL. For example, in this embodiment, the pixel structure PX with an odd number of pixel columns R (for example: Rn) can be the first-type pixel structure PXA, and the pixel structure PX for an even number of pixel columns R (for example: Rn+1) It may be a second-type pixel structure PXB. In other words, the first-type pixel structures PXA and the second-type pixel structures PXB are alternately arranged in the second direction y.

Please refer to FIG. 1 , in this embodiment, a plurality of pixel electrodes 182 of a plurality of pixel structures PX are arranged in a plurality of pixel electrode rows C, and a plurality of pixel electrodes 182 of each pixel electrode row C are arranged in the second direction y , and a plurality of pixel electrode rows C are arranged in the first direction x, and the plurality of pixel electrode rows C include the first pixel electrode row Cr, the second pixel electrode row Cb and the second pixel electrode row Cb for displaying red, blue and green respectively. Three pixel electrode rows Cg. In this embodiment, in the top view of the pixel array substrate 100, the transfer line gl can be selectively arranged between the first pixel electrode row Cr and the second pixel electrode row Cb for displaying red and blue respectively, but The present invention is not limited thereto.

It must be noted here that the following embodiments use the component numbers and part of the content of the previous embodiments, wherein the same numbers are used to denote the same or similar components, and descriptions of the same technical content are omitted. For the description of omitted parts, reference may be made to the aforementioned embodiments, and the following embodiments will not be repeated.

FIG. 4 is a schematic top view of a pixel array substrate 100A according to an embodiment of the present invention.

The pixel array substrate 100A in FIG. 4 is similar to the pixel array substrate 100 in FIG. 1 , the difference between the two lies in that the setting positions of the transfer lines gl are different.

Please refer to FIG. 4. Specifically, in this embodiment, in the top view of the pixel array substrate 100A, the plurality of transfer lines gl are arranged on the first pixel electrode row Cr for displaying red and blue and the second pixel electrode row Cr. In addition to between the electrode rows Cb, it is further arranged between the second pixel electrode row Cb and the third pixel electrode row Cg for displaying blue and green, and between the first pixel electrode row Cr and the third pixel electrode row for displaying red and green. Between the three pixel electrode rows Cg.

FIG. 5 is a schematic top view of a pixel array substrate 100B according to an embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of a pixel array substrate 100B according to an embodiment of the present invention. Fig. 6 corresponds to section line III-III' of Fig. 5 .

FIG. 7 is a schematic cross-sectional view of a pixel array substrate 100B according to an embodiment of the present invention. Fig. 7 corresponds to section line IV-IV' of Fig. 5 .

The pixel array substrate 100B in FIG. 5 , FIG. 6 and FIG. 7 is similar to the pixel array substrate 100 in FIG. 1 , FIG. 2 and FIG. 3 , the difference between them is that the thin film transistors T are different.

Please refer to FIG. 5 , FIG. 6 and FIG. 7 , specifically, in this embodiment, the gate Tc of the thin film transistor T is disposed between the semiconductor pattern Td of the thin film transistor T and the substrate 110 . In other words, the thin film transistor T of this embodiment may be a bottom gate thin film transistor (bottom gate TFT). In addition, in this embodiment, the material of the semiconductor pattern Td of the thin film transistor T is, for example, amorphous silicon (Amorphous silicon).

In addition, in this embodiment, the pixel array substrate 100B may not include the light-shielding pattern SM of the pixel array substrate 100 , the buffer layer 120 and the interlayer dielectric layer 140 . In this embodiment, the pixel array substrate 100B includes a third insulating layer 190 (shown in FIGS. 6 and 7 ), which is disposed between the second metal layer to which the transfer line gl and the data line DL belong and the first insulating layer 150 . In addition, in this embodiment, the transfer line gl of the pixel array substrate 100B is electrically connected to the gate line GL through the contact window 134 (shown in FIG. 5 and FIG. 7 ) of the gate insulating layer 130 .

The pixel array substrate 100B has similar technical effects and advantages to the aforementioned pixel array substrate 100 , which will not be repeated here.

Claims (9)

1. A pixel array substrate, comprising:

a substrate;

a plurality of data lines arranged on the substrate and arranged in a first direction;

a plurality of gate lines disposed on the substrate and arranged in a second direction, wherein the first direction is staggered with the second direction;

the pixel structures are arranged on the substrate, wherein each pixel structure comprises a thin film transistor, a pixel electrode and a bridging element, a source electrode and a grid electrode of the thin film transistor are respectively and electrically connected to a corresponding data line and a corresponding grid line, the pixel electrode is arranged outside a drain electrode of the thin film transistor, and the bridging element is electrically connected with a drain electrode of the thin film transistor and the pixel electrode; and

the plurality of patch cords are arranged on the substrate, are arranged in the first direction and are electrically connected to the gate lines;

the pixel structures are arranged into a plurality of pixel rows, the pixel structures of each pixel row are arranged in the first direction, and the pixel rows are arranged in the second direction;

each data line is provided with a first side and a second side which are opposite;

the source electrode of the thin film transistor of the pixel structure of one pixel row and the source electrode of the thin film transistor of the pixel structure of the next pixel row are electrically connected to the same data line;

the drain electrode of the thin film transistor of the pixel structure of one pixel row and the drain electrode of the thin film transistor of the pixel structure of the next pixel row are positioned on the first side of the same data line;

the pixel electrode of the pixel structure of the pixel row and the pixel electrode of the pixel structure of the next pixel row are respectively positioned on the second side and the first side of the same data line;

the bridging element of the pixel structure of the pixel row spans the same data line and one of the patch lines.

2. The pixel array substrate of claim 1, further comprising:

the first insulating layer is arranged on the thin film transistors of the pixel structures;

a common electrode layer disposed on the first insulating layer; and

the second insulating layer is arranged on the common electrode layer, wherein the bridging element of the pixel structure of the pixel row is arranged on the second insulating layer, and the common electrode layer is arranged between the bridging element of the pixel structure of the pixel row and the patch cord.

3. The pixel array substrate of claim 2, wherein the pixel electrode of the pixel structure of the pixel row is disposed on the second insulating layer, and the common electrode layer is disposed between the pixel electrode of the pixel structure of the pixel row and the patch cord.

4. The pixel array substrate of claim 1, wherein the bridge elements of the pixel structures of the pixel row are interleaved with the same data line, and the bridge elements of the pixel structures of the next pixel row are disposed outside the same data line and do not overlap the same data line.

5. The pixel array substrate of claim 1, wherein the plurality of pixel electrodes of the pixel structures are arranged in a plurality of pixel electrode rows, the plurality of pixel electrodes of each of the pixel electrode rows are arranged in the second direction, and the plurality of pixel electrode rows are arranged in the first direction; the pixel electrode rows comprise a first pixel electrode row and a second pixel electrode row which are respectively used for displaying red and blue; in a top view of the pixel array substrate, the patch cord is disposed between the first pixel electrode row and the second pixel electrode row.

6. The pixel array substrate of claim 1, wherein the plurality of pixel electrodes of the pixel structures are arranged in a plurality of pixel electrode rows, the plurality of pixel electrodes of each of the pixel electrode rows are arranged in the second direction, and the plurality of pixel electrode rows are arranged in the first direction; the pixel electrode rows comprise a second electrode pixel row and a third pixel electrode row which are respectively used for displaying blue and green; in a top view of the pixel array substrate, the patch cord is disposed between the second electrode pixel row and the third pixel electrode row.

7. The pixel array substrate of claim 1, wherein the pixel structures are arranged in a plurality of pixel electrode rows, the plurality of pixel electrodes of each pixel electrode row are arranged in the second direction, and the plurality of pixel electrode rows are arranged in the first direction; the pixel electrode rows comprise a first pixel electrode row and a third pixel electrode row which are respectively used for displaying red and green; in a top view of the pixel array substrate, the patch cord is disposed between the first pixel electrode row and the third pixel electrode row.

8. The pixel array substrate of claim 1, wherein the thin film transistor further comprises a semiconductor pattern, wherein different two regions of the semiconductor pattern are electrically connected to the source electrode and the drain electrode, respectively, and the semiconductor pattern is disposed between the gate electrode and the substrate.

9. The pixel array substrate of claim 1, wherein the thin film transistor further comprises a semiconductor pattern, wherein different two regions of the semiconductor pattern are electrically connected to the source electrode and the drain electrode, respectively, and the gate electrode is disposed between the semiconductor pattern and the substrate.

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