CN108922893A - pixel array substrate - Google Patents

Abstract

A pixel array substrate includes a substrate, data lines, multiple scan lines, multiple sub-pixel structures, a first insulating layer, a second insulating layer, touch wiring, a third insulating layer and a common electrode. Multiple sub-pixel structures are electrically connected to the same data line. Multiple sub-pixel structures are used to display different colors and are electrically connected to multiple scan lines respectively. Each sub-pixel structure includes active elements and pixel electrodes. The pixel electrode is disposed on the first insulation layer. The second insulation layer covers the pixel electrode. The touch traces are arranged on the second insulation layer. The third insulation layer covers a part of the touch trace. The common electrode is disposed on the third insulating layer and has a plurality of branches overlapping the pixel electrode.

Description

Pixel Array Substrate

technical field

The present invention relates to a substrate, and in particular to a pixel array substrate.

Background technique

In recent years, display panels have played an indispensable role in daily life, especially in mobile communication devices, display panels equipped with touch functions have become a mainstream trend. While related panel manufacturers are constantly improving the display quality of touch display panels, how to maintain production costs and make products more competitive is also one of the directions that each factory is committed to. Among them, the Tri-gate (Tri-gate) display panel has relatively good price competitiveness due to the use of a small number of source driver chips (Source IC). However, the pixel resolution of the display panel is continuously improved, so that the three-gate display panel faces the problem of insufficient charging rate.

Contents of the invention

An embodiment of the present invention provides a pixel array substrate with better performance.

A pixel array substrate according to an embodiment of the present invention includes a substrate, data lines, multiple scan lines, multiple sub-pixel structures, a first insulating layer, a second insulating layer, touch wiring, a third insulating layer, and a common electrode. The substrate has a display area and a peripheral area outside the display area. The data lines are arranged on the substrate. A plurality of scanning lines are arranged on the substrate and intersect with the data lines. Multiple sub-pixel structures are arranged in the display area of the substrate and are electrically connected to the same data line, wherein the multiple sub-pixel structures are respectively used to display different colors and are respectively electrically connected to different scanning lines. Each sub-pixel structure includes an active element and a pixel electrode electrically connected to the active element. The first insulating layer covers the active element, wherein the pixel electrode is disposed on the first insulating layer. The second insulating layer is disposed on the first insulating layer and covers the pixel electrodes. The touch wires are disposed on the second insulating layer. The third insulating layer is disposed on the second insulating layer and covers a part of the touch wiring. The common electrode is disposed on the third insulating layer, is electrically connected with the touch wire, and has a plurality of branches overlapping with the pixel electrodes.

A pixel array substrate according to an embodiment of the present invention, including a substrate, data lines, scanning lines, sub-pixel structures, peripheral wiring, a first insulating layer, a first transfer pattern, a second insulating layer, and touch wiring , a third insulating layer, a common electrode and a second transfer pattern. The substrate has a display area and a peripheral area outside the display area. The substrate has a display area and a peripheral area outside the display area. The data lines are arranged on the substrate. The scanning lines are arranged on the substrate and intersect with the data lines. The sub-pixel structure is arranged in the display area of the substrate and is electrically connected with the data line and the scan line. The sub-pixel structure includes an active element and a pixel electrode electrically connected to the active element. The peripheral wiring is arranged in the peripheral area of the substrate and has a reference potential. The first insulating layer covers the active element and the peripheral wiring, and has a first contact window overlapping with the peripheral wiring, wherein the pixel electrode is arranged on the first insulating layer located in the display area. The first transfer pattern is disposed on the first insulating layer in the peripheral area and is electrically connected to the peripheral wiring through the first contact window. The second insulating layer is disposed on the first insulating layer, covers the pixel electrode and the first transfer pattern, and has a second contact window overlapping with the first transfer pattern. The touch wires are disposed on the second insulating layer. The third insulating layer is disposed on the second insulating layer, covers a part of the touch trace, and has a third contact window communicating with the second contact window. The common electrode is disposed on the third insulating layer, is electrically connected with the touch wire, and has a plurality of branches overlapping with the pixel electrodes. The second transfer pattern is disposed on the third insulating layer located in the peripheral area, and is electrically connected to the first transfer pattern through the second contact window and the third contact window, and the common electrode is connected to the first transfer pattern through the first transfer pattern and the second contact window. The transfer pattern is electrically connected to the surrounding traces.

In an embodiment of the present invention, the thickness of the first insulating layer of the above-mentioned pixel array substrate is greater than the thickness of the second insulating layer and the thickness of the third insulating layer, wherein the thickness of the first insulating layer is 4000 angstroms to 10000 angstroms, The second insulating layer has a thickness of 1000 angstroms to 6000 angstroms, and the third insulating layer has a thickness of 1000 angstroms to 6000 angstroms.

In an embodiment of the present invention, the above-mentioned touch wires and data lines of the pixel array substrate extend in a first direction, the pixel electrode has a width W1 in the first direction, and the pixel electrode has a width W1 in the first direction. The two directions have a width W2, and W1<W2.

In an embodiment of the present invention, the plurality of branches of the common electrode of the above-mentioned pixel array substrate includes a plurality of first straight segments, a plurality of second straight segments, and a plurality of curved segments, and the extension direction of the plurality of first straight segments Different from the extension directions of the second straight segments, the bent segments are respectively connected between the first straight segments and the second straight segments, and the bent segments overlap with the touch traces.

In an embodiment of the present invention, the above-mentioned pixel array substrate further includes peripheral wiring, a first transfer pattern, and a second transfer pattern. The peripheral traces are arranged on the peripheral region of the substrate, wherein the first insulating layer is disposed on the peripheral traces and has a first contact window overlapping with the peripheral traces. The first transfer pattern is disposed on the first insulating layer in the peripheral area and is electrically connected to the peripheral wiring through the first contact window. The second transfer pattern is disposed on the third insulating layer located in the peripheral area, wherein the second insulating layer has a second contact window, the third insulating layer has a third contact window, the second contact window communicates with the third contact window, and the second contact window communicates with the third contact window. The two transfer patterns are electrically connected to the first transfer pattern through the second contact window and the third contact window, and the common electrode is electrically connected to the peripheral wiring through the first transfer pattern and the second transfer pattern, wherein the second transfer pattern The contact window is aligned with the third contact window.

In an embodiment of the present invention, the active element of the pixel array substrate includes a thin film transistor having a gate and a semiconductor pattern, and the pixel array substrate further includes a fourth insulating layer. The fourth insulating layer is disposed between the gate and the semiconductor pattern, wherein the fourth insulating layer has a fourth contact window communicating with the first contact window, and the first transfer pattern is connected to the surrounding area through the first contact window and the fourth contact window. The traces are electrically connected, wherein the first contact window is aligned with the fourth contact window.

Based on the above, the second insulating layer and the third insulating layer are disposed between the common electrode and the pixel electrode of the pixel array substrate in the embodiment of the present invention, so as to increase the distance between the common electrode and the pixel electrode. When the distance between the common electrode and the pixel electrode increases, the storage capacitance between the pixel electrode and the common electrode can be reduced, thereby increasing the charging rate. Thus, a low-cost and high-performance pixel array substrate can be realized.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a pixel array substrate according to an embodiment of the present invention.

FIG. 2 is a schematic top view of the pixel array substrate in FIG. 1 .

List of reference signs

10: Pixel array substrate

100: Substrate

110: The fourth insulating layer

110b: fourth contact window

120: first insulating layer

120a, 120b: first contact window

130: pixel electrode

131: The first transfer pattern

140: second insulating layer

140b: second contact window

150: third insulating layer

150a, 150b: third contact window

160: common electrode

161: branch

161a: First straight line segment

161b: Second straight line segment

161c, 161d, 161e: curved sections

162: Second transfer pattern

AA: display area

CH: semiconductor pattern

D1: first direction

D2: Second direction

D3: vertical projection direction

DL: data line

H1, H2, H3: Thickness

I: area

L1, L2, L3: Distance

PA: Peripheral Area

PL: Peripheral routing

PX1, PX2, PX3: sub-pixel structure

SL: scan line

T: active component

D: Drain

G: grid

TL: touch trace

S: source

W1, W2: Width

A-A', B-B': broken line

Detailed ways

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals (reference numerals) are used in the drawings and description to refer to the same or like parts.

FIG. 1 is a schematic cross-sectional view of a pixel array substrate 10 according to an embodiment of the present invention. FIG. 2 is a schematic top view of the pixel array substrate 10 in FIG. 1 . In particular, the cross section of the display area AA of the pixel array substrate 10 in FIG. 1 corresponds to the section line A-A' and section line B-B' in FIG. 2 .

1 and 2, the pixel array substrate 10 includes a substrate 100, a data line DL, a plurality of scan lines SL1, SL2, SL3, a plurality of sub-pixel structures PX1, PX2, PX3 and touch lines TL. The substrate 100 has a display area AA and a peripheral area PA outside the display area AA. In this embodiment, the data lines DL and the touch traces TL substantially extend in the first direction D1, and the scan lines SL3, SL2, and SL1 substantially extend in the second direction D2 and follow the first direction D1 sequentially. arranged on the substrate 100 . For example, in this embodiment, the first direction D1 and the second direction D2 are substantially perpendicular to each other, but the invention is not limited thereto.

A plurality of sub-pixel structures PX1 , PX2 , PX3 are disposed in the display area AA of the substrate 100 . Each sub-pixel structure PX1 , PX2 , PX3 is electrically connected to a corresponding data line DL and a corresponding scan line SL1 , SL2 or SL3 . In particular, in this embodiment, multiple sub-pixel structures PX1, PX2, and PX3 respectively used to display different colors (for example: red, green, and blue) are electrically connected to the same data line DL, and are respectively connected to different The multiple scan lines SL1, SL2, SL3 are electrically connected. That is to say, the display panel using the pixel array substrate 10 of this embodiment may be a tri-gate type (tri-gate, tri-gate type).

In this embodiment, each sub-pixel structure PX1, PX2, PX3 includes an active element T and a pixel electrode 130 electrically connected to the active element T, wherein the active element T of each sub-pixel structure PX1, PX2, PX3 is connected to the corresponding One of the data lines DL is electrically connected to one of the corresponding scan lines SL1, SL2 or SL3. In this embodiment, the pixel electrode 130 of the sub-pixel structures PX1, PX2, PX3 has a width W1 (marked in FIG. 2 ) in the first direction D1, and the pixel electrode 130 has a width W2 (marked in FIG. 2 ) in the second direction D2. 2 ), and the width W2 of the pixel electrode 130 is greater than the width W1, but the present invention is not limited thereto.

Referring to FIG. 1 , in this embodiment, the active device T includes a gate G, a source S, a drain D and a semiconductor pattern CH. The gate G is disposed on the substrate 100 and is electrically connected to a corresponding scan line SL1 , SL2 or SL3 . The source S is disposed on the substrate 100 and is electrically connected to a corresponding data line DL. The source S and the drain D are respectively electrically connected to two different regions of the semiconductor pattern CH. For example, in this embodiment, the structure of the semiconductor pattern CH can be single-layer or multi-layer; the material of the semiconductor pattern CH can include amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxides Semiconductor materials (for example: indium zinc oxide, indium gallium zinc oxide, or other suitable materials, or a combination of the above), or other suitable materials, or containing dopant in the above materials, or the above The combination.

In this embodiment, the pixel array substrate 10 further includes a fourth insulating layer 110 disposed between the gate G and the semiconductor pattern CH. In this embodiment, the semiconductor pattern CH may be selectively disposed on the gate G, thereby forming a bottom-gate TFT. However, the present invention is not limited thereto. According to other embodiments, the active element T may also be a top-gate TFT or other suitable types of TFTs.

Please refer to FIG. 1 and FIG. 2. In this embodiment, the materials of the multiple scan lines SL1, SL2, SL3 and the gate G can be the same; that is, the multiple scan lines SL1, SL2, SL3 and the gate G can be made of The same film layer is formed. In addition, in this embodiment, the materials of the data line DL, the source S, and the drain D may be the same; that is, the data line DL, the source S, and the drain D may be formed of the same film layer. In this embodiment, based on the consideration of conductivity, the materials of the data lines DL, the scan lines SL1 , SL2 , SL3 , the gate G, the source S and the drain D are generally metal materials. However, the present invention is not limited thereto. According to other embodiments, data lines DL, scan lines SL1, SL2, SL3, gate G, source S, and drain D may also use other conductive materials, such as: alloy, Nitride of metal material, oxide of metal material, oxynitride of metal material, or other suitable materials, or stacked layers of metal material and other conductive materials.

In this embodiment, the pixel array substrate 10 further includes a first insulating layer 120 . The first insulating layer 120 covers the active device T, a plurality of data lines DL and part of the fourth insulating layer 110, and has a first contact window 120a located in the display area AA. In this embodiment, the first contact window 120 a penetrates through the first insulating layer 120 to expose part of the surface of the drain D. Referring to FIG. The pixel electrode 130 is disposed on the first insulating layer 120 and fills the first contact window 120a of the first insulating layer 120 to be electrically connected to the drain D of the active device T. Referring to FIG.

Referring to FIG. 1 , in this embodiment, the pixel array substrate 10 further includes a second insulating layer 140 . The second insulating layer 140 is disposed on the first insulating layer 120 and covers the pixel electrode 130 and part of the first insulating layer 120 . The touch trace TL is disposed on the second insulating layer 140 . The second insulating layer 140 is disposed between the film layer to which the touch trace TL belongs and the film layer to which the pixel electrode 130 belongs. In particular, in this embodiment, the first insulating layer 120 and the second insulating layer 140 are sandwiched between the touch trace TL and the scan line SL1 , so that the touch trace TL and the scan line SL1 are aligned in the vertical projection direction D3 Therefore, the parasitic capacitance formed by the touch trace TL and the scan line SL1 can be reduced. Similarly, since the first insulating layer 120 and the second insulating layer 140 are interposed between the touch trace TL and the data line DL, the distance between the touch trace TL and the data line DL in the vertical projection direction D3 (not shown in FIG. mark) is far away, so the stray capacitance formed by the touch trace TL and the data line DL can be reduced.

It is worth mentioning that the pixel array substrate 10 of this embodiment adopts a tri-gate structure, so the scanning lines SL1, SL2, and SL3 have a high potential and the active element T is turned on for a short time, that is, The charging time is shorter. For related technologies of the Tri-gate architecture, reference may be made to the content of US Patent Application Publication No. US20100289792A1, the content of which is incorporated by reference in the present invention, but is not intended to limit the present invention. Through the above arrangement, the stray capacitance formed by the touch trace TL and the scan line SL1 and the stray capacitance formed by the touch trace TL and the data line DL can be reduced, so the pixel array substrate 10 can be used in three Under the premise of Tri-gate structure, it has stable signal transmission. In addition, the charging voltage Vti of the data line DL at the charging time ti of the i-th stage satisfies the following formula: Vti=V×{1-exp[-ti/(RC)]}, where V is the original charging voltage of the data line DL, R is the resistance value of the charging circuit, and C is the storage capacitance value formed by the common electrode 160 and the pixel electrode 130. It can be known from the above formula that the storage capacitance value C is inversely proportional to the charging rate Vti/V. This embodiment has a smaller common electrode 160 The storage capacitor formed with the pixel electrode 130 has a relatively large charging ratio. On the other hand, according to the power consumption rate formula, power consumption P=F×Cdata*V ² , where F is the clock frequency, V is the supply voltage, and Cdata is the data line DL, scan lines SL1, SL2, SL3 and touch As for the parasitic capacitance between the traces TL, it can be seen from the above formula that the parasitic capacitance Cdata is proportional to the power consumption P. This embodiment has a relatively small capacitance formed by the data line DL and the touch trace TL, so it has a relatively small capacitance. Small power consumption. Therefore, the display panel using the pixel array substrate 10 still has good display quality on the premise of low cost.

Referring to FIG. 1 , the pixel array substrate 10 further includes a third insulating layer 150 . In this embodiment, the third insulating layer 150 is disposed on the second insulating layer 140 and covers part of the touch trace TL and part of the second insulating layer 140 . More specifically, the third insulating layer 150 has a third contact window 150a, and the third contact window 150a penetrates through the third insulating layer 150 to expose part of the surface of the touch trace TL. In this embodiment, the first insulating layer 120, the second insulating layer 140, and the third insulating layer 150 have thicknesses H1, H2, and H3 respectively in the vertical projection direction D3, wherein the thickness H1 of the first insulating layer 120 is greater than that of the second insulating layer 120. The thickness H2 of the insulating layer 140 and the thickness H3 of the third insulating layer 150 are not limited thereto. For example, in this embodiment, the thickness H1 of the first insulating layer 120 may be 4000 angstroms to 10000 angstroms, the thickness H2 of the second insulating layer 140 may be 1000 angstroms to 6000 angstroms, and the thickness H3 of the third insulating layer 150 may be 1000 angstroms to 6000 angstroms, but the present invention is not limited thereto. In this embodiment, the material of the first insulating layer 120, the second insulating layer 140, the third insulating layer 150 and the fourth insulating layer 110 may include inorganic materials (for example: silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or stacked layers of at least two of the above materials), organic materials, or other suitable materials, or a combination of the above.

In this embodiment, the common electrode 160 is disposed on the third insulating layer 150 and fills in the third contact window 150 a of the third insulating layer 150 to be electrically connected to the touch trace TL. That is to say, the third insulating layer 150 is disposed between the common electrode 160 and the touch trace TL. For example, in this embodiment, the pixel electrode 130 and the common electrode 160 can both be penetrating electrodes, and the material of the penetrating electrodes includes metal oxides, such as indium tin oxide, indium zinc oxide, aluminum Tin oxide, aluminum zinc oxide, or other suitable oxides, or a stacked layer of at least two of the above. However, the present invention is not limited thereto. In another embodiment, the common electrode 160 can be a reflective electrode, and the pixel electrode 130 can be a transmissive electrode, wherein the material of the reflective electrode includes metal with high reflectivity Material.

It is worth mentioning that, in this embodiment, since the second insulating layer 140 and the third insulating layer 150 are interposed between the common electrode 160 and the pixel electrode 130, the common electrode 160 and the pixel electrode 130 are aligned vertically in the projection direction D3. The distance L2 above is relatively long, so the storage capacitance formed by the common electrode 160 and the pixel electrode 130 can be reduced. The distance L2 is, for example, 2000 angstroms to 12000 angstroms. The pixel array substrate 10 of this embodiment adopts a tri-gate structure, so the scan lines SL1 , SL2 , SL3 have high potentials to enable the active element T to be turned on for a short time, that is, the charging time is short. However, through the above arrangement, the storage capacitance formed by the common electrode 160 and the pixel electrode 130 can be reduced, so the pixel array substrate 10 can have a sufficient charging rate ( Charging ratio), so that the display panel using the pixel array substrate 10 has the advantages of low cost and good display quality.

Referring to FIG. 1 and FIG. 2 , in this embodiment, the common electrode 160 has a plurality of branches 161 overlapping with the pixel electrode 130 . Referring to Fig. 2, in this embodiment, a plurality of branches 161 includes a plurality of first straight segments 161a, a plurality of second straight segments 161b and a plurality of curved segments 161c, wherein the extension direction of the first straight segments 161a is the same as that of the second The extension direction of the straight line segment 161b is different, and the curved segment 161c is connected between the first straight line segment 161a and the second straight line segment 161b. In this embodiment, the plurality of branches 161 may further include a plurality of curved sections 161d, 161e, wherein the first straight section 161a is connected between the curved section 161c and the curved section 161d, and the second straight section 161b is connected to the curved section 161c and the curved section 161e.

In this embodiment, the plurality of bent sections 161c of the common electrode 160 overlap with the touch trace TL. That is to say, the touch trace TL is arranged away from the data line DL. Since the distance L3 between the touch trace TL and the data line DL in the direction D2 is far, the noise formed by the touch trace TL and the data line DL The low capacitance value helps to provide a stable signal. In addition, if the pixel array substrate 10 is applied to a liquid crystal display panel, the first straight line segment 161a and the second straight line segment 161b extending in different directions can define a plurality of liquid crystal alignment regions, and the bending point of the curved segment 161c is set at the plurality of liquid crystal alignment regions. On the discontinuation line (Disclination line) between the liquid crystal alignment regions, the touch trace TL overlaps the discontinuation line that cannot contribute to the brightness. At the same time, the setting of the touch trace TL will not excessively affect the transmittance of the liquid crystal display panel. However, the present invention is not limited thereto, and in another embodiment, the touch trace TL can also be disposed at other suitable places away from the data line DL.

Please refer to FIG. 1 , in the present embodiment, the pixel array substrate 10 further includes peripheral traces PL, a first transfer pattern 131 and a second transfer pattern 162 . The peripheral traces PL are disposed in the peripheral area PA of the substrate 100 . In this embodiment, the peripheral wiring PL and the gate G of the active device T, the scanning lines SL1, SL2, and SL3 can be formed of the same film layer, and the peripheral wiring PL and the gate G of the active device T and the scanning line SL1 The materials of , SL2 and SL3 can be the same, but the present invention is not limited thereto. The peripheral trace PL may have a reference potential. In this embodiment, the reference potential is, for example, the ground potential. However, the present invention is not limited thereto, and in other embodiments, the reference potential may also be a fixed potential or other appropriate potentials.

In this embodiment, the first insulating layer 120 is disposed on the peripheral wiring PL and has a first contact window 120b overlapping with the peripheral wiring PL. Similarly, the fourth insulating layer 110 is also disposed on the peripheral wiring PL and has a fourth contact window 110b overlapping with the peripheral wiring PL, wherein the first contact window 120b communicates with the fourth contact window 110b. Especially, in this embodiment, the first contact window 120b and the fourth contact window 110b located in the peripheral area PA can be aligned, that is, the first contact window 120b and the fourth contact window 110b can use the same mask and formed simultaneously in the same etching process, but the invention is not limited thereto.

In this embodiment, the first transfer pattern 131 is disposed on the first insulating layer 120 located in the peripheral area PA and is electrically connected to the peripheral wiring PL through the first contact window 120 b and the fourth contact window 110 b. For example, in this embodiment, the first transfer pattern 131 and the pixel electrode 130 can be formed of the same film layer, and the material of the first transfer pattern 131 and the pixel electrode 130 is the same, but the present invention is not limited thereto .

In this embodiment, the second insulating layer 140 has a second contact window 140b located in the peripheral area PA, the third insulating layer 150 has a third contact window 150b located in the peripheral area PA, the second insulating layer 140 and the third insulating layer 150 respectively have a second contact hole 140 b and a third contact hole 150 b communicating with each other to expose part of the surface of the first transfer pattern 131 . The second transfer pattern 162 is disposed on the third insulating layer 150 located in the peripheral area PA, and is electrically connected to the first transfer pattern 131 through the second contact window 140 b and the third contact window 150 b. In this embodiment, the common electrode 160 can be electrically connected to the peripheral trace PL through the first transfer pattern 131 and the second transfer pattern 162 . In this embodiment, the second contact window 140b is aligned with the third contact window 150b; that is, the second contact window 140b and the third contact window 150b can be formed simultaneously using the same mask and in the same etching process, but The present invention is not limited thereto. In this embodiment, the second transfer pattern 162 and the common electrode 160 can be formed of the same film layer, and the material of the second transfer pattern 162 and the common electrode 160 is the same, but the present invention is not limited thereto.

To sum up, the second insulating layer and the third insulating layer are disposed between the common electrode and the pixel electrode of the pixel array substrate in the embodiment of the present invention, so as to increase the distance between the common electrode and the pixel electrode. When the distance between the common electrode and the pixel electrode increases, the storage capacitance between the pixel electrode and the common electrode can be reduced, thereby increasing the charging rate. Thus, a low-cost and high-performance pixel array substrate can be realized.

Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention, and any ordinary skilled person in the technical field should be able to make some changes without departing from the spirit and scope of the present invention and retouching, so the scope of protection of the present invention should be defined by the appended claims.

Claims (17)

1. A pixel array substrate, comprising: A substrate having a display area and a peripheral area outside the display area; a data line arranged on the substrate; a plurality of scanning lines arranged on the substrate and intersecting with the data lines; and A plurality of sub-pixel structures are arranged in the display area of the substrate and are electrically connected to the data lines, wherein the plurality of sub-pixel structures are respectively used to display different colors, and are electrically connected to the plurality of different scanning lines respectively. Sexually connected, each of the sub-pixel structures includes an active element and a pixel electrode electrically connected to the active element; a first insulating layer covering the active element, wherein the pixel electrode is disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer and covering the pixel electrode; a touch trace, disposed on the second insulating layer; a third insulating layer disposed on the second insulating layer and covering a part of the touch trace; and A common electrode is arranged on the third insulating layer, is electrically connected with the touch wire, and has a plurality of branches overlapping at least one of the pixel electrodes. 2. The pixel array substrate as claimed in claim 1, wherein the second insulating layer and the third insulating layer are disposed between the common electrode and at least one of the pixel electrodes. 3. The pixel array substrate as claimed in claim 1, wherein the first insulating layer and the second insulating layer are disposed between the touch trace and the data line. 4. The pixel array substrate as claimed in claim 1, wherein the first insulating layer and the second insulating layer are disposed between the touch trace and the scan line. 5. The pixel array substrate as claimed in claim 1, wherein the second insulating layer is disposed between the touch wire and at least one of the pixel electrodes. 6. The pixel array substrate as claimed in claim 1, wherein the third insulating layer is disposed between the common electrode and the touch trace. 7. The pixel array substrate as claimed in claim 1, wherein the thickness of the first insulating layer is greater than the thickness of the second insulating layer and the thickness of the third insulating layer, wherein the thickness of the first insulating layer is 4000 angstroms to 10000 angstroms, the thickness of the second insulating layer is 1000 angstroms to 6000 angstroms, and the thickness of the third insulating layer is 1000 angstroms to 6000 angstroms. 8. The pixel array substrate as claimed in claim 1, wherein the touch trace and the data line extend in a first direction, and each of the pixel electrodes has a width W1 in the first direction and is in line with the second A second direction perpendicular to one direction has a width W2, and W1<W2. 9. The pixel array substrate according to claim 1, wherein the plurality of branches of the common electrode comprises a plurality of first straight segments, a plurality of second straight segments and a plurality of curved segments, the plurality of first straight segments The extension direction of the line segment is different from the extension direction of the plurality of second straight line segments, the plurality of curved segments are respectively connected between the plurality of first straight line segments and the plurality of second straight line segments, and the A plurality of curved segments overlap with the touch trace. 10. The pixel array substrate according to claim 1, further comprising: a peripheral trace disposed on the peripheral region of the substrate, wherein the first insulating layer is disposed on the peripheral trace and has a first contact window overlapping with the peripheral trace; a first transfer pattern, disposed on the first insulating layer located in the peripheral region and electrically connected to the peripheral wiring through the first contact window; and A second transfer pattern, disposed on the third insulating layer located in the peripheral area, wherein the second insulating layer has a second contact window, the third insulating layer has a third contact window, the second contact window Communicating with the third contact window, the second transfer pattern is electrically connected to the first transfer pattern through the second contact window and the third contact window, and the common electrode is electrically connected to the first transfer pattern through the first transfer pattern and the first transfer pattern. The two transfer patterns are electrically connected to the peripheral wiring, wherein the second contact hole is aligned with the third contact hole. 11. The pixel array substrate according to claim 10, wherein each of the active elements is a thin film transistor comprising a gate and a semiconductor pattern, and the pixel array substrate further comprises: A fourth insulating layer, disposed between each gate and each semiconductor pattern, wherein the fourth insulating layer has a fourth contact window communicating with the first contact window, and the first transfer pattern Electrically connected to the peripheral wiring through the first contact window and the fourth contact window, wherein the first contact window is aligned with the fourth contact window, the common electrode and at least one of the pixel electrodes are in The distance in a vertical projection direction is 2000 angstroms to 12000 angstroms. 12. A pixel array substrate, comprising: A substrate having a display area and a peripheral area outside the display area; a data line arranged on the substrate; A scanning line is arranged on the substrate and intersects with the data line; and a sub-pixel structure disposed on the display area of the substrate and electrically connected to the data line and the scan line, wherein the sub-pixel structure includes an active element and a pixel electrode electrically connected to the active element; a peripheral wiring arranged in the peripheral area of the substrate; a first insulating layer covering the active element and the peripheral wiring, and having a first contact window overlapping with the peripheral wiring, wherein the pixel electrode is disposed on the first insulating layer located in the display area; a first transfer pattern, disposed on the first insulating layer located in the peripheral region and electrically connected to the peripheral wiring through the first contact window; a second insulating layer, disposed on the first insulating layer, covering the pixel electrode and the first transfer pattern, and having a second contact window overlapping with the first transfer pattern; a touch trace, disposed on the second insulating layer; a third insulating layer, disposed on the second insulating layer, covering a part of the touch trace, and having a third contact window communicated with the second contact window; a common electrode, disposed on the third insulating layer, electrically connected to the touch wiring, and has a plurality of branches overlapping with the pixel electrode; and A second transfer pattern is disposed on the third insulating layer located in the peripheral area, and is electrically connected to the first transfer pattern through the second contact window and the third contact window, and the common electrode is connected to the first transfer pattern through the first contact hole. A transfer pattern and the second transfer pattern are electrically connected to the peripheral wiring. 13. The pixel array substrate as claimed in claim 12, wherein the second contact hole is aligned with the third contact hole. 14. The pixel array substrate according to claim 12, wherein the active element is a thin film transistor comprising a gate and a semiconductor pattern, and the pixel array substrate further comprises: A fourth insulating layer, disposed between the gate and the semiconductor pattern, wherein the fourth insulating layer has a fourth contact window communicating with the first contact window, and the first transfer pattern passes through the first contact window The contact window and the fourth contact window are electrically connected to the peripheral wiring. 15. The pixel array substrate as claimed in claim 14, wherein the first contact hole is aligned with the fourth contact hole. 16. The pixel array substrate as claimed in claim 12, wherein the touch trace and the data line extend in a first direction, the pixel electrode has a width W1 in the first direction, and the pixel electrode is in contact with the A second direction perpendicular to the first direction has a width W2, and W1<W2, the distance between the common electrode and the pixel electrode in a vertical projection direction is 2000 angstroms to 12000 angstroms. 17. The pixel array substrate according to claim 12, wherein the plurality of branches of the common electrode comprises a plurality of first straight segments, a plurality of second straight segments and a plurality of curved segments, the plurality of first straight segments The extension direction of the line segment is different from the extension direction of the plurality of second straight line segments, the plurality of curved segments are respectively connected between the plurality of first straight line segments and the plurality of second straight line segments, and the A plurality of curved segments overlap with the touch trace.