TWI416230B - Pixel array - Google Patents

Abstract

A pixel array comprises a plurality of scan lines extended along a row direction in a zigzag manner, a plurality of data lines extended along a column direction and a plurality of pixels connected the scan lines and the data lines. Each pixel arranged in n-th row includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first transistor and a first pixel electrode. A first gate of the first transistor is connected to the (n+1)-th scan line. A first drain of the first transistor is connected to the first pixel electrode. A second sub-pixel includes a second transistor and a second pixel electrode. A second gate of the second transistor is connected to the n-th scan line. A second drain of the second transistor is connected to the second sub-pixel electrode. A first source of the first transistor and a second source of the second transistor are connected to the same data line among the data lines.

Description

Pixel array

This invention relates to a display array, and more particularly to a pixel array.

In general, a flat panel display is mainly composed of a display panel and a plurality of driver ICs, wherein the display panel has a pixel array, and the pixels in the pixel array are corresponding to the scan lines and Driven by the corresponding data line. In order to make flat-panel display products more popular, the industry is in full swing to reduce costs. In recent years, a data-driven wafer half-source architecture design has been proposed, which mainly uses the layout on the pixel array to reduce The amount of data driven wafers used.

FIG. 1A is a schematic diagram of a conventional pixel array. Referring to FIG. 1, in a design of a pixel array 100a, two scan lines 120a are located between two adjacent columns of pixels 130a, 130b, wherein the active elements 140, 150 of the two pixels 130a, 130b The gates 142, 152 are respectively located on both sides of the scan line 120a. In the fabrication flow of the active components 140, 150 having the above structure, the gates 142, 152 of the active components 140, 150 and the sources 144, 154, the drains 146, 156 of the active components 140, 150 are different masks. The process is made. However, when the precision of the machine is insufficient or the alignment error on the process, the gates 142, 152 of the active elements 140, 150 and the sources 144, 154, the drains 146, 156 will be relatively displaced. The characteristics of the active components 140, 150 deviate from the original design values. At this time, since the gates 142 and 152 are respectively disposed on opposite sides of the corresponding scanning line 120a, when the gates 142 and 152 of the active elements 140 and 150 are relatively displaced with the gates 146 and 156, the pixels 130a and 130b are The gates 142, 152 and the drain 146 of the active elements 140, 150, The overlap area change of 156 is different. When the direction toward the pixel 130b is shifted, the gate-drain parasitic capacitance Cgd (Cgd) of the pixel 130a located on the scanning line 120a side becomes larger. The gate-drain parasitic capacitance Cgd of the pixel 130b located on the other side of the scanning line 120a becomes smaller, resulting in a difference in the gate-drain parasitic capacitance Cgd in the pixels 130a and 130b. As a result, the difference between the gate-drain parasitic capacitance Cgd caused by the error in the above process is large, and thus the pixel array 100a is liable to cause display brightness unevenness during display.

In order to reduce the difference between the gate-drain parasitic capacitance Cgd between the pixels, a pixel array structure is proposed in U.S. Patent No. 6,583,777. Referring to FIG. 1, the pixel array 100b has a plurality of irregularly arranged pixels R, G, B and scan lines 110b and data lines 120b connected to pixels R, G, and B, respectively. The scan line 110b extends straight along the column direction, and the data line 120b extends linearly in the row direction and the scan lines 110b intersect perpendicularly. However, since the pixels R, G, and B are irregularly arranged, it is easy to cause a phenomenon in which the color expression is significantly insufficient in the display process. In addition, since each of the pixels R, G, and B spans the three scanning lines 110b, the design of the pixel array reduces the aperture ratio, and the brightness is insufficient and the display quality is poor when applied to the display.

The present invention provides a pixel array which can reduce the difference in gate-drain parasitic capacitance and thus contribute to improvement in display quality.

The invention provides a pixel array comprising a plurality of scan lines, a plurality of data lines and a plurality of pixels. The scan lines extend in a zigzag direction along the column direction. The data line extends in the row direction and intersects the scan line. The pixels are connected to the scan lines and the data lines, and each pixel arranged in the nth column includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first transistor and a first pixel electrode, wherein a first gate of the first transistor is connected to the (n+1)th scan line, and one of the first transistors The first drain is connected to the first pixel electrode. The second sub-pixel includes a second transistor and a second pixel electrode, wherein a second gate of the second transistor is connected to the nth scan line, and a second gate of the second transistor is The two pixel electrodes are connected, a first source of the first transistor and a second source of the second transistor are connected to the same data line in the data line.

In an embodiment of the invention, the layout patterns of the first transistor and the second transistor are upwardly convex based on the corresponding scan lines.

In an embodiment of the invention, the layout patterns of the first transistor and the second transistor are convex downwards based on the corresponding scan lines.

In an embodiment of the invention, in the pixels arranged in the same column, the first transistor and the second transistor are located on the same side of the column of pixels.

In an embodiment of the invention, the three sides of each of the first pixel electrodes or each of the second pixel electrodes are surrounded by a corresponding one of the scan lines.

In an embodiment of the invention, each of the scan lines has a waveform on the pixel array.

In an embodiment of the invention, each of the scan lines includes a plurality of first wires and a plurality of second wires. The first wire extends in the column direction. The second wire extends in the row direction. The first wire and the second wire are alternately connected.

In an embodiment of the invention, a portion of the second wire is covered by one of the first pixel electrode or the second pixel electrode.

In an embodiment of the invention, the second wire is located between the first sub-pixel and the second sub-pixel in the same pixel and between two adjacent pixels.

In an embodiment of the invention, the length of each of the first wires is substantially greater than or equal to the width of one of the pixel electrodes, and the length of each of the second wires is substantially greater than or equal to one of the paintings. The length of the element electrode.

In an embodiment of the invention, each of the scan lines further includes a plurality of first branches and a plurality of second branches. The first branch connects the portion of the first wire and extends in the row direction. The second branch connects the portion of the first wire and extends in the row direction. The first branch and the second branch are substantially parallel to the second wire.

In an embodiment of the invention, the first partial branch and the partial second branch located in the same pixel are covered by the second pixel electrode.

In an embodiment of the invention, the pixels connected to the same data line are distributed on both sides of the data line.

In an embodiment of the invention, in the pixels arranged in the same column, the partial pixels in the even rows are connected to one of the scan lines, and the partial pixels in the odd rows are connected to the other scan line.

In an embodiment of the present invention, in each of the pixels arranged in the nth column, the first transistor and the second transistor respectively have a first channel layer and a second channel layer, and the first channel The layer is above the (n+1)th scan line and the second channel layer is above the nth scan line. The first drain is connected to the first pixel electrode from the first channel layer along a first direction, and the second drain is connected to the second pixel electrode from the second channel layer along a second direction, and the first direction Same as the second direction.

In an embodiment of the invention, in the pixels arranged in the same column, the lines connecting the center points of the first and second sub-pixels are close to the same line.

In an embodiment of the invention, in each pixel, the shape of the first transistor and the shape of the second transistor are in the form of a mirror image based on the data line.

In an embodiment of the invention, the first sub-pixel further includes a first capacitor electrode, and the electrical The first pixel electrode is connected, and the first capacitor electrode and the data line are in the same film layer and partially overlap with the previous scan line to form a first storage capacitor. The second sub-pixel further includes a second capacitor electrode electrically connected to the second pixel electrode, and the second capacitor electrode and the data line belong to the same film layer and partially overlap with the previous scan line to form a second storage capacitor. .

Based on the above, the pixel array of the present invention designs the scan lines into a zigzag layout manner, and arranges the first sub-pixel and the second sub-pixel connected to the same data line on both sides of the data line. At the same time, the first gate of the first transistor in the same pixel is connected to the (n+1)th scan line, and the second gate of the second transistor is connected to the nth scan line. Therefore, the design of the pixel array of the present invention can greatly reduce the number of layouts of the data lines, thereby reducing the manufacturing cost, and effectively improving the aperture ratio to significantly improve the brightness of the screen display, and can also improve the color performance of the display. In addition, since the drain of the transistor is the same in the direction in which the corresponding pixel electrodes extend, the gate-drain parasitic capacitance (Cgd) in the overall pixel is obtained when there is a misalignment between the layers on the transistor. The difference is small. In this way, when the pixel array of the present invention is applied to a display, it helps to improve the display uniformity of the display, thereby avoiding the problem of unevenness caused by flicker.

The above described features and advantages of the present invention will be more apparent from the following description.

100a, 100b‧‧‧ pixel array

110a, 110b‧‧‧ scan lines

120a, 120b‧‧‧ data line

130a, 130b‧‧ ‧ pixels

140, 150‧‧‧ active components

142, 152‧‧‧ gate

144, 154‧‧‧ source

146, 156‧‧ ‧ bungee

200a, 200b, 200c, 200d‧‧‧ pixel array

210‧‧‧ scan line

210a‧‧‧First scan line

210b‧‧‧second scan line

212‧‧‧First wire

214‧‧‧second wire

First branch of 216‧‧

218‧‧‧Second branch

220, 220a, 220b‧‧‧ data line

230, 230a‧‧ ‧ pixels

240‧‧‧ dielectric layer

242‧‧‧First contact window

244‧‧‧second contact window

310, 310', 310", 310'''‧‧‧ first sub-pixel

312, 312', 312" ‧ ‧ first transistor

312a, 312a', 312a" ‧ ‧ first channel layer

312b, 312b’, 312b”‧‧‧ first gate

312c, 312c', 312c" ‧ ‧ first bungee

312d, 312d', 312d" ‧ ‧ first source

314, 314', 314", 314'''‧‧‧ first pixel electrodes

316‧‧‧First Capacitance Electrode

318‧‧‧ brake insulation

320, 320', 320", 320'''‧‧‧ second sub-pixel

322, 322', 322" ‧ ‧ second transistor

322a, 322a’, 322a”‧‧‧ second channel layer

322b, 322b’, 322b”‧‧‧second gate

322c, 322c’, 322b” ‧ ‧ second bungee

322d, 322d’, 322d” ‧ ‧ second source

324, 324', 324", 324'''‧‧‧ second pixel electrodes

326‧‧‧First Capacitance Electrode

C1‧‧‧First storage capacitor

C2‧‧‧Second storage capacitor

D‧‧‧ gap

D1‧‧‧ first direction

D2‧‧‧ second direction

L1‧‧‧ direction

R, G, B‧‧ ‧ pixels

T1, T2‧‧‧ connection

S‧‧‧degree of offset

Figure 1A is a schematic diagram of a conventional pixel array.

Figure 1B is a schematic diagram showing another pixel array.

2A is a schematic diagram of a pixel array according to an embodiment of the present invention.

Figure 2B is a schematic illustration of the scan lines of the pixel array of Figure 2A.

2C is a schematic diagram of a pixel array according to another embodiment of the present invention.

2D is a schematic diagram of a pixel array according to still another embodiment of the present invention.

3A is a schematic diagram of a pixel array according to an embodiment of the present invention.

Fig. 3B is a schematic cross-sectional view taken along line A-A' and line B-B' of Fig. 3A.

FIG. 3C is a schematic diagram of a pixel array according to another embodiment of the present invention.

2A is a schematic diagram of a pixel array according to an embodiment of the present invention. 2B is a schematic diagram of a scan line of the pixel array of FIG. 2A. Referring to FIG. 2A and FIG. 2B simultaneously, in the embodiment, the pixel array 200a includes a plurality of scan lines 210, a plurality of data lines 220, and a plurality of pixels 230. For convenience of explanation, the pixel array 200a has a column direction L1 and a row direction L2, and the column direction L1 is substantially orthogonal to the row direction L2.

As shown in FIG. 2B, the scan line 210 of the present embodiment extends substantially in a zigzag manner along the column direction L1. For convenience of description, the scan line 210 will be followed by a plurality of first scan lines 210a and a plurality of second scans. The configuration of the line 210b will be described as an example. In other words, the scanning lines 210 are vertically parallel to each other in the column direction L1, and microscopically, the scanning lines 210 are substantially one-sided in shape and extend on the substrate.

More specifically, in this embodiment, each of the first scan lines 210a (or the second scan lines 210b) includes a plurality of first wires 212, a plurality of second wires 214, a plurality of first branches 216, and a plurality of Second branch 218. The first wire 212 extends substantially along the column direction L1, and the second wire 214 extends substantially along the row direction L2. In particular, the first wire 212 and the second wire 214 are alternately connected such that the first scan line 210a has a substantially square waveform. Of course, in other embodiments, the first scan line 210a may also have a giant tooth shape or an S shape. The first branch 216 connects a portion of the first wire 212 and extends substantially along the row direction L2. The second branch 218 connects a portion of the first wire 212 and extends along the column direction L2. Wherein the first branch 216 and the second branch 218 are substantially parallel to the second guide Line 214, and the first scan line 210a connects a first branch 216 and a second branch 218 to each of the first wires 212 adjacent to the second scan line 210b, such that the first branch 216 of the first scan line 210a is The second wires 214 of the second scan line 210b are substantially located on both sides of the data line. Thereby, each sub-pixel adjacent data line can further achieve the effect of avoiding lateral light leakage by the first branch 216 and the second branch 218.

Referring to FIG. 2A and FIG. 2B again, the data line 220 in this embodiment extends substantially along the row direction L2 and intersects the first scan line 210a and the second scan line 210b to define a plurality of pixel regions. In this embodiment, the data line 220 intersects the first scan line 210a and the second scan line 210b but is not electrically connected. Each pixel 230 in the pixel array 200a is connected to the corresponding first scan line 210a, second scan line 210b, and data line 220, and each pixel 230 arranged in the nth column includes a first sub-pixel. 310 and a second sub-pixel 320. The first sub-pixel 310 includes a first transistor 312 and a first pixel electrode 314, wherein the first transistor 312 has a first channel layer 312a, a first gate 312b, a first drain 312c, and A first source 312d. The first channel layer 312a is located above the (n+1)th scan line 210 (ie, the second scan line 210b), and the first gate 312b and the (n+1)th scan line 210 (ie, the second scan) Line 210b) is connected. The first drain 312c is connected to the first pixel electrode 314, and the first drain 312c is connected to the first pixel electrode 314 from the first channel layer 312a along a first direction D1, that is, the first pixel electrode 314. Corresponding to the (n+1)th scan line 210 (ie, the second scan line 210b). The three sides of the first pixel electrode 314 are surrounded by the corresponding previous scanning line 210 (i.e., the first scanning line 210a).

On the other hand, the second sub-pixel 320 includes a second transistor 322 and a second pixel electrode 324. The second transistor 322 has a second channel layer 322a, a second gate 322b, and a second layer. The drain 322c and a second source 322d. The second channel layer 322a is located above the nth scan line 210 (that is, the first scan line 210a), and the second gate 322b is connected to the nth scan line 210 (that is, the first scan line 210a). The second drain 322c is connected to the second pixel electrode 324, and the second drain 322c is connected to the second pixel electrode 324 from the second channel layer 322a along a second direction D2, that is, the second pixel electrode 324 corresponds to the nth scan line 210 (ie, the first scan line 210a). In particular, the first direction D1 is the same as the second direction D2. That is, the first direction D1 is substantially parallel to the second direction D2. The three sides of the second pixel electrode 324 are surrounded by a corresponding one of the scanning lines (not shown).

Specifically, the layout patterns of the first transistor 312 and the second transistor 322 are in a form that protrudes upward corresponding to the reference of the second scan line 210b and the first scan line 210a, respectively, and thus in this embodiment The pixel of the nth column is located in the area surrounded by the nth scan line 210, and is located in the first sub-pixel 310 and the second sub-pixel 320 of the nth column, and the first gate 312b and the (n) +1) scanning lines 210 (ie, second scanning lines 210b) are connected, and second gate 322b is connected to the nth scanning line 210 (that is, the first scanning line 210a), in other words, to the first gate 312b. The connected scan line 210 is the next one of the scan lines 210 connected to the second gate 322b, and since n is an arbitrary positive integer, those skilled in the art can also refer to the first gate 312b and the nth scan. The line 210 is connected, and the second gate 322b is connected to the (n-1)th scanning line 210, which is not limited by the present invention. For example, in other embodiments, referring to FIG. 2C, the pixel array 200b, the layout patterns of the first transistor 312' and the second transistor 322' may correspond to the second scan line 210b and the first scan line, respectively. The pattern of the base of 210a is convex downward. That is, the pixel of the nth column is located in the area surrounded by the nth scan line 210. In the nth column of pixels, the first gate 312b' is connected to the nth scan line 210, and The second gate 322b' is connected to the (n-1)th scan line 210. In other words, the scan line 210 connected to the first gate 312b' is also the scan line 210 connected to the second gate 322b'. The next one, and since n is an arbitrary positive integer, those skilled in the art can also say that the first gate 312b is connected to the nth scan line 210, and the second gate 322b and the (n+1)th scan line are connected. 210 is connected, and the present invention is not limited thereto. In addition, those skilled in the art are aware of the directional terms mentioned in the present invention, such as "upper", "lower", "front", "back", "left", "right", etc., only refer to additional drawings. Direction. Therefore, the direction used is used for illustration, not for To limit the invention. In other words, if the illustration of FIG. 2A is rotated by 180 degrees, the layout patterns of the first transistor 312 and the second transistor 322 are also obtained to correspond to the reference of the second scan line 210b and the first scan line 210a, respectively. For the convex type, please refer to Figure 2D. Moreover, in the present example, the first source 312d of the first transistor 312 and the second source 322d of the second transistor 322 are connected to the same data line 220a in the data line 220.

Specifically, as shown in FIG. 2A, the second wire 214 is located between the first sub-pixel 310 and the second sub-pixel 320 in the same pixel 230 and between the adjacent two pixels 230. The length of each of the first wires 212 is substantially greater than or equal to the width of the first pixel electrode 314 (or the second pixel electrode 324), and the length of each of the second wires 214 is substantially greater than or equal to the first pixel electrode. The length of 314 (or second pixel electrode 324). In addition, the data line 220a of the embodiment substantially intersects the first scan line 210a and the second scan line 210b, wherein the first sub-pixel 310 and the second sub-pixel 320 connected to the same data line 220a are distributed in the The two sides of the data line 220a, and the first sub-pixel 310 and the second sub-pixel 320 are substantially in the same column. In the pixel 230 in which the present example is arranged in the same column, the partial pixels 230 located in the even rows are connected to one of the scanning lines 210, and the partial pixels 230 located in the odd rows are connected to the other scanning line 210. That is, the second sub-pixel 320 located in the even row is electrically connected to the first scan line 210a, and the first sub-pixel 310 located in the odd row is electrically connected to the second scan line 210b.

In addition, the first gate 312b of the first transistor 312 is substantially connected to the second scan line 210b, and the second gate 322b of the second transistor 322 is substantially connected to the first scan line 210a. In the pixels 230 arranged in the same column, the first transistor 312 and the second transistor 322 are located on the same side of the column pixel 230, and in each pixel 230, the first transistor 312 is the second transistor. The 322 is flipped horizontally by 180 degrees. That is, the shape of the first transistor 312 and the shape of the second transistor 322 are mirrored and slightly misaligned with the data line 220a as a reference line. In other words, the layout of the first transistor 312 and the second transistor 322 described above are substantially the same, that is, the first channel layer 312a and the second layer. The shape of the channel layer 322a, the first drain 312c and the second drain 322c correspond to the extending direction of the first pixel electrode 314 and the second pixel electrode 324, and the shapes of the first source 312d and the second source 322d. All the same. In addition, the first pixel electrode 314 and the second pixel electrode 324 cover a portion of the second wire 214, wherein the second pixel electrode 324 also covers a portion of the first branch 216 and a portion of the second branch 218 located in the same pixel 230.

Further, in the present embodiment, in the pixels 230 arranged in the same column, the line connecting the center points of the first sub-pixel 310 and the second sub-pixel 320 approaches the same straight line. Specifically, in the pixel 230 formed by the first sub-pixel 310 and the second sub-pixel 320, the first sub-pixel 310 located in the odd-numbered row and the second sub-pixel 320 located in the even-numbered line are not completely aligned . The line connecting the center point of the first sub-pixel 310 is T1, and the line connecting the center point of the second sub-pixel 320 is T2, wherein the offset degree S of the connection line T1 and the connection line T2 is the first sub-pixel. 310 or the second sub-pixel 320 is 3% to 50% of the length. Since the degree of offset S is not large, the first sub-pixel 310 and the second sub-pixel 320 can be counted in the same column.

It should be noted that, in this embodiment, the extending direction of the first drain electrode 312c and the second drain electrode 322c are the same as the extending direction of the second pixel electrode 324. Therefore, even when a misalignment occurs between different layers when making a transistor or a slight offset due to the tolerance of the precision of the machine, the variation of the gate-drain parasitic capacitance (Cgd) can be more uniform, here The more consistent variation means that the gate-drain parasitic capacitance (Cgd) of each pixel 230 on the pixel array 200a will become larger or smaller at the same time. In this way, the difference in brightness between adjacent two pixels 230 is small, and when the pixel array 200a is applied to a display (not shown), the display uniformity of the display is improved, thereby avoiding flicker (flicker). ) causes a problem of uneven brightness.

In addition, since the pixel array 200a of the present embodiment designs the scan line 210 in a zigzag layout manner, the first sub-pixel 310 and the second sub-pixel 320 connected to the same data line 220a are disposed in the data. Both sides of line 220a. At the same time, the first transistor 312 in the same pixel 230 will be located. The first gate 312b is connected to the second scan line 210b, and the second gate 322b of the second transistor 322 is connected to the first scan line 210a. In addition to greatly reducing the number of layouts of the data lines 220, this design can also effectively increase the aperture ratio, so that the brightness of the screen display is significantly improved. In addition, the pixels 230 of the embodiment are basically located on the same column, and each of the pixels 230 composed of the first sub-pixel 310 and the second sub-pixel 320 is substantially rectangular, and thus is compared with In the conventional pixel array 100, the embodiment can effectively improve the color performance of the picture.

3A is a schematic diagram of a pixel array according to an embodiment of the present invention. Fig. 3B is a schematic cross-sectional view taken along line A-A' and line B-B' of Fig. 3A. Referring to FIG. 3A and FIG. 3B simultaneously, the pixel array 200c of the present embodiment is similar to the above-described pixel array 200a. However, in the pixel array 200c of the present embodiment, the gap D between adjacent pixels is reduced, and thus, in the same layout space, since the gap D between adjacent pixels becomes smaller, the pixel is The area can be increased to increase the aperture ratio of the pixels. In addition, in the pixel array 200c having a high aperture ratio of the present embodiment, the dielectric layer 240 having high coverage characteristics covers the first transistor 312" and the second transistor 322", and the dielectric layer 240 is also visible. As an overcoating, the layout of the first pixel electrode 314" and the second pixel electrode 324" may further extend above the corresponding scan line 210 to further increase the aperture ratio of the pixel. It should be noted that, in this embodiment, the first pixel electrode 314" and the second pixel electrode 324" only show a portion of the nth scan line and the (n+1)th scan line. However, in other embodiments, referring to FIG. 3C, the first pixel electrode 314 ′′′ and the second pixel electrode 324 ′′′ may also cover the entire first sub-pixel 310′′′ and the second sub-picture. Around the 320'''.

In order to further enhance the storage capacitance of the first sub-pixel 310" and the second sub-pixel 320", the first sub-pixel 310" further includes a first capacitor electrode 316, and the second sub-pixel 320" further includes a first Two capacitor electrodes 326. In detail, the first capacitor electrode 316 is electrically connected to the first pixel electrode 314 ′′, and the first capacitor electrode 316 and the previous scan line 210 (ie, the nth scan line) 210) partially overlapping to form a first storage capacitor C1, that is, the lower electrode of the first storage capacitor C1 is a portion of the previous scan line 210, the upper electrode is the first capacitor electrode 316, and the upper electrode is the same as the data line 220. Membrane layer. The second capacitor electrode 326 is electrically connected to the second pixel electrode 324 ′′, and the second capacitor electrode 326 is partially overlapped with the previous scan line 210 (ie, the (n-1)th scan line 210 ) to form a second storage. The capacitor C2, that is, the lower electrode of the second storage capacitor 326 is a portion of the upper scan line 210, the upper electrode of which is the second capacitor electrode 326, and the upper electrode and the data line 220 belong to the same film layer. In detail, please refer to the figure. 3A and FIG. 3B, in the first sub-pixel 310" in the nth column, the first pixel electrode 314" is electrically connected to the first transistor 312" through the first contact window 242 of the dielectric layer 240. The first capacitor electrode 316 is electrically connected to the second contact window 244 of the dielectric layer 240. In an actual operating mechanism, an open voltage level is applied to the (n+1)th scan line 210 (ie, the second scan line 210b) to turn on the first transistor 312", and then a data is input from the data line 220a. The voltage, the data voltage is transferred to the first pixel electrode 314" via the first transistor 312" that is turned on and the first contact window 242 of the dielectric layer 240. And, the first pixel electrode 314 having the data voltage The data voltage is transmitted to the first capacitor electrode 316 through the second contact window 244 of the dielectric layer 240 such that the first pixel electrode 314" is equipotential to the first capacitor electrode 316, and thus the (n+1)th scan a line 210 (ie, a second scan line 210b), a first capacitor electrode 316, and a gate insulating layer between the (n+1)th scan line 210 (ie, the second scan line 210b) and the first capacitor electrode 316 318 together constitute a first storage capacitor C1 of the first sub-pixel 310", and the first storage capacitor C1 is used to stabilize the data voltage of the first pixel electrode 314" during the closing of the first transistor 312" to improve display quality. . In this way, the first sub-pixel 310" can have both a high aperture ratio and a high storage capacitance value. Similarly, the operation mechanism of the second sub-pixel 320'' is similar to that of the first sub-pixel 310", and will not be described again. .

In summary, the pixel array of the present invention designs the scan line into a zigzag layout manner, and arranges the first sub-pixel and the second sub-pixel connected to the same data line on both sides of the data line. . At the same time, the first gate of the first transistor in the same pixel is connected to the (n+1)th scan line. The second gate of the second transistor is connected to the nth scan line. Therefore, the design of the pixel array of the present invention can greatly reduce the number of layouts of the data lines, thereby effectively increasing the aperture ratio, thereby significantly improving the brightness of the screen display, and improving the color performance of the display. In addition, since the drain of the transistor is the same in the extending direction of the corresponding drawing electrode, the gate-drain parasitic capacitance in the overall pixel is obtained when there is a registration deviation between the layers on the transistor. The difference in Cgd) is small. In this way, when the pixel array of the present invention is applied to a display, it helps to improve the display uniformity of the display, thereby avoiding the problem of unevenness caused by flicker.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

200a‧‧‧ pixel array

210‧‧‧ scan line

210a‧‧‧First scan line

210b‧‧‧second scan line

220‧‧‧Information line

230‧‧‧ pixels

310‧‧‧The first sub-pixel

312‧‧‧First transistor

312a‧‧‧first channel layer

312b‧‧‧first gate

312c‧‧‧First bungee

312d‧‧‧first source

314‧‧‧ first pixel electrode

320‧‧‧Second sub-pixel

322‧‧‧Second transistor

322a‧‧‧second channel layer

322b‧‧‧second gate

322c‧‧‧second bungee

322d‧‧‧second source

324‧‧‧Second pixel electrode

D1‧‧‧ first direction

D2‧‧‧ second direction

L1‧‧‧ direction

L2‧‧‧ direction

T1, T2‧‧‧ connection

S‧‧‧degree of offset

Claims (17)

A pixel array includes: a plurality of scan lines extending in a zigzag direction along a column direction; a plurality of data lines extending along a row direction and intersecting the scan lines; a plurality of pixels, and the scan lines and the plurality of pixels Each of the pixels arranged in the nth column includes: a first sub-pixel including a first transistor and a first pixel electrode, wherein a first gate of the first transistor Connected to the (n+1)th scan line, and a first drain of the first transistor is connected to the first pixel electrode; and a second subpixel includes a second transistor and a first a second pixel electrode, wherein a second gate of the second transistor is connected to the nth scan line, and a second drain of the second transistor is connected to the second pixel electrode, the first transistor a first source and a second source of the second transistor are connected to the same data line of the data lines, and are connected to the shapes of the first transistor and the second transistor on the same data line. The data line is in the form of a mirror image. The pixel array of claim 1, wherein the layout pattern of the first transistor and the second transistor is upwardly convex based on a corresponding scan line. The pixel array of claim 1, wherein the layout pattern of the first transistor and the second transistor is a downward convex shape based on a corresponding scan line. The pixel array of claim 3, wherein in the pixels arranged in the same column, the first transistors and the second transistors are located on the same side of the column of pixels. The pixel array of claim 4, wherein three sides of each of the first pixel electrodes or each of the second pixel electrodes are surrounded by a corresponding one of the scan lines. The pixel array according to claim 5, wherein each scan line is on the pixel array One side waveform. The pixel array of claim 5, wherein each of the scan lines comprises: a plurality of first wires extending along the column direction; and a plurality of second wires extending along the row direction, wherein The first wires are alternately connected to the second wires. The pixel array of claim 5, wherein a portion of the second wires are covered by one of the first pixel electrode or the second pixel electrode. The pixel array of claim 5, wherein the second wires are located between the first sub-pixel and the second sub-pixel in the same pixel and between two adjacent pixels. The pixel array of claim 5, wherein each of the first wires has a length substantially greater than or equal to a width of one of the pixel electrodes, and each of the second wires has a length substantially greater than or equal to one of the pixels. The length of the electrode. The pixel array of claim 5, wherein each of the scan lines further comprises: a plurality of first branches connecting the portions of the first wires and extending along the row direction; and a plurality of second branches Connecting a portion of the first wires and extending along the row direction, wherein the first branches and the second branches are substantially parallel to the second wires. The pixel array of claim 5, wherein a portion of the first branch and a portion of the second branch located in the same pixel are covered by the second pixel electrode. The pixel array of claim 1, wherein the pixels connected to the same data line are distributed on both sides of the data line. The pixel array according to claim 13, wherein in the pixels arranged in the same column, a part of the pixels in the even line is connected to one of the scanning lines, and a part of the pixels in the odd line and the other Scan line connection. The pixel array of claim 1, wherein in the pixels arranged in the nth column, the first transistor and the second transistor respectively have a first channel layer and a second through a first channel layer above the (n+1)th scan line, the second channel layer being above the nth scan line, the first drain layer being along the first direction from the first channel layer Connected to the first pixel electrode, the second drain is connected to the second pixel electrode from the second channel layer along a second direction, and the first direction is the same as the second direction. The pixel array of claim 1, wherein in the pixels arranged in the same column, the lines connecting the center points of the first and second sub-pixels are close to the same line. The pixel array of claim 1, wherein the first sub-pixel further comprises a first capacitor electrode electrically connected to the first pixel electrode, and the first capacitor electrode and the data line are The same film layer is partially overlapped with the previous scan line to form a first storage capacitor, and the second sub-pixel further includes a second capacitor electrode electrically connected to the second pixel electrode, and the second capacitor The electrode and the data line belong to the same film layer and partially overlap with the previous scan line to form a second storage capacitor.