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TWI305661B - Process for transfer of a thin layer formed in a substrate with vacancy clusters - Google Patents

Process for transfer of a thin layer formed in a substrate with vacancy clusters Download PDF

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Publication number
TWI305661B
TWI305661B TW095103237A TW95103237A TWI305661B TW I305661 B TWI305661 B TW I305661B TW 095103237 A TW095103237 A TW 095103237A TW 95103237 A TW95103237 A TW 95103237A TW I305661 B TWI305661 B TW I305661B
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TW
Taiwan
Prior art keywords
substrate
thin layer
transfer
layer formed
vacancy clusters
Prior art date
Application number
TW095103237A
Other languages
English (en)
Other versions
TW200723364A (en
Inventor
Christophe Maleville
Eric Neyret
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of TW200723364A publication Critical patent/TW200723364A/zh
Application granted granted Critical
Publication of TWI305661B publication Critical patent/TWI305661B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47L—DOMESTIC WASHING OR CLEANING; SUCTION CLEANERS IN GENERAL
    • A47L9/00—Details or accessories of suction cleaners, e.g. mechanical means for controlling the suction or for effecting pulsating action; Storing devices specially adapted to suction cleaners or parts thereof; Carrying-vehicles specially adapted for suction cleaners
    • A47L9/24—Hoses or pipes; Hose or pipe couplings
    • A47L9/242—Hose or pipe couplings
    • A47L9/246—Hose or pipe couplings with electrical connectors
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)

Description

1305.661 該支撐基底是以與施體基底相同的方法得到。 23. —種製造包含一半導體材料之薄層與一支撐基底的方法 ，該薄層，其產生自轉移至具有在第一密度的空孔聚集 之一施體基底的一部份之該支撐基底上，其特徵在於包 含： •在將施體基底的該部分轉移至支撐基底後，固化存在 於施體基底之該部份中之空孔聚集，轉移至支撐基底 上之部分的步驟，以將第一密度降至第二密度， •以及在該固化步驟之前，先適以一或多個步驟，以使 在第一密度存在於施體基底之該部分中之空孔聚集的 尺寸不會擴大。 24. —種絕緣層上半導體基底，包括一絕緣層，插介於一半 導體材料的薄層與一支撐基底之間，係根據申請專利範 圍第1至23項其中任一之方法得到，從具空孔聚集密度等 於大約3/cm2之施體基底開始，其特徵在於該薄層具有的 空孔聚集密度等於或小於大約0.075/cm2。 25. 如申請專利範圍第24項的絕緣層上半導體基底，其特徵 在於該支撐基底具有的空孔聚集密度大於或等於大約 3/cm2 ° 26. —種用於回收具有空孔聚集且已用做為施體基底的方法 ，該施體基底已被取下一薄層且轉移至一支撐基底，其 特徵在於其以一或多個適宜的步驟組成，以便不會使存 在於該基底内之空孔聚集的尺寸變大。 H:\George\95026\95026·更正-附件 3.doc -28-
TW095103237A 2005-01-31 2006-01-27 Process for transfer of a thin layer formed in a substrate with vacancy clusters TWI305661B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0500936A FR2881573B1 (fr) 2005-01-31 2005-01-31 Procede de transfert d'une couche mince formee dans un substrat presentant des amas de lacunes

Publications (2)

Publication Number Publication Date
TW200723364A TW200723364A (en) 2007-06-16
TWI305661B true TWI305661B (en) 2009-01-21

Family

ID=34979525

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095103237A TWI305661B (en) 2005-01-31 2006-01-27 Process for transfer of a thin layer formed in a substrate with vacancy clusters

Country Status (7)

Country Link
US (1) US7285471B2 (zh)
JP (1) JP5025957B2 (zh)
KR (1) KR100796831B1 (zh)
CN (1) CN100524620C (zh)
FR (1) FR2881573B1 (zh)
SG (1) SG124408A1 (zh)
TW (1) TWI305661B (zh)

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WO2008050176A1 (en) * 2006-10-27 2008-05-02 S.O.I.Tec Silicon On Insulator Technologies Improved process for transfer of a thin layer formed in a substrate with vacancy clusters
US8124499B2 (en) * 2006-11-06 2012-02-28 Silicon Genesis Corporation Method and structure for thick layer transfer using a linear accelerator
JP5249511B2 (ja) * 2006-11-22 2013-07-31 信越化学工業株式会社 Ｓｏｑ基板およびｓｏｑ基板の製造方法
FR2911430B1 (fr) * 2007-01-15 2009-04-17 Soitec Silicon On Insulator "procede de fabrication d'un substrat hybride"
EP1950803B1 (en) 2007-01-24 2011-07-27 S.O.I.TEC Silicon on Insulator Technologies S.A. Method for manufacturing silicon on Insulator wafers and corresponding wafer
FR2912259B1 (fr) * 2007-02-01 2009-06-05 Soitec Silicon On Insulator Procede de fabrication d'un substrat du type "silicium sur isolant".
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WO2009106915A1 (en) * 2008-02-26 2009-09-03 S.O.I.Tec Silicon On On Insulator Technologies Method for reducing the amount or eliminating the crystalline defects, in a semiconductor layer of a composite structure
US8299485B2 (en) * 2008-03-19 2012-10-30 Soitec Substrates for monolithic optical circuits and electronic circuits
FR2941324B1 (fr) * 2009-01-22 2011-04-29 Soitec Silicon On Insulator Procede de dissolution de la couche d'oxyde dans la couronne d'une structure de type semi-conducteur sur isolant.
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
EP2513964B1 (en) 2009-12-15 2014-02-19 Soitec Process for recycling a substrate.
EP3685440A4 (en) * 2017-09-24 2021-09-22 Monolithic 3D Inc. 3D SEMICONDUCTOR DEVICE, STRUCTURE AND PROCESSES
WO2019125810A1 (en) * 2017-12-21 2019-06-27 Globalwafers Co., Ltd. Method of treating a single crystal silicon ingot to improve the lls ring/core pattern

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Also Published As

Publication number Publication date
US20060172508A1 (en) 2006-08-03
JP2006261648A (ja) 2006-09-28
JP5025957B2 (ja) 2012-09-12
TW200723364A (en) 2007-06-16
CN100524620C (zh) 2009-08-05
KR100796831B1 (ko) 2008-01-22
US7285471B2 (en) 2007-10-23
SG124408A1 (en) 2006-08-30
KR20060088052A (ko) 2006-08-03
FR2881573A1 (fr) 2006-08-04
FR2881573B1 (fr) 2008-07-11
CN1828830A (zh) 2006-09-06

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