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KR970053793A - 정전적방전(esd) 구조 - Google Patents

정전적방전(esd) 구조 Download PDF

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Publication number
KR970053793A
KR970053793A KR1019950070194A KR19950070194A KR970053793A KR 970053793 A KR970053793 A KR 970053793A KR 1019950070194 A KR1019950070194 A KR 1019950070194A KR 19950070194 A KR19950070194 A KR 19950070194A KR 970053793 A KR970053793 A KR 970053793A
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KR
South Korea
Prior art keywords
region
pad
active region
area
active
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Application number
KR1019950070194A
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English (en)
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KR100379330B1 (ko
Inventor
안종구
Original Assignee
문정환
Lg 반도체 주식회사
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Application filed by 문정환, Lg 반도체 주식회사 filed Critical 문정환
Priority to KR1019950070194A priority Critical patent/KR100379330B1/ko
Publication of KR970053793A publication Critical patent/KR970053793A/ko
Application granted granted Critical
Publication of KR100379330B1 publication Critical patent/KR100379330B1/ko

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements

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  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 정전적방전 구조에 관한 것으로, 엔웰 영역내의 P+ 액티브 영역에 형성된 P-N 다이오드를 포함하는 영역과; 피웰 영역내의 N+ 액티브 영역에 형성된 P-N 다이오드, 기생 필드 프랜지스터 디바이스(FTD)및 패드영역을 포함하느 영역을 구비하여 구성되며, 상기와 같이 구성한 정전적방전 구조는 입력 패드 영역을 활용함으로써 ESD 방전 전류의 면적을 크게 하여 ESD의 내성이 좋아지고, N+ 액티브 영역을 패드영역에 형성함으로써 패드 레이아웃의 면적을 줄일 수 있게 되어 칩 사이즈(Chip size)를 크게 줄일 수 있는 장점이 있다.
또한, N+ 액티브 영역과 P+ 액티브 영역이 서로 붙어 있어 래치업(Latch-up)을 방지하기 위한 가드(Guard)영역의 형성이 용이해지고, 패드 아래의 액티브 영역을 보호하기 위하여 그 중간에 폴리층(Poly layer)를 삽입하여 보상함으로써 패드 아래의 ESD 구조 소자의 동작을 용이하게 할 수 있는 장점이 있다.

Description

정전적방전(ESD) 구조
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명에 따른 패드 레이아웃도과 그 등가회로도.

Claims (2)

  1. 엔웰 영역내의 P+액티브 영역에 형성된 P-N 다이오드를 포함하는 영역과; 피웰 영역내의 N+ 액티브 영역에 형성된 P-N 다이오드, 기생 필드 트랜지스터 디바이스(FTD) 및 패드영역을 포함하는 영역을 구비하여 구성되는 것을 특징으로 하는 정전적방전 구조.
  2. 제1항에 있어서, 패드영역 아래의 액티브 영역을 보호하기 위하여 입력 패드보다 액티브 영역의 컨택영역사이에 삽입하는 폴리층은, 패드영역 아래의 액티브 영역과 같은 크기와 모양으로 이루어지는 것을 특징으로 하는 정전적방전 구조.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950070194A 1995-12-31 1995-12-31 정전적방전(esd)구조 KR100379330B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950070194A KR100379330B1 (ko) 1995-12-31 1995-12-31 정전적방전(esd)구조

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950070194A KR100379330B1 (ko) 1995-12-31 1995-12-31 정전적방전(esd)구조

Publications (2)

Publication Number Publication Date
KR970053793A true KR970053793A (ko) 1997-07-31
KR100379330B1 KR100379330B1 (ko) 2003-06-19

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ID=37417074

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950070194A KR100379330B1 (ko) 1995-12-31 1995-12-31 정전적방전(esd)구조

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KR (1) KR100379330B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100660202B1 (ko) * 2005-08-08 2006-12-21 주식회사 포스코 저온인성이 우수한 라인 파이프 강재의 재질특성 평가방법

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0752775B2 (ja) * 1988-07-30 1995-06-05 日本電気株式会社 入力保護回路装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100660202B1 (ko) * 2005-08-08 2006-12-21 주식회사 포스코 저온인성이 우수한 라인 파이프 강재의 재질특성 평가방법

Also Published As

Publication number Publication date
KR100379330B1 (ko) 2003-06-19

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