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KR950012705A - 정전방전 보호회로의 트랜지스터 및 그 제조방법 - Google Patents

정전방전 보호회로의 트랜지스터 및 그 제조방법 Download PDF

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Publication number
KR950012705A
KR950012705A KR1019930021959A KR930021959A KR950012705A KR 950012705 A KR950012705 A KR 950012705A KR 1019930021959 A KR1019930021959 A KR 1019930021959A KR 930021959 A KR930021959 A KR 930021959A KR 950012705 A KR950012705 A KR 950012705A
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South Korea
Prior art keywords
transistor
electrostatic discharge
protection circuit
drain electrode
semiconductor substrate
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KR1019930021959A
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KR0166101B1 (ko
Inventor
이우봉
오세준
여태정
고재완
구영모
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019930021959A priority Critical patent/KR0166101B1/ko
Priority to JP6253096A priority patent/JP2556959B2/ja
Priority to DE4437759A priority patent/DE4437759C2/de
Priority to US08/326,880 priority patent/US5545572A/en
Priority to TW083109849A priority patent/TW253074B/zh
Publication of KR950012705A publication Critical patent/KR950012705A/ko
Priority to US08/652,949 priority patent/US5907174A/en
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Publication of KR0166101B1 publication Critical patent/KR0166101B1/ko
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 회로에 고전압 또는 과전류가 가해졌을 경우 전류 또는 전압을 중도에서 소모시켜 회로를 보호하는 역할을 하는 정전방전(Electrustatic Discharge, ESDI 보호회로에 관한 것으로, 특히 작은 공핍층의 확장에도 쉽게 소스 또는 드래인전극과 연결되도록 소스전극 또는 드레인전극 중 어느 하나와 근접하여 비대칭적으로 형성된 구조의 높은 문턱전압을 갖는 정전방전 보호회로의 트랜지스터를 형성함으로써 전류 플럭스를 분산시킴으로써 순간적인 ESD 충격 방출이 가능케 하고 고전류 플럭스 집중에 의한 열 발생을 감소시켜 ESD 충격에 대한 저항특성을 향상시키는 효과를 얻을 수 있다.

Description

정전방전 보호회로의 트랜지스터 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 본 발명에 따른 제1도의 제1트랜지스터(107)의 구조 및 전자 흐름도,
제6A도 내지 제6D도는 제5도의 구조를 이루는 제1트랜지스터 (107)를 제조하는 일실시예의 공정 단면도.

Claims (3)

  1. 높은 문턱전압을 갖는 증전방전(electrostatic discharge, ESD) 보호회로의 트랜지스터에 있어서, 반도체 기판에 고농도로 도핑된 매립층이 형성되되, 작은 공핍층의 확장에도 쉽게 소스 또는 드래인전극과 연결되도록 소스전극 또는 드레인전극 중 어느 하나와 근접하여 비대칭적으로 형성된 구조로 이루에지는 것을 특징으로 하는 정전방전 보호회로의 트랜지스터.
  2. 높은 문턱전압을 갖는 정전방전 보호회로의 트랜지스터 제조 방법에 있어서, 반도체 기판(10)에 포토 레지스트(20)를 도포한 다음 마스크 공정을 진행하여 상기 포토레지스트를 소정부위 식가하여 반도체 기판을 노출시킨 후 노출된 반도체기판에 불순물을 주입하여 매립층(30)을 형성하되 소스전극 또는 드래인전극 중 어느 하나와 근접하여 비대칭적으로 형성하는 단계와, 게이트산화막(40), 게이트전극(80)을 차례로 형성 한 후 전체구조 상부에 절연막(50)을 형성하고, 마스크 공정을 진행하여 소스전극 및 드래인전극을 형성하기 위해 반도체 기판을 소정부위 노출시키는 단계와, 불순물을 주입하여 소스전극 및 드래인전극(60)을 형성하는 단계와, 전체구조 상부에 전도막(70)을 증착한 다음 마스크 공정을 진헝하여 드래인전극과 게이트전극을 접속시키는 단계를 포함하여 이루어지는 것을 특징으로 하는 정전방전 보호회로의 트랜지스터 제조방법.
  3. 제2항에 있어서, 상기 트랜지스터(100)는 N형 모스트랜지스터로서 소스전극과 근접된 매립층(30) 형성을 위해 N형 불순물을 고농도로 주입하는 것을 특징으로 하는 정전방전 보호회로의 트랜지스터 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930021959A 1993-10-21 1993-10-21 정전방전 보호회로의 트랜지스터 및 그 제조방법 Expired - Lifetime KR0166101B1 (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019930021959A KR0166101B1 (ko) 1993-10-21 1993-10-21 정전방전 보호회로의 트랜지스터 및 그 제조방법
JP6253096A JP2556959B2 (ja) 1993-10-21 1994-10-19 静電放電消去回路のトランジスターおよびその製造方法
DE4437759A DE4437759C2 (de) 1993-10-21 1994-10-21 Transistor für einen Schutzschaltkreis gegenüber elektrostatischer Entladungen und Verfahren zu seiner Herstellung
US08/326,880 US5545572A (en) 1993-10-21 1994-10-21 Method for fabricating electrostatic discharge protecting transistor
TW083109849A TW253074B (ko) 1993-10-21 1994-10-24
US08/652,949 US5907174A (en) 1993-10-21 1996-05-24 Electrostatic discharge protecting transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930021959A KR0166101B1 (ko) 1993-10-21 1993-10-21 정전방전 보호회로의 트랜지스터 및 그 제조방법

Publications (2)

Publication Number Publication Date
KR950012705A true KR950012705A (ko) 1995-05-16
KR0166101B1 KR0166101B1 (ko) 1999-01-15

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KR1019930021959A Expired - Lifetime KR0166101B1 (ko) 1993-10-21 1993-10-21 정전방전 보호회로의 트랜지스터 및 그 제조방법

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US (2) US5545572A (ko)
JP (1) JP2556959B2 (ko)
KR (1) KR0166101B1 (ko)
DE (1) DE4437759C2 (ko)
TW (1) TW253074B (ko)

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KR100332472B1 (ko) * 1998-10-28 2002-09-05 주식회사 하이닉스반도체 정전기보호회로를구비한반도체장치의제조방법
KR100402672B1 (ko) * 1995-10-31 2004-06-04 텍사스 인스트루먼츠 인코포레이티드 CMOS/BiCMOS기술에서ESD방지를위한집적화된횡형구조
KR100498587B1 (ko) * 1997-06-30 2005-09-15 주식회사 하이닉스반도체 반도체소자의필드트랜지스터형성방법

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JPH09129871A (ja) * 1995-10-31 1997-05-16 Nkk Corp Ｍｏｓトランジスタおよびその製造方法
KR100211539B1 (ko) * 1995-12-29 1999-08-02 김영환 반도체소자의 정전기방전 보호장치 및 그 제조방법
US6355508B1 (en) 1998-09-02 2002-03-12 Micron Technology, Inc. Method for forming electrostatic discharge protection device having a graded junction
US6051456A (en) * 1998-12-21 2000-04-18 Motorola, Inc. Semiconductor component and method of manufacture
US6063672A (en) * 1999-02-05 2000-05-16 Lsi Logic Corporation NMOS electrostatic discharge protection device and method for CMOS integrated circuit
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US6552879B2 (en) 2001-01-23 2003-04-22 International Business Machines Corporation Variable voltage threshold ESD protection
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US6873017B2 (en) * 2003-05-14 2005-03-29 Fairchild Semiconductor Corporation ESD protection for semiconductor products
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US7723823B2 (en) * 2008-07-24 2010-05-25 Freescale Semiconductor, Inc. Buried asymmetric junction ESD protection device
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US20240170531A1 (en) * 2022-11-17 2024-05-23 Globalfoundries U.S. Inc. Structure with buried doped region and methods to form same

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KR100402672B1 (ko) * 1995-10-31 2004-06-04 텍사스 인스트루먼츠 인코포레이티드 CMOS/BiCMOS기술에서ESD방지를위한집적화된횡형구조
KR100498587B1 (ko) * 1997-06-30 2005-09-15 주식회사 하이닉스반도체 반도체소자의필드트랜지스터형성방법
KR100332472B1 (ko) * 1998-10-28 2002-09-05 주식회사 하이닉스반도체 정전기보호회로를구비한반도체장치의제조방법

Also Published As

Publication number Publication date
US5545572A (en) 1996-08-13
JP2556959B2 (ja) 1996-11-27
JPH07202196A (ja) 1995-08-04
DE4437759A1 (de) 1995-04-27
DE4437759C2 (de) 2002-02-21
TW253074B (ko) 1995-08-01
KR0166101B1 (ko) 1999-01-15
US5907174A (en) 1999-05-25

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Termination date: 20140421

Termination category: Expiration of duration