KR950021134A - 반도체소자의 콘택 형성방법 - Google Patents
반도체소자의 콘택 형성방법 Download PDFInfo
- Publication number
- KR950021134A KR950021134A KR1019930031912A KR930031912A KR950021134A KR 950021134 A KR950021134 A KR 950021134A KR 1019930031912 A KR1019930031912 A KR 1019930031912A KR 930031912 A KR930031912 A KR 930031912A KR 950021134 A KR950021134 A KR 950021134A
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- word line
- gate electrode
- forming
- depositing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 title 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract 9
- 238000000151 deposition Methods 0.000 claims abstract 7
- 125000006850 spacer group Chemical group 0.000 claims abstract 3
- 238000005468 ion implantation Methods 0.000 claims 6
- 238000005530 etching Methods 0.000 claims 4
- 239000012535 impurity Substances 0.000 claims 2
- 229920005591 polysilicon Polymers 0.000 claims 2
- 238000002513 implantation Methods 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000004904 shortening Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (5)
- 반도체소자의 콘택 형성방법에 있어서, 피웰(P-well)이 형성된 반도체기판 상부에 분리영역 마스크(a')를 이용해 LOCOS 방식으로 필드 산화막을 성장하고 게이트 산화막과 게이트 전극 및 워드선용 다결정 실리콘을 시각 지연없이 증착하는 공정과, 상기 다결정실리콘에 불순물 주입공정을 행하고, 일정 두께의 제1절연막을 증착하고, 제1게이트 전극 및 워드선마스크를 이용해 제1절연막과 다결정실리콘을 소정의 크기로 식각해 에비 게이트 전극 및 워드선패턴을 형성하는 공정과, 상대적으로 저농도의 이온주입공정을 행하고, 상기 예비 게이트 전극 및 워드선과 제1절연막의 상부에 절연막을 일정 두께 증착한 후, 비등방성 식각하여 제1절연막 스페이서를 형성하고 상대적으로 고농도의 이온주입 공정을 행함으로써, 제1LDD 활성영역을 형성하는 공정과, 전체 구조상에 제2절연 산화막을 증착하여 평탄화시킨 후, 상기 제2절연막의 상부에 감광막을 도포하고 제2게이트 전극 및 워드선겸 콘택 마스크를 이용해 감광막을 노광, 현상하여 감광패턴을 형성하는 공정과, 상기 감광막 패턴을 장애물로 이용해 제2절연막과 예비 게이트 전극 및 워드선다결정실리콘을 식각해 콘택홀과 게이트 전극 및 워드선을 동시에 형성하고, 그 내부에 상대적으로 저농도의 이온주입 공정을 행하는 공정과, 전체 구조상부에 일정 두께의 절연막을 증착한 후, 상기 절연막을 비등방성 식각하여 제2절연막 스페이서를 형성하고 상대적으로 고농도의 이온주입 공정을 행함으로써, 제2LDD 구조의 활성영역은 형성하는 공정과, 전체 구조상부에 일정 두께의 제2전도층을 증착하고, 제2전도층 전극 마스크(d')를 이용해 제2전도층 전극(10)을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 소자의 콘택 형성방법.
- 제1항에 있어서, 상기 제1절연막은 생략할 수 있는 것을 특징으로 하는 반도체소자의 콘택 형성방법.
- 제1항에 있어서, 상기 제2게이트 전극 및 워드선겸 콘택 마스크는 콘택홀과 전극을 동시에 형성하는 것을 특징으로 하는 반도체소자의 콘택 형성방법.
- 제1항에 있어서, 상기 고농도 이온주입 공정을 생략함으로써, MOSFET의 문턱 전압을 높이고, 이웃하는 활성영역간의 누설전류와 핫 캐리어(Hot Carrier) 현상을 방지하는 것을 특징으로 하는 반도체소자의 콘택 형성방법.
- 제4항에 있어서, 상기 고농도 이온주입 공정을 생략함으로써, 제2전도층은 불순물이 주입된 다결정실리콘을 사용해서 불순물이 확산되도록 하는 것을 특징으로 하는 반도체소자의 콘택 형성방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR93031912A KR970009617B1 (en) | 1993-12-31 | 1993-12-31 | Contact forming method of semiconductor device |
JP6327748A JP2557206B2 (ja) | 1993-12-31 | 1994-12-28 | 半導体素子の製造方法 |
US08/365,954 US5770464A (en) | 1993-12-31 | 1994-12-29 | Method for fabricating semiconductor devices having lightly doped drain |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR93031912A KR970009617B1 (en) | 1993-12-31 | 1993-12-31 | Contact forming method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950021134A true KR950021134A (ko) | 1995-07-26 |
KR970009617B1 KR970009617B1 (en) | 1997-06-14 |
Family
ID=19374835
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR93031912A Expired - Lifetime KR970009617B1 (en) | 1993-12-31 | 1993-12-31 | Contact forming method of semiconductor device |
Country Status (3)
Country | Link |
---|---|
US (1) | US5770464A (ko) |
JP (1) | JP2557206B2 (ko) |
KR (1) | KR970009617B1 (ko) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0967640A3 (en) * | 1998-06-25 | 2000-01-05 | Siemens Aktiengesellschaft | Method of making a self-aligned contact |
US6710424B2 (en) | 2001-09-21 | 2004-03-23 | Airip | RF chipset architecture |
US6534405B1 (en) * | 2001-10-01 | 2003-03-18 | Taiwan Semiconductor Manufacturing Company | Method of forming a MOSFET device featuring a dual salicide process |
CN110890368B (zh) * | 2018-09-07 | 2024-09-20 | 长鑫存储技术有限公司 | 半导体器件的制备方法和半导体器件 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2618011B1 (fr) * | 1987-07-10 | 1992-09-18 | Commissariat Energie Atomique | Procede de fabrication d'une cellule de memoire |
KR950000519B1 (ko) * | 1991-02-28 | 1995-01-24 | 현대전자산업 주식회사 | 폴리실리콘층을 이용한 자기정렬콘택 제조방법 |
KR940006682B1 (ko) * | 1991-10-17 | 1994-07-25 | 삼성전자 주식회사 | 반도체 메모리장치의 제조방법 |
US5283204A (en) * | 1992-04-15 | 1994-02-01 | Micron Semiconductor, Inc. | Method of forming passivation oxidation for improving cell leakage and cell area |
KR950011556B1 (ko) * | 1992-07-03 | 1995-10-06 | 현대전자산업주식회사 | 반도체 접속장치 형성방법 |
KR960002064B1 (ko) * | 1992-11-16 | 1996-02-10 | 현대전자산업주식회사 | 반도체 소자의 콘택 제조방법 |
US5378641A (en) * | 1993-02-22 | 1995-01-03 | Micron Semiconductor, Inc. | Electrically conductive substrate interconnect continuity region and method of forming same with an angled implant |
-
1993
- 1993-12-31 KR KR93031912A patent/KR970009617B1/ko not_active Expired - Lifetime
-
1994
- 1994-12-28 JP JP6327748A patent/JP2557206B2/ja not_active Expired - Fee Related
- 1994-12-29 US US08/365,954 patent/US5770464A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR970009617B1 (en) | 1997-06-14 |
JPH07326753A (ja) | 1995-12-12 |
US5770464A (en) | 1998-06-23 |
JP2557206B2 (ja) | 1996-11-27 |
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