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KR920001750A - 반도체 장치 및 그 제조방법 - Google Patents

반도체 장치 및 그 제조방법 Download PDF

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Publication number
KR920001750A
KR920001750A KR1019910010434A KR910010434A KR920001750A KR 920001750 A KR920001750 A KR 920001750A KR 1019910010434 A KR1019910010434 A KR 1019910010434A KR 910010434 A KR910010434 A KR 910010434A KR 920001750 A KR920001750 A KR 920001750A
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KR
South Korea
Prior art keywords
insulating film
semiconductor device
substrate
impurity
wiring layer
Prior art date
Application number
KR1019910010434A
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English (en)
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KR940008729B1 (ko
Inventor
히로유키 노지
고이치 기시
유스케 고야마
소이치 스기우라
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이크로 일렉트로닉스 가부시키가이샤
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Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바 마이크로 일렉트로닉스 가부시키가이샤 filed Critical 아오이 죠이치
Publication of KR920001750A publication Critical patent/KR920001750A/ko
Application granted granted Critical
Publication of KR940008729B1 publication Critical patent/KR940008729B1/ko

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음.

Description

반도체장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도(a) 내지 제1도(j)는 본 발명의 1실시예에 따른 CMOS형 반도체장치를 제조공정순으로 각각 도시한 단면도.
제2도는 상기 실시예에 따른 MOSFET의 깊이에 따른 불순물농도변화의 시뮬레이션결과를 나타낸 도면.
제3도는 질화막이 없는 종래의 MOSFET의 깊이에 따른 불순물농도변화의 시뮬레이션결과를 나타낸 도면이다.
* 도면의 주요부분에 대한 부호의 설명
10 : P형 실리콘기판 18 : 게이트산화막
20B : 게이트전극 29 : 불화보론이온
30 : 불화보론이온 주입부분 30A : p+형 소스/드레인영역
30B : 낮은 불순물농도의 p형 소소/드레인영역
32B : 측벽 34 : 질화막

Claims (6)

  1. 제1도전형의 반도체기판(14)상에 이 기판(14)과 절연된 상태로 형성된 배선층(20B)과, 이 배선층(20B) 양옆에 대응되는 상기 기판(14)내에 형성된 적어도 2개의 제 2도전형 확산층(30) 및, 상기 배선층(20B)의 측부에 접하면서 상기 확산층(30)의 위쪽을 일부 덮도록 형성된 측부절연막(32B)을 갖춘 반도체장치에 있어서, 적어로 상기 확산층(30)에 대응되는 위쪽에 형성되어 상기 반도체장치의 제조시에 상기 확산층(30)을 구성하는 불순물의 확산을 제어하는 내산화성 절연막(34)을 갖추고서, 상기 내산화성 절연막(34) 바로 아래의 확산층(30A)의 불순물농도가 상기 측부절연막(32B) 바로 아래의 확산층(30B)의 불순물농도보다 높게된 것을 특징으로 하는 반도체장치.
  2. 제1항에 있어서, 상기 내산화성 절연막(34)이 질화막인 것을 특징으로 하는 반도체장치.
  3. 제1항 또는 제2항중 어느 1항에 있어서, 상기 불순물이 보론인 것을 특징으로 하는 반도체장치.
  4. 제1도전형의 반도체기판(14)상에 이 기판(14)과 절연된 상태로 도체층(20)을 형성하는 공정과, 상기 도체층(20)을 패터닝하여 배선층(20B)을 형성하는 공정, 형성된 상기 배선층(20B)을 마스크로 하여 상기기판(14)내에 제2도전형의 불순물(29)을 도입하는 공정, 전면에 절연막(32)을 형성하는 공정, 상기 배선층(20B)의 측부에 상기 절연막(32)이 남도록 상기 절연막(32)을 에칭하여 측부절연막(32B)을 형성함과 더불어 상기 불순물(29)이 도입된 기판(14)표면의 일부를 노출시키는 공정 및, 산화성 분위기에서 상기 불순물(29)을 활성화 열처리하는 공정을 구비하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
  5. 제4항에 있어서, 상기 내산화성 절연막화가 질화인 것을 특징으로 하는 반도체장치의 제조방법.
  6. 제4항 또는 제5항에 있어서, 상기 불순물이 보론인 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910010434A 1990-06-27 1991-06-24 반도체장치 및 그 제조방법 KR940008729B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2168931A JP2907344B2 (ja) 1990-06-27 1990-06-27 半導体装置およびその製造方法
JP02-168931 1990-06-27

Publications (2)

Publication Number Publication Date
KR920001750A true KR920001750A (ko) 1992-01-30
KR940008729B1 KR940008729B1 (ko) 1994-09-26

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US (1) US5266823A (ko)
JP (1) JP2907344B2 (ko)
KR (1) KR940008729B1 (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE1007221A3 (nl) * 1993-06-15 1995-04-25 Philips Electronics Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
JPH07335904A (ja) 1994-06-14 1995-12-22 Semiconductor Energy Lab Co Ltd 薄膜半導体集積回路
US6433361B1 (en) 1994-04-29 2002-08-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor integrated circuit and method for forming the same
JP3312083B2 (ja) * 1994-06-13 2002-08-05 株式会社半導体エネルギー研究所 表示装置
US5525064A (en) * 1995-01-19 1996-06-11 Teledyne Electronic Technologies Connector with molded stud(s) and insulated nuts
JPH08250728A (ja) * 1995-03-10 1996-09-27 Sony Corp 電界効果型半導体装置及びその製造方法
JP3472655B2 (ja) * 1995-10-16 2003-12-02 ユー・エム・シー・ジャパン株式会社 半導体装置
KR100226740B1 (ko) * 1997-03-12 1999-10-15 구본준 반도체 소자의 제조방법
US6221709B1 (en) * 1997-06-30 2001-04-24 Stmicroelectronics, Inc. Method of fabricating a CMOS integrated circuit device with LDD N-channel transistor and non-LDD P-channel transistor
US7245018B1 (en) * 1999-06-22 2007-07-17 Semiconductor Energy Laboratory Co., Ltd. Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof
US6992152B2 (en) * 1999-10-19 2006-01-31 Texas Petrochemicals Lp Apparatus and method for controlling olefin polymerization process
KR100411304B1 (ko) * 2001-06-30 2003-12-18 주식회사 하이닉스반도체 동기식 디램 소자의 제조방법

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4623912A (en) * 1984-12-05 1986-11-18 At&T Bell Laboratories Nitrided silicon dioxide layers for semiconductor integrated circuits
JPS63217655A (ja) * 1987-03-06 1988-09-09 Toshiba Corp 半導体装置の製造方法
JP2559397B2 (ja) * 1987-03-16 1996-12-04 株式会社日立製作所 半導体集積回路装置及びその製造方法

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Publication number Publication date
US5266823A (en) 1993-11-30
JPH0457337A (ja) 1992-02-25
KR940008729B1 (ko) 1994-09-26
JP2907344B2 (ja) 1999-06-21

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