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KR850005736A - Cmos 직접회로 - Google Patents

Cmos 직접회로 Download PDF

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Publication number
KR850005736A
KR850005736A KR1019850000281A KR850000281A KR850005736A KR 850005736 A KR850005736 A KR 850005736A KR 1019850000281 A KR1019850000281 A KR 1019850000281A KR 850000281 A KR850000281 A KR 850000281A KR 850005736 A KR850005736 A KR 850005736A
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circuit
mos transistor
cmos
semiconductor substrate
substrate
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KR1019850000281A
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KR890004472B1 (ko
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카즈히꼬 쯔지
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야마시다 도시히꼬
마쯔시다덴기산고 가부시기 가이샤
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/206—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of combinations of capacitors and resistors

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

CMOS 직접회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 CMOS 직접회로의 개략평면도.
제2도는 제1도의 X-Y선을 따라 절취한 CMOS 집적회로의 단면도.
제3도는 제2도의 CMOS 집적회로의 대응회로도.
제4도는 래치업효과를 설명하기 위한 CMOS 집적회로의 회로도.

Claims (16)

  1. 제1도전형 반도체기판(12)(12')과, 상기 반도체기판(12)(12')에 형성된 제2도전형 불순물층(10)(10')과, 상기 반도체기판(12)(12')에 형성된 제1 MOS트랜지스터와, 상기 불순물층(10)(10')에 형성된 제2MOS트랜지스터와, 상기 제1 MOS트랜지스터와 제2 MOS트랜지스터에 전압을 공급하는 전원수단과, 상기 제1 MOS트랜지스터 및 제2 MOS트랜지스터중 적어도 하나의 하부에 위치한 상기 반도체기판(12)(12') 및 불순물층(10)(10')중 적어도 하나이상에 형성되어서 상기 전원수단과 상기 제1 및 제2 MOS트랜지스터중 적어도 하나와의 사이에 전기적으로 접속된 한개 이상의 저항(R1)(R2)으로 구성된 CMOS 집적회로.
  2. 제1항에 있어서, 상기 반도체기판(12)은 N형이고, 상기 불순물층(10)은 P형이며, 상기 제1 MOS트랜지스터(14)는 P채널형이고, 상기 제2 MOS트랜지스터(22)는 N채널형인 것을 특징으로 하는 CMOS 집적회로.
  3. 제1항에 있어서, 상기 반도체기판(12')은 P형이고, 상기 불순물층(10')은 N형이며, 상기 제1 MOS트랜지스터(22)는 N채널형이고, 상기 제2 MOS트랜지스터(14)는 P채널형인 것을 특징으로 하는 CMOS 집적회로.
  4. 제1항에 있어서, 상기 전원수단은 전원회로와 접지회로를 가지며, 상기 전원회로는 상기 저항을 통하여 상기 제1MOS트랜지스터에 접속된 것을 특징으로 하는 CMOS 집적회로.
  5. 제1항에 있어서, 상기 전원수단은 전원회로와 접지회로를 가지며, 상기 접지회로는 상기 저항을 통하여 상기 제2 MOS트랜지스터와 접속된 것을 특징으로 하는 CMOS 집적회로.
  6. 제1항에 있어서, 상기 전원수단은 전원회로와 접지회로를 가지며, 상기전원회로는 제1 저항을 통하여 상기 제1 MOS트랜지스터에 접속되고, 상기 접지회로는 제2 항을 통하여 상기 제2 MOS트랜지스터에 접속된 것을 특징으로 하는 CMOS 집적회로.
  7. 제1항에 있어서, 상기 저항은 상기 반도체기판(12)(12')과 불순물층(10)(10')중 적어도 하나의 일부를 사용하여 형성시킨 것을 특징으로 하는 CMOS 집적회로.
  8. 제1항에 있어서, 상기 제1 및 제2 MOS트랜지스터는 상보회로를 형성하는 것을 특징으로 하는 CMOS집적회로.
  9. 제1도전형 반도체기판(12)(12')과, 상기 반도체기판(12)(12')에 형성된 제2도전형 불순물층(10)(10')과, 상기 반도체기판(12)(12')에 형성된 제1 MOS트랜지스터 및 상기 불순물층(10)(10')에 형성된 제2 MOS트랜지스터를 가진 CMOS 회로와, 상기 반도체기판(12)(12') 및 불순물층(10)(10')중 적어도 하나의 일부를 통하여 상기 CMOS 회로와 전기적으로 접속되어서 상기 CMOS 회로에 전압을 공급하는 전원수단으로 구성되고, 상기 반도체기판(12)(12')과 불순물층(10)(10')중 적어도 하나의 일부는 상기 CMOS 접적회로의 래치업효과를 방지하기 위한 저항의 기능을 하도록 된 CMOS 집적회로.
  10. 제9항에 있어서, 상기 반도체기판(12')은 P형이고, 상기 불순물층은 상기 P형 반도체기판(12')에 형성된 N웰(10')이며, 상기 전원수단은 상기 N웰(10')의 일부를 통하여 상기 제2 MOS트랜지스터에 전기적으로 접속된 것을 특징으로 하는 CMOS 집적회로.
  11. 제9항에 있어서, 상기 전원수단은 상기 반도체기판(12)(12')의 일부를 통하여 상기 제1 MOS트랜지스터에 전기적으로 접속된 것을 특징으로 하는 CMOS 집적회로.
  12. P형 실리콘기판(12')과, 상기 기판(12')에 형성된 N웰(10')과 상기 기판에 형성된 N채널형 MOS트랜지스터 및 상기 N웰(10')에 형성된 P채널형 MOS트랜지스터를 가진 CMOS 회로와, 전압이 인가되는 전원회로와, 상기 CMOS 회로부로부터 이격되게 상기 N웰(10')에 형성되어서 상기 전원회로와 전기적으로 접속된 단자전극으로 구성되며, 상기 CMOS회로부와 단자적극사이에 위치한 상기 N웰(10')의 일부는 상기 CMOS집적회로의 래치업효과를 방지하기 위한 저항의 기능을 하도록 된 CMOS 집적회로.
  13. 제12항에 있어서, 상기 CMOS회로와 접지와의 사이에 전기적으로 접속된 외부저항(ra)을 가진것을 특징으로 하는 CMOS 집적회로.
  14. N형 실리콘기판(12)과, 상기 기판(12)에 형성된 P웰(10)과, 상기 기판(12)에 형성된 P채널형 MOS트랜지스터 및 상기 P웰에 형성된 N채널형 MOS트랜지스터를 가진CMOS 회로와, 전압이 인가되는 전원회로와, 상기 CMOS 회로부로부터 이격되게 상기 기판에 형성되어서 상기 전원회로와 전기적으로 접속된 제1단자전극과, 상기 CMOS 회로부로부터 이격되게 상기 P웰에 형성되어서 상기 바닥에 전기적으로 접속된 제2단자전극으로 구성되며, 상기 제1 단자전극과 CMOS 호로부사이에 위치한 상기 기판의 일부와 상기 제2 단자전극와 CMOS 회로부사이에 위치한 상기 P웰(10)의 일부는 상기 CMOS 접적회로의 래치업효과를 방지하기 위한 저항(R1)(R2)의 기능을 하도록 된 CMOS 집적회로.
  15. 반도체기판(12)(12')과, 상기 기판(12)(12')에 형성되며 CMOS 구조를 포함하는 다수의 메모리셀(50)과, 상기 메모리셀(50)과 이격된 위치에 형성되어서 상기 메모리셀(50)하부의 상기 기판부분을 통하여 상기 메모리셀(50)과 전기적으로 접속된 상기 메모리셀(50)에 전압을 공급하기 위한 전원회로로 구성되며, 상기 기판의 일부는 상기 메모리셀(50)의 래치업효과를 방지하기 위한 저항(R1)(R2)의 기능을 하도록 된 반도체 메모리장치.
  16. 제15항에 있어서, 상기 저항(R1)(R2)은 상기 메모리셀(50)의 하부에 배열된 것을 특징으로 하는 반도체 메모리장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019850000281A 1984-01-20 1985-01-18 Cmos 집적회호 KR890004472B1 (ko)

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Application Number Priority Date Filing Date Title
JP85-281 1984-01-20
JP59008721A JPS60152055A (ja) 1984-01-20 1984-01-20 相補型ｍｏｓ半導体装置
JP8721 1984-01-20

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KR890004472B1 KR890004472B1 (ko) 1989-11-04

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Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60231356A (ja) * 1984-04-28 1985-11-16 Mitsubishi Electric Corp 相補形金属酸化膜半導体集積回路装置
US4908688A (en) * 1986-03-14 1990-03-13 Motorola, Inc. Means and method for providing contact separation in silicided devices
JPS63278248A (ja) * 1987-03-13 1988-11-15 Fujitsu Ltd ゲ−トアレイの基本セル
JP2722453B2 (ja) * 1987-06-08 1998-03-04 三菱電機株式会社 半導体装置
JPH0713871B2 (ja) * 1987-06-11 1995-02-15 三菱電機株式会社 ダイナミツクｒａｍ
JPS648659A (en) * 1987-06-30 1989-01-12 Mitsubishi Electric Corp Supplementary semiconductor integrated circuit device
US5117274A (en) * 1987-10-06 1992-05-26 Motorola, Inc. Merged complementary bipolar and MOS means and method
US4947228A (en) * 1988-09-20 1990-08-07 At&T Bell Laboratories Integrated circuit power supply contact
US5274262A (en) * 1989-05-17 1993-12-28 David Sarnoff Research Center, Inc. SCR protection structure and circuit with reduced trigger voltage
US5072273A (en) * 1990-05-04 1991-12-10 David Sarnoff Research Center, Inc. Low trigger voltage SCR protection device and structure
US5003362A (en) * 1989-07-28 1991-03-26 Dallas Semiconductor Corporation Integrated circuit with high-impedance well tie
US5021858A (en) * 1990-05-25 1991-06-04 Hall John H Compound modulated integrated transistor structure
US5317183A (en) * 1991-09-03 1994-05-31 International Business Machines Corporation Substrate noise coupling reduction for VLSI applications with mixed analog and digital circuitry
JP3184298B2 (ja) * 1992-05-28 2001-07-09 沖電気工業株式会社 Ｃｍｏｓ出力回路
JPH09199607A (ja) * 1996-01-18 1997-07-31 Nec Corp Ｃｍｏｓ半導体装置
US5883566A (en) * 1997-02-24 1999-03-16 International Business Machines Corporation Noise-isolated buried resistor
GB2394833B (en) * 2000-08-11 2005-03-16 Samsung Electronics Co Ltd Protection device with a silicon controlled rectifier
US7132696B2 (en) 2002-08-28 2006-11-07 Micron Technology, Inc. Intermeshed guard bands for multiple voltage supply structures on an integrated circuit, and methods of making same
US9842629B2 (en) 2004-06-25 2017-12-12 Cypress Semiconductor Corporation Memory cell array latchup prevention
US7773442B2 (en) * 2004-06-25 2010-08-10 Cypress Semiconductor Corporation Memory cell array latchup prevention
FR2872630B1 (fr) * 2004-07-01 2006-12-01 St Microelectronics Sa Circuit integre tolerant au phenomene de verrouillage
JP5135815B2 (ja) * 2006-02-14 2013-02-06 ミツミ電機株式会社 半導体集積回路装置
US7834428B2 (en) * 2007-02-28 2010-11-16 Freescale Semiconductor, Inc. Apparatus and method for reducing noise in mixed-signal circuits and digital circuits
KR102248282B1 (ko) * 2014-01-21 2021-05-06 삼성전자주식회사 Cmos 반도체 장치
US10410934B2 (en) * 2017-12-07 2019-09-10 Micron Technology, Inc. Apparatuses having an interconnect extending from an upper conductive structure, through a hole in another conductive structure, and to an underlying structure
US10861848B2 (en) * 2018-08-23 2020-12-08 Xilinx, Inc. Single event latch-up (SEL) mitigation techniques
EP3944316A1 (en) * 2020-07-21 2022-01-26 Nexperia B.V. An electrostatic discharge protection semiconductor structure and a method of manufacture

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5910587B2 (ja) * 1977-08-10 1984-03-09 株式会社日立製作所 半導体装置の保護装置
JPS5939904B2 (ja) * 1978-09-28 1984-09-27 株式会社東芝 半導体装置
JPS6046545B2 (ja) * 1980-05-16 1985-10-16 日本電気株式会社 相補型ｍｏｓ記憶回路装置

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KR890004472B1 (ko) 1989-11-04
JPS60152055A (ja) 1985-08-10
JPH0315348B2 (ko) 1991-02-28
US4672584A (en) 1987-06-09

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