JPS61141432A - Display device for camera - Google Patents

Abstract

PURPOSE:To reduce the size of a display device and to make easily visible the display by displaying selectively an override quantity and metered manual deviation quantity on the same display device. CONSTITUTION:An arithmetic means for the override quantity, an arithmetic means for the metered manual deviation quantity and a set of display means provided commonly to the respective arithmetic means are provided. The display is so changed over by a control means that the result calculated by the arithmetic means for the metered manual deviation quantity is displayed by the above- mentioned display means in the metered manual setting stage and that the result calculated by the arithmetic means for the override quantity is displayed by the above-mentioned display means in case excet the metered manual setting stage.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a display device for a camera.

BACKGROUND ART Camera display devices are known that digitally display a so-called override amount, which is slightly larger or smaller than the appropriate exposure amount obtained from photometry results, in an auto mode for automatically controlling the exposure amount in a conventional camera. On the other hand, a camera display device is also known that displays the amount of deviation of the set exposure value from the appropriate exposure value, so-called metered manual deviation, in the manual mode.

In a camera that displays these override amounts and metered manual deviation amounts, if all of the display contents are displayed on a separate display section, the space required for the display section will be large.

On the other hand, in the manual mode, there is no need to display the override amount, and on the other hand, in the auto mode, there is no need to display the metered manual deviation amount.

OBJECTS OF THE INVENTION The present invention has been made with attention to the above-mentioned points, and an object of the present invention is to provide a display device for a camera that can perform required display in a small space.

Structure of the Invention The camera display device of the present invention includes an override amount calculation means, a metered manual deviation amount calculation means, a set of display means provided in common for each of the above calculation means, and a metered manual setting. At times, the result calculated by the deviation amount calculation means of the metered manual is displayed by the display means, and in cases other than when the metered manual is set, the result calculated by the override amount calculation means is displayed by the display means. It is characterized by comprising a control means for switching.

In the operation manual mode, the display of the override amount is meaningless, but the metered manual deviation amount display is important, so in the manual mode, a meter is displayed in the above display area.

On the other hand, except when in manual mode, there is no need to display the metered manual deviation amount, and since it is important to display the override amount, the above display section will erase the metered manual deviation amount display and replace it with Display override values.

Embodiment FIG. 1 is a diagram showing the external appearance of a camera to which this invention is applied. L is the camera body, 2 is a shutter button, 3 is an interchangeable lens, and the interchangeable lens 3 contains data about the lens, such as the maximum aperture value. A device is provided that outputs data indicating such information as an electrical signal to the camera body. Further, the shutter button 2 is provided with a photometric switch St and a release switch S2, which are operated according to the amount of depression of the button, by a known method.

Reference numeral 4 denotes an external display section, which displays the calculated EV value and operation mode, as well as various other data that will be described in detail later.

5 is a finder, and within the field of view of this finder 5 is provided an internal display section 6 (see FIG. 2) for displaying data and the like displayed on the external display section 4.

SM is the main switch.

Figure 2 shows details of the display on the external display section 4.
OPROGFLAMSh for A1-code display
.

be. When the AE mode is a program mode (hereinafter referred to as P mode), PROGRAM is displayed and S is turned off, and when the AE mode is in aperture priority mode (hereinafter referred to as A mode), A is displayed and PROCR and MS are turned off. Manual mode (hereinafter referred to as
(referred to as M mode) and shutter time priority mode (referred to as
(hereinafter referred to as S mode), M and S are displayed, respectively. Below that is the SO mark in ISOS-mode, immediately below there is a 7-segment 4-digit SS, ISO, and CTR display, and to the right of it is a setting instruction mark TAI゛
There is. Below that is the camera's main switch S.
There is a 7-segment, 2-digit F, +/- display across the bar display, which only turns off when M is turned off, and a setting instruction mark TA2 on the right side of it. To the left of the two digits is an aperture value discrimination mark F, and further to the left end is a +/- mark, which is a sign when override 1 is set.

Furthermore, FIG. 2C shows details of the display on the internal display section 6.
Starting from the left end, there are 2 adjacent images for displaying camera shake (camera shake).
Mark CAI has two camera shapes.

There is CA2, followed by 7 segment 4 digit SS.

There are ISO and CTR display sections, followed by S, P, and A for AE mode display. The S mark consists of a 7-segment arrow pointing toward the 4-digit side to indicate shutter speed priority.
Similarly, the A mark is located immediately to the right to indicate aperture priority.
The segment consists of an arrow pointing toward the 2-digit side. The P mark has nothing to do with prioritizing both aperture and seconds, so there is no arrow between S and A.The 7 segment 2 digits on the right side for AE mode display are for F value display and +/- mode. Displays the +/- value of. Immediately to the right of that is the 8 M for mode display.
There is a mark. This is because the metered manual display lights up at the same time, so it is displayed near the meter display to make it easier to understand. To the right are the override and metered manual symbols, tens and -, followed by a seven-segment numerical band. This numerical band is the +/- billion display (P, A.

(Only in S mode) and also displays the metered manual value in <AE mode (Only in M mode).

Finally, there are the ASI and AS2 marks that indicate the metering mode. For average metering, only ASI lights up, and for partial metering,
Both ASI and AS2 are lit camphors.

Fig. 32 a, b1 Fig. 33 a, b shows the override being displayed, but in the internal display of the finder, the place where the override value is displayed is the override (+/-
) mode and AE mode. This is an attempt to display information near the center of the display section during override mode display to make it easier to understand.

FIG. 3 shows the overall configuration of the control device related to the above-mentioned camera display. The CPU10, which uses a central control micro combinator that controls the operation of the entire camera, is supplied with a power supply element E from the battery 11, the main switch SM pulled up by a resistor R, the reference oscillator XL1 for operating the CPU10, and peripherals. A group of control signals for circuits (especially for displays).

C5, PWC, serial data 5DATA necessary for serial data transfer, and a normal clock SCK are connected to the peripherals.

An outline of the operation of CPU10 will be described later.

On the other hand, the display circuit section 20 receives the power supply element E from the battery 11, the main switch SM, the signals C8 and PWC from the CPU10,
5DATA, SCK, 1ffi from standard! XL2. A reference voltage ji21 for driving the liquid crystal is inputted, and outputs include a group of driving outputs for common and segment electrodes of the external display section 4 and internal display section 6 using a liquid crystal display. The drive output terminal group is connected to the external display section 4 of the camera and the external display section 6 inside the shearing goo, which are connected in parallel.

Inside the display circuit 20, there is a data latch section 22 that latches serial data. Decoder section 23 that decodes the latched data. Segment driver unit 2 that drives the LCDs of external and internal display units 4 and 6 using decoded signals
4. Common driver section 25 that drives the common section of the LCD
．． Oscillation frequency dividing section 26 that creates operating clocks for each section. L.C.
There is also a voltage generating section 27 that generates a driving voltage of D.
FIG. 4 is a detailed diagram of the oscillation frequency dividing section 26 shown in FIG. ). The flip-flop FFI is provided with a reset terminal R so that it can be initialized by installing a battery.

FIG. 5 is a detailed diagram of the common driver section 25.
, VLCD2. Each voltage of VDD is connected to analog switch A.
SI ~ AS4 and PchFET FPI, φ1 through FP2. It is configured to output to COMI and C0M2 at a timing of φ8°. Nantes Gate NA1.2. NOR gate NRI,2 and inverter IN3.4 are gates for creating timing.

The sixth piece is a part of the detailed diagram of the segment driver part 24,
VLCD2. The analog switch AS6 and PchFET EP3 for switching each voltage of VDD are made of φ1. φ,. Among the timings of the segment data S2n, 52n-
It is configured to be driven according to the state of No. 1. Nant gates NA3 to NA7 and inverter IN6.7 are S2n
, 52n-1 constitutes a clock selector, and inverters IN5. Flip-flop FF2 is φ. ,φ,.

Glue a to create clocks with four types of phase differences from
It constitutes a Tsuku generator.

The entire segment driver section is of the type shown in FIG. 6, in which the clock selector, analog switch, and PchFET parts are prepared in the same number as the SEG output terminals, and a clock generator is added.

FIG. 7 is a detailed diagram of the data latch unit 22. There are seven 8-bit soft registers Sl'tl-SR7 that input serial data 5DATA from CPUl0, and the parallel outputs of these soft registers are connected to the falling edge of the LTCH signal. Seven 8-bit latches LTI-L
Connected to T7.

The reset R input is applied to the jlO data of the latch LTI, and the set S input is applied to the 01 data, and the j10 data and HI data are power-on reset FOR, respectively.
Reset and set by signal. Therefore, the initial state is j10='Low' and jl1='High'.

On the other hand, the external serial clock SCK is
Noah game 1-NR3~N as φS signal passed through ORI
It becomes the input of R9, and also serves as the φ input of the counter decoder CD. Set input S of counter decoder CD
When h4 is "High", the outputs B5l-B57 of counter decoder CD are all "High", and the S input is "
When it becomes “Low”, BSI is activated sequentially every 8 pulses of φλ force.
to BS7 becomes "Low".

When any one of B11 to B57 is "Low-", one of the corresponding NOR gates NR3 to NR9 becomes active, and the φS signal input to the NOR gate is sent to the φλ of one of the serial registers 5RI to 8R7. External control signal pw from CPU 10
c and cs are logically summed by the OR gate OR3 to become the P-C8 signal, which is input to the other input of the OR gate OR1 and the S input of the counter decoder. Also, one input of the OR gate OR2 and the other input B
An OR logic is performed with S7, and it becomes the D input of flip-flop FF3 and one of the NAND games) NA8. For the flip 70 tube FF3, the FOR signal is input to the set human power S, and the silkworm output is connected to the other input of NA8. Further, the φ and specific output in FIG. 4 are connected to the φλ force of the flip-flop FF3.

FIG. 8 is a detailed block diagram of the decoder section 23 of FIG. 3, which includes switch circuits SWI, Sw2 . Data converter DCI to DC
4. Segment decoder sections SDI to SD6. It is composed of an output control section CTLl. The switch circuit SW1 receives the outputs j12 to H of the decoder 22 as human power.
e, j22-j27, j32-j37. j4
25 outputs j50 to j53 of the decoder 22 are input to the data conversion unit DC3, and outputs j10 and jn of the decoder 22 are input to the data conversion unit DC4.
1j20. j211 j54
~ j57. j60~j67゜j70~j77-2
A total of 53 wires, including four wires, are connected to the outputs of latches LTI to LT7 in FIG. In addition, the data converter I)C4 has a third
The two main switch signals SM and PWC (7) shown in the figure are input. As shown in Figure 4, output controller section CTLII has φ, 4 connected as an input, and 5 as an output.
70 l-370 are connected to the segment driver section 24.

FIG. 9 is a detailed diagram of the switch circuit SWI in FIG. 8,
jn from data latch 22 (n = 12 to 47 (excluding 17.2 G, 21.30.31)) → Pn
(n = 12-47 (however, 17.20.30゜31
25 signals to 25 Nants gates N
'Use A, FOM, CTR, ISO.

It is switched by the SS signal. FON, CTR.

When the ISO and SS signals are “Lo 2”, the Pn signal is “
The jn signal becomes “High” and is cut off, but the FON.

When the CTR, ISO, and SS signals are “High@”, Pn
= jn, and the request is turned on.

FIG. 10 is a diagram explaining the symbols used in FIG. 11, FIGS. 13 to 15, and FIG. 23, including A, B, and C.

For each input of D, the same function as the Nantes gate is indicated by marking the intersection of the arrow with the output Q. That is, Q
=B-D.

FIG. 11 is a detailed diagram of the data conversion unit DC3 in FIG.
The logic of outputs p1 to p9 is shown for inputs 550 to j53. This output is powered by the switch circuit SW2 in FIG.

FIG. 12 is a detailed diagram of the switch circuit SW2 of FIG. 8, showing the logic in which the input pi-99 is switched to q71-q78 and qs2-Q89 by the switching signal MO+/-ON signal. When the human p signal is input to the Nantes gate, and the switching signal MON and +/-ON signal are Low, the output q signal becomes High and the p signal is cut off. At times, the output q signal is equal to the input p signal, resulting in a switched-on state.

FIG. 13 shows the segment decoder sections SDl to SD in FIG.
In the detailed diagram of 4, the output rl-r2 for the input qt-439
It shows the logic of 9. The diagram shows segment decoder section 5.
Since the basic configurations of the DI-5D4 are the same, they are shown in the same drawing, but the necessary parts of the 5DI-3D4 are extracted from this drawing. This output is an input to the output control section CTLI shown in FIG.

FIG. 14 is a detailed diagram of the data converter DC2 of FIG. 8, showing the logic of outputs q40 to Q62 for inputs p12 to p16. This output is from the segment decoder SD in Figure 8.
It is now input 5.

FIG. 15 is a detailed diagram of the segment decoder section SD5 of FIG. 8, in which inputs q40 to Q62. For Q71 to q78,
The logic of outputs r30 to r43 is shown. This output is the 8th
It is an input to the output control unit CTLl shown in the figure.

FIG. 16a is a part of a detailed diagram of the output control section CTLl of FIG. 8, in which outputs of S1 to S70 are obtained by the outputs of the segment decoder sections 5DI-SD6 and data conversion JIDC4 and the clock φ14.

In this figure, r2n and Ba are shown in arbitrary combinations, but in reality they are connected in the combinations shown in Table 1.

Table 1 shows a truth table by replacing the circuit diagram of FIG. 16a with logical expressions. Furthermore, a combination of r2n and 8 meals is specifically shown. (l≦−≦8).

(l≦2n≦68) r69 is shown in FIG.

FIG. 16 shows input r69 and output s69. It shows the logic to s70.

FIG. 17 shows the relationship between the output ql-q39 of the data conversion unit DC1 of the decoder unit 23 and the characters displayed on the display units 4 and 6, and the inputs p22 to p2 to the data conversion unit DC1.
27. p32-p37, p4 G-p47. When ql-q39 is output according to the shape of CTR, q1-q3
The displayed characters are controlled according to the state of 9, "LO level" or "High".

That is, if the output qt is "High", it is 501. Therefore, the display of the 10a digit on the display section 4 (upper 6) is 0° If q2 is "High", the display of the 10o digit is 2.
ta' i ya 7. Engineering, 81. , Ia, yo2゜2
! ~p27, p32~p for ISO values
37. Regarding the CTR value, data is given in p40 to p47 and the CTR signal, respectively. Also, p22~p27゜p3
2 to p37 and p40 to p47 are all “High.”
", the configuration is such that no output is output for that data. Therefore, for example, when the data of p22 to p27 for the shutter speed SS value is output, the other p32 to p37. p40 to p47 are all ". High
data converter DC4 and switch circuit S so that
It is composed of WI. (See FIGS. 9 and 21) The contents that can be displayed are illustrated in FIG. 18. There are 36 types of SS values, 31 types of ISO values, and 100 types of CTR values.

19 and 20 are diagrams showing the relationship between the data of the data conversion unit DC2 and the switch circuit SW2 and the characters displayed on the display units 4 and 6.
p12-p16 and SW2 pi-p9, MON, +
/-q40 to q62. depending on the ON state. q71-q
7B, q82 to q89 output data as shown in this figure. p12 to p16 for F value, p1 for override value and metered manual value
Data are given on p.9.

FIG. 21 is a part of a detailed diagram of the data converter DC4 of FIG. 8, and shows switch switching signals MON, +/-ON, and FON of switch circuits SW1 and SW2.

CTR, ISO, SS logic and CTLI section ON,
The logic of the OFF signal and the logic of the 0FFVLCD signal applied to the voltage generator 27 in FIG. 3 are shown, respectively. The input signal is the output signal j10. of the data latch section. H1, j55.
j56. j60～j67゜j70. j71 and cF, outside f
f signal, SM, and PWC.

FIG. 22 is a part of a detailed diagram of the data converter DC4 in FIG. 8, and shows B! of the CTL1 section. ~B8 shows the logic of the signal.

The input signals are the output signals j2o and j55 of the data latch section.
~Co57. j61-j64° j70-j74 and the external signal PWτ.

FIG. 23 is a part of a detailed diagram of the data conversion aBDc4 in FIG. 8, and shows the logic of the r51 to r69 signals of the control ffcTL1. The input signal is the output signal j21. of the data latch section. j54～j57゜j70～j73. j7
5 to j77 and the output signal q40 of the DC2 section. and an external signal PWτ. 21 to 23 include all the data conversion section DC4 of FIG. 8.

FIG. 24 is a detailed diagram of the voltage generating section 27. By creating a reference voltage V LCD externally by connecting a diode DI and a resistor R1 between +E and GND, and supplying it to the booster circuit 27a (the part surrounded by the broken line) including the capacitor C6C1,
(+E-VLCD) double voltage (10E-V LCDI)
occurs. Both V LCD and V LCDI are led to V LCD0 and V LCD2, respectively, by an output control circuit made of an analog switch and a PchFET.

V LCD0 and V LCD2 are 0FFVLCD17>
Changes the output depending on the state. 0FFVLCDhzeL
ow”, VLCDO=VLCD, VLCD2
= VLCDl, and 0FFV LCD is “High”
When , V LCD0 = V LCD2 = V D
It becomes D.

Further, the booster circuit section 27a obtains a clock from φ6 in FIG. 8 to switch the connection of the capacitors C+ and Ct to boost the voltage. Further, FOR is a terminal for starting the booster circuit, and POI' shown in FIG. 8 is started by outputting it.

FIG. 26 is a time chart of the data latch section 22 of FIG. 7. Both external signals pwc and cs become "L, ow", and at the falling edge of SCK, the serial register SRI ~
The data in SR7 will be rewritten.

The falling edge of the 8th pulse at the beginning of SCK "The contents of 6SR1 are all rewritten, and from the 9th pulse, the shift registers SR2 to SR7 are rewritten every 8 pulses. The 49th pulse immediately after SR6 is rewritten. At the rising edge of φ, BS7 becomes “Low” and rewriting of SR7 begins.At the same time, flip-flop FF3 reads the D input at the rising edge of φY, so the 4 outputs of FF3 become “L”.
OW” and does not change until BS7 becomes “High” again.

The output of the LTCH and the P-CS signal result in LTCH pulses, 1 to 8, 7, a, 7, 8. .
1 content is taken into the latch of LTI-LT7.

FIG. 25 is a time chart showing the overall general operation from after the battery is installed in the camera. Immediately after the battery is installed, the display circuit section 20 is initialized by the FOR signal. Signal VLC
DI becomes earth GND level and 0FPVLCD becomes “
Therefore, no voltage is applied to the liquid crystal.Then, the CPU I0(7)XLI starts oscillating, and the CPU starts operating.After a while, the oscillator XL2 of the display circuit section 20 starts oscillating, and the clock φ.

~φ14 starts to start. When the clock φ starts operating, the data latch section 22 starts operating, and when serial data comes from CPU10, it operates as shown in FIG. 26. When the clock φ starts operating, the voltage generating section 27 shown in FIG. 24 starts operating, and after a short period of time, the potential of the signal VLCDI becomes stable. After that, OF F V'LC as necessary.
If D is set to "L ov'", the liquid crystal drive voltage, VL
CDO and VLCD 2 are supplied to display sections 4 and 6.

28 to 35 and 37 to 39 show various display styles of the external display section 4 and the internal display section 6, and each figure a except for FIG. 37 shows the external display section 4, Each figure shows the display on the internal display section 6.

Figures 28a and 28b are AE displays in program mode, showing auto second time 1/250, auto aperture value 5°6, program PROGRAM, and reverse discharge.

The mark ASI at the right end of FIG. 28 indicates the photometry mode and indicates average photometry. .

Figures 29a and 29b are the AE display in aperture priority mode, where the aperture setting mark indicates the set aperture value of 5.6 and the auto second time of 1/250, and the aperture priority A and sand represent the AE mode. .

FIGS. 30a and 30b are AE displays in the Shabuta time priority mode. When the shutter speed setting mark is crossed out, the set shutter speed value is 1/250 and the auto aperture value is 5°6, and the shutter speed priority S and tsukuda indicate the AE mode.

FIGS. 31a and 31b are AE displays in manual mode.

The second and aperture setting marks indicate the shutter second and second value and the aperture setting is 1.4, and the manual mode M and mouth indicate the AE mode.The right end of the internal display indicates the metering mode. It is a photometry mark, and the left side is the error amount of the manual setting value with respect to the appropriate value, which is the so-called metered manual instruction value, -!-6.
This indicates that there is a difference in indication of 5EV. Further, the mark on the left end is a mark indicating a camera shake (hand shake) warning, and the two marks are lit alternately.

FIGS. 32a and 32b are displays during override setting. It represents the override direction and absolute amount 1.5EV.

FIGS. 33a and 33b are AB mode displays after override setting. Compared to FIG. 28, an override direction + has been added. The internal display also displays the absolute override amount of 1.5 EV. However, +1 and 5 are blinking on the internal display.

FIGS. 34a and 34b are displays during ISO setting.

The ISO mark and the 150 value 100 are displayed.

However, the ISO mark does not light up on the internal display.

FIGS. 37a and 37b show hand shake (camera shake) warning displays. On the internal display section 6, mark CA on the leftmost camera
I and CA2 light up alternately to indicate movement.

FIG. 37C shows the display on the external display section 4.

FIG. 35 is a display in standby mode.

Only the bar display was dimmed, and all other lights were off. Functions other than camera display are in a stopped state.

<Operation Description> - Overall Operation - The basic operation of the display circuit section 20 will be explained. When the DC voltage +E is supplied from the power supply 11, the momentary F generated by the power-on reset circuit 40 (right end in Figure 4)
The OR signal causes the flip-flop FFI of the frequency division stage (FIG. 4), the 7-lip flop FF2 of the clock generator of the segment driver section 24 (FIG. 6), and the flip-flop FF3 of the data latch circuit 23 to be activated. The latch Tl (FIG. 7) and the starting FET 27b (FIG. 24) of the voltage generator 27 are each set to their initial states. In latch LT1, each data terminal is set to j10=“Low”.

Set Ht=“High”. Flip 70 tube FFI.

In FF2, set the output state to Q = “Low” = “) (ig
Set the output state to Q="High" in FF3.
”.

Set to “Low”. In the voltage generating section 27, FET
27b is turned ON for a moment, the capacitor C2 is charged with electric charge, and the level of VLCDI becomes the GND level. In this state, since the crystal oscillator XL2 of the oscillator 41 (Fig. 4) has not started oscillating, there is no circuit operation at all, and the oscillation rise of XL2 ( Waiting for the oscillation rise of =φ. On the other hand, VDD, VLD2.
VLDO is given in an undefined state, but (COMl
is VLCD2゜C0M2 is VLCDO, 5EGn is S
VDD or V LCD depending on the state of 2n, 52n-1
2) 0FFVLCD input to the voltage generator 27 is jl
Due to the initial setting of O = 'Low' and jll = 'High', the 24th
By the switch circuit shown in the figure, V LCD2 = V LCD
0 = V DD, and the voltages applied to each terminal of the LCD display on the inner and outer mounting portions 4.6 are equal, and there is no DC voltage application state that is harmful to the liquid crystal.

Next, the crystal oscillator XL2 starts oscillating and φ. When a signal enters the flip-flop FFI in the frequency dividing stage, all parts start operating at the same time.

The clock φ enters the flip-flop FF3 of the data latch section 22 and functions to generate an LTCH pulse when serial data communication from the CPU10 starts.

The clock φ, enters the booster circuit of the voltage generator 27, and the clock C,
, CI is switched to boost the voltage.

Clock φ0. φ1° enters the common driver section 25 and segment driver section 24 and becomes a clock for the liquid crystal drive waveform.

Clock φ5. is input to the output control unit CTLI of the decoder unit 23 and used to control the blinking state of the display contents.

The operation after the rise of oscillation of the crystal oscillator XL2 will be explained first with respect to the voltage generating section 27. The clock φ input to the booster circuit 27a in FIG. 24 starts the boosting operation, and the initial VLCD
What was the ILCD display level (V DD-2V
LCD) level and stabilize it. From then on,
It continues to work without interruption until the power supply voltage drops and it stops operating, or the oscillation circuit stops, causing the lifting and lowering operation to stop. On the other hand, the data latch circuit 22, which has started operating in response to the clock φ, sets the terminal N O,jl 1 to 'L'.
ow@.

The moment a signal other than "High" is input and latched, OF
Wait for the output of LCDI, V LCD0 = V LCD. These are common drivers 25. The voltage is guided by the segment driver 24 and applied to the LCD display of the inner and outer display sections 4.6 as a voltage for driving the liquid crystal, and a liquid crystal display is performed based on the latched data.

Next, the data latch section 22 will be explained with reference to FIG. 26. This circuit starts operating when both the pwc and cs multiplied signals become "Low". 7We is, for example, a timing signal for supplying power to a photometry circuit of a camera (not shown), and P
The photometry circuit starts operating when WC="Lov". Further, C5 is a signal for determining the destination of serial data communication, and one signal is output from °cputO to other circuits in the camera (not shown). C5
="Low" selects the other party for serial data communication.

When either pwc or tusk is “High”, P・C
8 signal is "HIGH", the counter decoder CD is set, and all BSI-B57 outputs are "HIGH".
”. Also, the output φS of the OR gate ORI is “H”.
high@, and the output LTCH of the Nant gate NA8 is also "High". pwτ, ``Ka4 all・Lo
w-. hour counter decoder. . is moving
Along with becoming one work, or gate ORI,
OR gate OR2 opens and the SCK and BS7 signals become detectable. At the rising edge when the first pulse of SCK is input, BSI becomes "Low" and NOR gate NR3 opens.

Since the φ input of the shift register SRI rises at the fall of the first pulse, the contents of 5DATA at that time are taken in by the soft register 5Rth<t. The data at this time is jIO
It is. Then a second pulse comes and the same operation is repeated. At the falling edge of the 8th pulse, 8 pieces of data have been taken into the soft register SRI, and the 8th data is 07
It is called. Until this time, signal BSI is "L ov".

When the next ninth pulse rises, BSI becomes "High", B S2 becomes "Low", NOR gate NR3 closes, and NOR gate NR4 opens. Since the φ input of shift register SR2 rises at the fall of the 9th pulse, the 5DA at that time
Only one shift register SR2 takes in the contents of TA. The data at this time is j20. From then on, the process continues in the same way, and at the rise of the 49th pulse, BS6 becomes "High".
BS7 becomes “Low”, Noah gate NR8 closes,
Noah Gate NR9 opens. Further, the output of the OR gate OR2 becomes "Low". The contents of shift register SR7 are taken in from 370 to core 7 data up to the 56th pulse, but from the first pulse until the 56th pulse, LTC
The H output remains H4gh” and each shift register S
Data is not fetched from R to latch LT.

The output of the OR gate OR2 becomes "Low" due to the OR gate OR2 opening at the 49th pulse, but due to the rising edge ζ5 of the clock φ, the flip-flop FF3 takes in the "Low" of the D input, and the output becomes "High". However, the output changes faster than the Nando game)
Since the other human power of NA8 is set to "Low", the LTCH output remains "HIgh@".

Here, the output of the OR gate OR2 becomes "High" depending on whether the 57th pulse comes or whether either pwc or cs becomes "High".At this moment, the output of the flip-flop FF3, which is the other input of the Nant gate NA8, becomes "High". Since the silkworm output is also “High”, the output LTCH of NA8 becomes “L ov”. This “High” → “
The falling edge of "Low" signals the latch, and the data temporarily stored in the shift register 5RI-9R7 is latched into the data memory of the latch LTI-LT7.Then, with the rising edge of the clock φ, the data temporarily stored in the shift register 5RI-9R7 is latched into the data memory of the latch LTI-LT7.
takes in the “High”” of the D input, and the σ output takes “Lo”
w”, and the counter decoder CD is pwc, c
s is set to "High", and each returns to its initial state.

The above is an overview of the operation of the data latch. Here, if the number of clock bytes for Norial data communication is insufficient, the last latch pulse LTCH will not be output, so no data abnormality will occur, and even if the number of clock bytes exceeds 5.
It is automatically turned off at the 7th pulse and naturally no abnormality occurs.

Furthermore, since the clock within the same byte is processed so as not to be interrupted on the sending CPU side, abnormalities in data communication are completely prevented.

On the other hand, even if the external 1 [No. 4 PWC, O8, SCK, and 5DATA] operate normally, if the internal φ is not operating, the L
TCH pulse is no longer output and shift register 5RI-5
The data taken into R7 cannot be latched into latches LTI to LT7. This means that if it is considered that the liquid crystal drive waveform does not operate when φ is not operating, a DC voltage will be applied to the liquid crystal. Therefore, at that time, jl O = "Low", N I = "High"
' and set 0FFVLCD="High" so that no voltage is applied to the liquid crystal. For this reason, external data is not taken in when the clock φ is not operating.

Next, the common driver section 25 and the segment driver section 2
I will explain about 4.

In Figures 5, 6, and 927, Nando Game)N
AI, NA2. Analog switch ASI-AS4゜Pch FET FPI, F by a gate circuit consisting of NOR gates NR1, NR2 and inverters INS, IN4.
Controls each switch of P2. The input signals of the gate circuit are φ, φ1°), and due to this timing, C0M2. The outputs of COMI change as shown in FIG. 27. Signals C0M2 and CO
MI is the same as the period of clock φ1°, and they are 1
It has a shift of /4 period.

The output values are vDD and V LCD0 and V LCD21.
7) It has three levels.

In FIG. 6, four types of clocks generated by the clock φ processed by the clock generator composed of the inverter INS and the flip-flop FF2 and the clock φ1° are selected by the clock selector composed of the Nant gates NA3 to NA7. . The selection conditions are S2n,
52n-1, and by this condition, S
The output waveform of E G n is determined.

This state is shown in FIG. 27, and each state is different depending on four types of states determined by S2n and S2n~1.

The period is clock φ,. , and there is a shift of 1/4 period from each other. The output values are VDD and V
It has two LCD levels. signal COMI,
The potential difference between 2 and segment signal 5EGn is 2XVLC.
The LCD display lights up depending on the waveform of the portion that becomes D2.

For COMIj, 5EGn (LH), 5EGn (
The segment of the LCD display to which the voltage of HH) is applied lights up, and 5EGn (HL), 5
The segment of the LCD display to which the voltage of EGn (HH) is applied lights up. 5EGn (LL) is C0
M1. The segment will no longer light up for C0M2 as well.

In other words, the 52n-1 signal is a signal that controls lighting of the segment for COMI, and is OFF when 52n-1="Low" and ON when 52n-1="Might". The S2n signal is a signal that controls the lighting of the segment for C0M2, and is OFF when 52n = “Low”.
, 52n = “High”, it is turned ON.

Data latched in Figure 7 jlO~N 7°j20~
j27, j30~ j37. j40～ko4
7゜j50-j57. j60-j67,. 70~j77
is jl7. j30. All bits except 3 bits of j31 are input to the decoder section shown in FIG. SWI.

SW2. DCI-DC4, 5DI-SO2 are simply gate circuits and have no timing relationship at all.

The explanation is below.

First, the contents of the serial data will be explained. .

HO and H1 are signals that control the supply of liquid crystal driving voltage, and only when N O = "Low" and jl 1 = "High", the liquid crystal driving voltage is stopped and the voltage applied to the liquid crystal becomes 0.

j12 to j16 are data signals (
(see Figures 9, 14, 15, and 20),
There are 23 types. Also, j12 to j16 are all “High”
Nothing is displayed when .

320 is a signal (see FIG. 22) regarding a warning of insufficient battery voltage in the camera, and all displays displayed at j20-High' repeat blinking at a cycle determined by φ14.

j21 is a hand shake (camera shake) warning signal (see FIG. 23), which becomes "High" when the shutter speed becomes slower than near the limit that causes hand shake (camera shake).

At this time, camera shake marks CAI and CA2 on the internal display section 6 in the finder are lit alternately.

j22 to j27 are data signals (
(see Figures 9, 13, 17, and 18),
There are 36 types. Also, j22 to co27 are all “High”
”, nothing is displayed.

j32 to j37 are data signals regarding the ISO value of film sensitivity (Fig. 9, Fig. 13, Fig. 1γ).

(see Figure 18), and there are 31 types. Also, j32~j
When all 37 are 'High', nothing is displayed.

340 to j47 are data signals (
(see Figures 9, 13, 17, and 18),
10,000 types from 0 to 99.

Further, when all of j40 to j47 are 'High'', nothing is displayed.

j50 to j53 are data signals regarding the override value and the metered manual deviation amount (see Figures 11, 12, and 19.20), and there are 9 types of override values depending on the content to be displayed.
1 and the metered manual deviation value 14[] are switched and sent from the CPU. j50-j53
When all are "High", nothing is displayed. For switching the display contents, the receiver has the j55.356 signal (described later).

j54 to j56 are 5IGN signals (see Figures 21, 22, and 23) related to the override value, the sign of the metered manual deviation amount, and the signal switching, and j54 is "+" and the signal related to the sign of “-”, j
55 and 356 are signals for switching data between the override value and the metered manual deviation amount for each external display and internal display.

j57 is a signal used to display the so-called preview moment (see Figures 22 and 23), which is used to check the depth of field by narrowing down the lens aperture before shooting. At times, this signal becomes "High", causing the aperture mark F on the external display section 4 to blink and the setting number-chain band indication mark TAI.

Controls the lighting of the bar at TA2.

j60 is an ISO display priority signal l5OPRI. This means that the main switch SM is OFF, and OFF
Even if the LCD signal is "High" and the liquid crystal drive voltage is stopped, when this signal becomes "Htgh", the liquid crystal drive voltage is increased by the segment driver 24. The 0FFV LCD signal is set to “L” so that it is supplied to the common driver 25.
ow" (see Figure 21). This signal is not used alone; data on the tSO display mode and ISO value are sent from the CPU 10 at the same time as this signal. In terms of camera operation, this means that the battery is installed. This is the state immediately after.

j61i! Metered? This is a blinking signal of the deviation amount of 2s full M'dMOVER (see Figure 22), and this signal is “H”.
The deviation value of the metered manual flashes at “high”.

j62 is the shift signal 5HIF for blinking the program mode mark during the shift of the camera's program mode.
T (see FIG. 22), and when j62 is "High", this mark blinks. Here, the shift refers to a state in which the combination of the aperture value and the Nyatta seconds value in the program mode is changed and operated. Incidentally, all AE modes can be blinked as needed, regardless of the program mode.

j63 is the control interlocked warning signal Not, C0NT (22nd
(see figure), and this signal goes “High” when an exposure value that exceeds the aperture value and second value that the camera can control is required.
h'', and the aperture value and/or second value flashes on the side of the subtraction control value depending on the AE mode to issue a warning.

j64 is a brightness-linked warning signal BV (see Figure 22), and this signal becomes "High" when the brightness value exceeds the brightness value that the camera can measure, and the ASI and AS2 during the metering mode display. flashes to warn you.

j65 is the bulb time signal BULB (see Figure 21), which is a signal for switching the display contents of 4 digits and 7 segments during bulb exposure from the shutter seconds display (buLb) to the bulb exposure seconds count display. Press @ to display the valve count, and display the contents of j40 to j47.

j66 is an all-off signal ALLOFF (see Figure 21), which controls the waveform of the driving SEG terminal so that it becomes an OFF waveform (see Figure 27, 5EGn (LL)). The OFF display will appear. However, camera marks CAI and CA2 cannot be controlled.

j67 is the all lighting signal ALL, ON (see Figure 21), and the waveform of the driving SEG terminal is all ON waveform (second
7 (see Fig. 5EGn (HH)), and when the signal is ``High'', all the signals are displayed as ON.

However, the camera mark CA1. CA2 cannot be controlled.

j7o and j7t are camera operation mode signals CALL
MODE (see Figures 19, 20, and 21), normal AE mode, main switch SM/) 4O
5TANDBY mode where the camera is not working even in N,
There are four states: summer SO mode for ISO setting and display, and +/- mode for +/general setting and display, and the display contents are switched according to each mode. (See Figures 28 to 35)j72. j7
3 is the camera's AE mode signal AEMODE (see Figures 22 and 23), which has four states: program mode, aperture priority mode, shutter speed priority mode, and manual setting mode. Switch the displayed content.

j74 is the ISO output when prompting to set the ISO value
This is a warning signal ISOARM (see FIG. 22), and when this signal becomes "High", the ISO mark and ISO value in the interior and exterior display sections 4 and 6 flash.

j75 [Mode off signal MODE OFF (see Figure 23). When this signal becomes °H1gh", the AE mode display that is being displayed goes out. The mode display is turned off when the film is not fed when loading film into the camera.
Make it.

j76 and j77 are photometry mode switching signals AVE/5POT
(See Figure 23), and when the partial metering mode is selected between the average metering mode and the partial metering mode (either j76 or 177 or ! becomes L ov@), the viewfinder's internal display Turn on AS2 in section 6. It is always lit during ASI and AE mode.

The DC4 also uses external signals SM and vWτ as data, and is connected to the data code converter (Fig. 23) and the L of the display unit 4.6 regarding the display of shutter speed, aperture value, etc. outside of the numerical band.
A decoding section (Fig. 22) for controlling blinking of each display segment of the CD display, and two signal switching sections SWI, S.
It is divided into three parts: a decoding section (FIG. 21) related to W2.

Figure 21 is created mainly with SW1 and SW2 switching signals, and FOM, CTR, ISO, and SS signals are SWI
, MO, N, +/-ON signals control SW2. In addition, the ON and OFF signals are commands to control the CTLI and display an ON display and an OFF display for all segments. Furthermore, the 0FFVLCD signal is "
When it is High', it functions to cut off the liquid crystal drive power supply and the liquid crystal drive circuit. The purpose of this is to prevent DC voltage from being applied to the liquid crystal when the XL2's primary oscillation is stopped, and to reduce power consumption when the main switch SM of the camera is turned off. On the other hand, the CALL MODE signal 370. j71 represents four camera operation modes;
h" is the AE mode mode for normal shooting.j70-
When j71 = "High", it is called 180 mode for G*I SO sensitivity setting. j70・j71=")(igh
” is called the 5TANDBY mode, which is the camera standby state. When j70/j7 plate = “High”, it is called the +/- mode for setting the override amount.

To explain the signals for SWI and SW2 according to the above four modes (see Figure 21), during AE mode, p
wc becomes °Low (the camera starts operating).
Then, the FON signal becomes “High” and SWI works,
Aperture value information j12 to H6 is selected and decoded and displayed. When FWv becomes "High" (the camera enters a standby state), the FON signal becomes "Low" and the aperture value information is erased by SWl.

On the other hand, when pwc is -Low' and j65 is Low' (
During normal operation), the SS signal becomes High', and the shutter speed information j22 to j27 are selected and decoded and displayed. At this time, other CTR signals and ISO signals are “Low”
'ts available, timer count information and ISO value information are S
Deleted by WI.

PW(IJ('Lov"l'565#"Higb"+
In this case (during “shibu count”), the CTR signal becomes High.
timer count information j40 to j47 are selected and decoded and displayed. At this time, other SS signals, I
The SO signal is “Low” and the shutter time information and I
SO value information is erased by SWI. .

Also, the +/-ON signal is "L ov", but the MON signal is pwc is "LO OV" and 350 or j56 data is 'H'.
Since it is "High", the value information of the metered manual deviation amount is selected and decoded and displayed by SW2, but the override value information is erased.

SS, CTR, FON, MON in ISOS mode.

+/-ON signal is all ``Lov' te, xso signal''
````igh,'', !=''°゛°''゛419+6°, l5
OI''1 information j32 to j37 are selected and decoded and displayed. At this time, other numerical bands are erased.

5 During TANDBY mode, SS, CTR, FON, l
509M0N, +/-ON signals are all “Low”,
All numerical bands are erased.

During +/- mode, SS, ISO, CTR, FON, M
All ON signals become ``Low'', and when PWC is ``Lot'', the +/-ON signal becomes ``High-''.

At this time, override information j50 to j53 are selected and decoded and displayed.

Figure 22 shows a control signal for the blinking display of each display segment. When the output B1-88 becomes "High", if the corresponding segment (see Table 1) is lit, that segment is Flashing.

The B8 signal is a signal that causes the F mark on the external display section 4 to blink, and is mainly controlled by 357 data.

The B7 signal is the 7th segment of the CD on the internal display section 6.
This is a signal that flashes the numbers 8 and 8, and the col and 2 second digits between them, mainly j55. j56. It is controlled by the data of j6t.

The B6 signal is a signal that blinks ASI and AS2 on the internal display section 6, and is mainly controlled by j64 data.

The B5 signal is a signal that causes numbers 5 and 6 of the 7 segments, col, and l to blink on both the external and internal display sections 4 and 6, and is mainly controlled by the j63 data.

The B4 signal is a signal that causes 7 segments 1 to 4 to blink on both the external and internal display sections 4.6, and is mainly used for j63. It is controlled by the data of j74.

The B3 signal is a signal that causes both the external and internal display sections 4.6 to flash, and is mainly controlled by 362 data.

The B2 signal is a signal that causes the ISO mark on the external display section 4 to blink and is mainly controlled by 374 data.

The Bl signal is a signal that causes all segments other than the segments 88 to B2 to blink except for CAL and CA2, and there is no particular data signal. However, including B1, blinking control is performed by j20 data from 82 to B8.

FIG. 23 shows a decoder for the seven segments for displaying numbers in the inner/outer representation part 4.6 except for 1 to 8 and col, l, col, and 2. Serial data j54 to j57. j70~jrs, j75~j77
, j21. and external signal pwτ, and further decode DC2
The output is controlled by each of the 440 output signals, and the outputs are from r51 to r69, and each output is “High.”
”, the corresponding segments will light up.

FIG. 9 shows SWI, which selects signals.

The input signal is 02~[6 aperture value, j22~j2
Shutter time value of 7, tSO value of j32 to j37, j4
These are timer count values from 0 to j47, and there are FON signal, CTR signal, ISO signal, and SS signal to select each. When each selection signal is "High", the NAND gate opens and output data p = input data j, while "L"
ow”, the NAND gate closes and the output data p="
High”.

(Example) When FON=“High” Outputs p12 to p16 transmit inputs 02 to H6 as they are.

When FON=“Low”, all outputs p12 to p16 become “High”.

Next, the force <DCt, which is not shown in detail, will be explained.

DCI is serial data j2 processed by SWl
2-j27. j32-j37. j40~j47
p22-p27, p32-p37, p corresponding to
A data converter (
decoder). Figure 17.

Figure 18 is for explaining the concept of DCI,
The input data is AL and old GH, p32 to p371 = corresponding IsOSS value types (ISO6 to 15O6400) and ALLHigh,
There are 100 types of timer count values (CTR values) (00 to 99'') corresponding to p40 to p47 and ALL High.
I For example, rb of SS value
Data p27 to p22 corresponding to uLbJ = “LLLL
When LL″″ is input (other data G at that time) 32~
p37, p40 to p47 are processed with DC4 and SWI so that they become ALLHigh. ) Output data is q7 data “b#” for segment decoder SDI.
, q18 data is "Lo" for Sn2, Q29 data is "U" for Sn3, and q39 data is "b" for Sn4.

Also, data p37 to p corresponding to the ISO value r200J
When 32=1LHHHLL'' is input, other data p22 to p27.p40 to p47 at that time are set to ALLHigh.
Processed with DC4 and SWI to make it look like this. ) The output data is ql data for segment decoder SDI, q8 data for Sn2, and q2 data for Sn3.
1 data, and data for Sn4 is not output.

Also, p22-p27, p32-p37, p40
When p47 are all 'High', no output is output to the segment decoders SDI to SD4.

All segments for 5DI-8D4 are turned off.

It is composed of a gate circuit having the above configuration.

Next, segment decoders SDI to SD4 shown in FIG.
I will explain about it. The data signals qt to Q39 obtained in the previous section are respectively ql-q7 to SDI and q8 to q18 to Sn.
2, q19 to q29 to Sn3, q30 to q39 to S
Enter in n4. The inside of the 5DI-8D4 is basically the same, but among the 14 inputs, terminals to which no corresponding data signals are input are pulled up to the power supply side in each block. The circuit is configured such that when the input becomes "Low", a valid output is obtained. For example, S.D.
When the q7 data signal (b of buLb) is output to I,
The tgo input becomes “Lo”. At this time, the other SDI inputs q1 to q6 and the input being bulldozed are High.
”, but the outputs (c), (d), (e), (D, and (g)) related to the line that became “Low” all become “High” and the other (a), (b) , (h) line is.

This output is (c), (d), (e)
, (f), (g) are r3 to r in terms of SDI terminals.
7, which is input to the next stage CTLI and connected to the liquid crystal display. This r output corresponds approximately 1:1 to the liquid crystal segment (see Fig. 16a, Figs. 2 and 2c, and Table 2). The output here (c), (d),
(e), (f).

(g) corresponds to the numerical segment name of each of the seven segments, and represents the character "6" (see Figure 2).

Furthermore, for example, q21 data signal (r2
When J) appears, 10,000 manpower becomes “Low” (a).

(b), (d), (e), (g) are 'High'
Then the character "2" will be displayed.

P12 to p16 obtained by SWI enter the decoder DC2 shown in FIG. 14. p16~I)12='LLLLLL'
The output at the time is q40, and an output of "L ov" is output. The output of q4G goes out to segment decoder SD5, while it goes out to decoder DC4E.

Other outputs are exclusively connected to SC2.

The contents of the output of 4407q62 based on the data of p12 to p16 include 2311 kinds of aperture values shown in the concept of SC2 shown in FIGS. 19 and 20. These are SC2 shown in Figure 15.
A segment decoder is performed on a part of (the input part of q40 to Q62), and outputs of r30 to r43 are obtained.

For data j50 to j53, decoder D of the first star map
There is C3. j60 data is data below the decimal number,
A p1 output and a p2 output are obtained.

The j51-j53 data represents information from 0 to 6, the outputs are p3 to p9, and the output becomes active at "Htgh". This output is input to the switch SW2 in FIG. 12, and the output destination is switched by the selection information MON, +/-ON. When MON is °I (high), +/-ON is L
ow", and the outputs of p2 to p9 are inverted and q82
~q89, but all q71 A-478 become "High". -Sumo wrestler/-When ON is "High", MON is "Los" and the outputs of pi to p7 are inverted and output to Q71 to q77, but q82 to q
89 is all “High@”. Also, 478 is “L”
OW”. MON.

When both +/-ON are low, Q71 to Q7B,
) All outputs of q82 to Q89 become "H1gh".

The output of SW2 is q71 to q78 to SC2, q82 to Q
89 is output to SO2.

q71-q78. output by SW2. The contents of q82 to Q89 are shown in Figures 19 and 20. q71 to q78 contain seven types of numerical values and one type of decimal point for override values, and q82 to Q89.
Q89 has an integer digit value of 7N for the metered manual value (including override value) and a display of 1 below the small pattern.
Each corresponds to the species.

Although the contents of SO2 are not shown, the basic idea is the same as that of 5DI-8D4 shown in FIG. 13, and shown in FIG.

A typical gate configuration is used to establish a relationship between the data shown in FIG. 20 and the output display example.

Finally, r made by 5DI-9D6 and DC4
l~r69 and Bl~B8. When ON, OFF signals and the clock of φI4 are input, the output control section C
TLI will be explained.

The internal configuration of CTLI is already shown in FIG.

r69→S69. Except for the configuration of the portion 570, the configuration is basically as shown in FIG. 16a. First, in FIG. 16, when a "High" signal is input to r69, the gates for S69 and 870 are opened and the clock of φ, 4 is used.
“High” and “Low” are repeated, but S69 and 87
0 is output in reverse phase. In this way, the corresponding CAI, C
The A2 mark lights up alternately, giving the impression that the camera mark is blurring. For circuits for signals other than r69, logical expressions and truth tables showing the relationship between the output S and the input are shown in Table 1. As this table shows, the Then the output S is S69
．． All except 370 are "High" and the display content is CA1. All lights except CA2.

Next, when the ON signal is "High-", the OFF signal is "
When H1jlh' is reached, the output S becomes S69. All except S70 become "Low", and CA1. All displays except CA2 go out.

5, when the signal is "High" and the OFF signal is "Low", when Bm (B1' to B8)h"Lov-, the output S = r, and the display content is in accordance with the display information given by serial data. Lights up to display.

"The signal is "High", the OFF signal is °Low", B
When any part of @(Bl-88) becomes “High” by DC4, it corresponds to r in the same group according to the combination of day and r under the truth table in Table 1. The output S blinks according to the display contents at that time in accordance with the clock of φ,4.

For example, the B6 signal is °H1gh” and the other 81 to B
5. B7. When the B8 signal is “Low”, the corresponding outputs S59 and 96 of r59 and r60 in the B6 signal group
0 repeats 'High@' and 'Low'.

However, when the states of r59 and r6G are "Low", S59 and S6G cannot become "High". Therefore, As2 and A corresponding to S59 and S60
If the SI is lit, it will change to flashing.

Outputs 81 to 870 obtained by the above CTLI are input to each segment driver (Fig. 6), and output as a liquid crystal drive waveform (see Fig. 27) to the final output SEG terminal (SEGI to 5EC35). .

The relationship between the CTLI output S and the SEG terminal is shown in Table 2.

The names of the segments shown in this table are the same as the names of all the segment diagrams shown in FIG. 2C.

1. When starting the camera: When the camera is started by turning on the main switch SM, an interrupt is generated in the CPUIG, the CPU 10 is released from the stopped state, and the camera starts operating according to the program in the internal ROM. At the same time, voltage is supplied to a photometric circuit (not shown), but it takes several + IHIC to operate reliably and provide necessary data to the CPU 10.
time is required.

However, the CPU, which operates at high speed, is communicating serial data with the display circuit section one or more times at this point. The contents of serial data communication (see Figure 36) mainly include exposure information such as shutter speed and aperture value, but if the photometry circuit etc.
) Accurate values of these exposure information cannot be obtained when the device is not in constant operation. Therefore, it is not good to carry out serial data communication in this state because it not only has no meaning but also causes erroneous display. Therefore, at startup, the CPU
Until G takes in accurate information and completes the calculation, it is possible to avoid displaying a troublesome inaccurate value on the display by sending data to turn off the light or data for standby display. . The display section of the embodiment has a structure in which the previous display is maintained unless new serial data communication occurs. There is no particular problem as long as you do not use this to communicate serial data until the calculation is completed, but the CPU
The program is designed to create a program flow that avoids exceptions as much as possible, so it is better to communicate serial data at regular intervals to reduce the RO for the program.
This is good in the sense that it does not increase the capacity of M. Therefore, the above method becomes better.

Immediately after the battery is installed in the camera, +E voltage is applied to the CPU 10 and the display circuit section 20, and each starts operating. Each circuit has a separate crystal oscillator XL1. XL2
, and starts operating independently, but in this case, XLI
Generally speaking, XL has a higher frequency than XL2.
I starts oscillating early. After the oscillation starts, the CPU10 starts operating according to the program in the internal ROM, but since there is little work to be done immediately after the battery is installed, it stops functioning after several tens of m5ec and waits for it to be woken up again. . Generally, at this point, the XL of the display circuit section 20 is
2 oscillation rise (generally °100Isec - 1sec
degree) is not guaranteed. When XL2 of the display section is not oscillating, serial data communication with the CPU is not received, and the clock φ shown in Fig. 7 is not generated, so the operation is as shown in the time chart shown in Fig. 26. LTCH pulse will not be generated unless Also, even if XL2 is oscillating, as long as there is no serial data communication, the display circuit section 2
Do not rewrite data within 0. (pw in Figure 7
Since ε, 5DATA, and SCK do not come, BS7 does not occur and LTCH pulse does not occur. ), the operation of the CPU 10 as described above is not good because the display content continues to be displayed indefinitely, indicating the battery installation status. Therefore, j in Fig. 7 of this circuit
One countermeasure is to prevent the initial indefinite display by turning off the power for driving the LCD using a power-on reset circuit as shown in FIGS. 10 and 24 and 25. Furthermore, if the power-on reset circuit does not work for some reason, or if it is not good for the light to remain off for a long time, serial data communication from CPU10 will continue until the guaranteed start-up time of XL2 after battery installation. As a result, as soon as the oscillation of XL2 starts, normal operation starts and the display contents change immediately. The contents of the serial data at this time may be data for turning off the light, data for standby display, or any other arbitrary data.

Therefore, the CPU operates by performing serial data communication using display data from the time it performs necessary processing immediately after the battery is installed until the guaranteed start-up time of the XL2 oscillation, and after a predetermined period of time, if necessary. All you have to do is go into a stopped state and stop functioning. However, the CPU 10 must prohibit interrupt operations during the guaranteed rise time of XL2.

- Before cput o stops - Immediately before CPUIO stops its operation, CPU10 sends standby mode display data to the display. After that, until CPU10 is activated again, there is no data transfer, so the display remains unchanged and the standby mode display continues. Immediately before the main switch SM is turned off and the CPU10 stops operating, the CPU10 sends display data for the lights-out mode to the display in the same manner as described above. After that, there is no data transfer until the main switch SM is turned on again, so the display remains unchanged and remains off.

-ALLON and ALLOFF- Serial data HO, jl 1 is the highest priority data that completely turns off the LCD power supply.

""・The light goes off when jll = "High".

On the other hand, the data of j66 and j67 should be checked
This data is prepared for the first time and is second priority data. When j67="High@", all segments light up, j66="Low""
At this time, waveforms in which all segments are turned off are output from the COM and SEG terminals, respectively. When each waveform is connected normally or applied to the CD, it will be displayed whether all the lights are on or all the lights are off. However, if the connection with the LCD is misaligned, a part of the LCD may turn off or turn on, or the brightness may be different from other segments, making it obvious that the connection is abnormal. .

Also, as a method of providing signals for serial data communication, 5DA
By connecting the TA line to 1E through a small resistor, that is, pulling it up, all serial data will be “
"High" information, and the priority bit j67 comes alive and becomes the full lighting mode.On the other hand, when it is connected to GND, that is, pulled down, all serial data is "
"Low" information, the priority bit j66 becomes active, and the all-lights-off mode is activated.This is a very easy check that can be done even after the camera is assembled.

Furthermore, there is no need to provide a dedicated terminal, which is ideal.

- Off mode and standby mode - Fig. 35 shows the display on the external display section 4 in standby mode. Only the bar is lit and all other external and internal displays are turned off. As the camera body, the CPU
l0 is in a stopped state and is waiting for an input corresponding to an interrupt instruction. Further, although power is supplied to the display circuit 20, no power is supplied to any other circuits (not shown) other than the CPU10. However, when an interrupt input such as a photometry switch is input to the CPU10, power is supplied, other circuits start working, and the camera function starts.

On the other hand, the display in the lights-out mode turns off all displays.

The method is to turn off the LCD drive power by 0FFV LC.
Set D to “High”. The operation of the camera body at this time is only in a stopped state where the CPU is waiting for an input interrupt from the 8M terminal, and no power is supplied to any other circuits except for the display circuit (not shown).

The main feature of the camera in standby mode and off mode is that only the main switch SM is active in off mode. On the other hand, in the standby mode, other operation start switches such as a photometry switch (not shown) come into play. Further, the current consumption is lower in the off mode, which is energy saving, and the voltage applied to the liquid crystal is zero in the off mode, so the liquid crystal has a good shelf life.

- Manually configurable data indication marks - Figure 29 a, b
In the A mode, since the aperture can be set, the black mark TA2 on the aperture chain side is lit, and the black mark TAI on the shutter speed side, which cannot be set, is turned off.

Similarly, in the S mode, that is, the shutter priority mode shown in Figures 30a and 30b, since the shutter speed can be set, one mark TAI on the shutter speed side is lit, and the mark TAI on the aperture chain side, which cannot be set, is lit. Mark TA2 goes out.

In FIGS. 31a and 31b, in manual (M) mode, since both numerical values can be set, both black marks TA1. TA2
lights up to indicate that both can be set.

In the P mode shown in FIG. 28, since there are no numerical values that can be set, both marks are turned off to clearly indicate their meaning.

The lighting and extinguishing of these marks is controlled using the AE mode information according to j72.373 as is.

However, if the function for determining the presence or absence of a lens (not shown) determines that there is no re-lens, the aperture of the lens cannot be set. Therefore, in this case, the setting mark TA2 regarding the aperture is set to birch, which does not light up regardless of the mode. This is controlled by the q40 signal shown in FIG.

1-Open F value display - The aperture value display is a 7-segment numerical display as shown in FIGS. 28 to 31. The contents of the aperture value are shown in FIG. Here, the rq40J signal indicates a state equivalent to no lens when -1 is displayed, and rq43J to rq62J are 0.5E.
This is the aperture value rounded to each V. On the other hand, the lens' maximum aperture F value has been
) There are numerical values such as 3, 5, and 4.5 that are rare. However, these values are not multiplied by the aperture value for each 0.5 EV, so these values are treated as special, and rq
Prepared as 41J and rq42J signals. In this way, the result of the calculation performed by the CPUIG or the set aperture value is the aperture value (determination is made by an unillustrated aperture signal), and the 3.5 or 4.
When it is 5 etc., change the CP to display 3.5 or 4.5 instead of the normal display of 3.4 or 4.8 etc.
Gives display signal from UIO. Further, when the result of the calculation performed by the CPUIG or the set aperture value is not the aperture value, the normal display such as 3.4 or 4°8 is used for display.

The above two series of display formats are provided.

As an example, FIGS. 33a and 33b show display examples of the open F value.

The open F value is determined, for example, as follows.

As shown in FIG. 40, in step Sl, the control CPU l0
reads the open FlIAvo from the lens 3 and stores it in the internal register. On the other hand, CPU10 uses the calculation F @ A v calculated in step S2 based on the camera settings and the value obtained from the photometry result, and calculates Av in step S3.
Determine o=Av, and if Avo=AV, open Fll1
Step S4) to extract A vo, step S5) to extract the calculated F value Av by rounding it to every 0.5EV if Avo≠Ay, data of j12 to j16 (AvDS
P) is determined and the extracted output is displayed on display units 4 and 6 (Stella fs6).

-Combined display of override amount and metered manual amount- The +6.5 in Figure 31 is the deviation amount of the metered manual, and is always lit during the manual mode, which is the only internal display of the infinder. The displayed range is +6.5
~-6.5EV (see Figure 20), and when that amount is exceeded, +6.5 and -6.5 are displayed blinking. M'dMOVER of 1ij61 data as data when blinking
is set to ``High''.

Also, +1.5 in Figure 33 is the override amount,
It always appears depending on the setting when in AE mode other than manual mode. Similarly, only the internal display of the infinder is displayed.

The displayed range is +4.0 to -4.0 EV (see Figure 20), and settings cannot be made beyond that amount. Here, the override display is constantly flashing to distinguish it from the metered manual, and at the same time draws attention to the override setting.

On the external display, +/- symbols (OR+,
OR-, 0R8) lights up, but in metered manual mode the +/- symbol (OR+, OR+) lights up.

0R8) is turned off and not displayed.

The data for each quantity of override and metered manual is received and received using the same register.
A separate identification signal is required.

This signal is provided by the 5IGN signal of j54 to j5B data.

Table 3 shows the relationship between the data contents of j54 to j56 and their output display states. This makes the portions j54 to j56 of FIGS. 21 to 23 easier to understand.

-6 and A mode display- The display mode is shown in FIGS. 29 and 30.

FIG. 29 shows the display in the A mode, and the A mode display section with an arrow pointing toward the display of the manually settable aperture value is lit. Figure 30 shows the display in S mode,
The S mode display section with an arrow pointing toward the manually settable shutter speed value display lights up. By doing this, the meaning of the mode display and the meaning of the numerical display can be understood at a glance, making the mode display extremely easy to use.

Figures 38a and 38b show the display contents at the time of initial loading after mounting the film. During film blank feeding, which is the initial loading period, the shutter speed is 1/4000 seconds and the aperture value is controlled at the minimum value (F22 in this case). At that time, all exposure mode displays have disappeared, but this is due to j75 bit 2 "1""",-Lr%-F*'""'
t, rcsz・1 Figures 39a and 39b show the display contents when the lens is not attached. When the CPU 10 detects that there is no lens by a mechanism not shown, all display j12 to j16 are set to "Low". This is step S1 of the flowchart in Figure 41.
8, and the display decoder that receives this is 4 in Figure 20.
40 signal and set F62 in FIG. 23 to "Lo".

Therefore, the display shows the aperture value - 1,
The aperture chain side mark TA2 of the settable marks disappears. FIG. 42 shows another embodiment in which camera shake on the internal display section 6 is displayed. In this case, as shown in (a) in the figure, it is composed of three segments, and the type of camera is indicated by lighting two of these segments. These two segments can be selected from two types (b) and (C), and camera shake is displayed by lighting these two types alternately.

FIG. 41 shows an outline of the operation of the control CPU10.

When the battery is installed, the CPU I O starts operating from a reset start (step SO). At the same time, voltage is also applied to the display circuit. First, in the cpu, to.

Perform initial settings for both cameras (step 510)
Then, display data, turn-off data, standby data, ISO data, etc. are sent out once for the display circuit (step 5ll). (n is a value determined depending on the time it takes for the display circuit to guarantee normal operation) When the transmission is completed, interrupts from a switch group (not shown) are permitted (step 512).
. If there is nothing, the internal operation clock is stopped and the system enters a stopped state (step 513). Among the switch groups (not shown), the photometric switch 81 or the initial load switch SB has a relationship with the main switch SM as shown in FIG. 44, and the other switch groups have the same configuration as Sl and SB. When the main switch SM is OFF, the Sl and SR large inputs are pulled down and St.

SB large input is dead. In this state, it is the SM fault signal that generates the INTset signal that generates the interrupt. When the main switch SMh (ON) generates an IN T set signal, an INT flip-flop (not shown) is set, and the CPUIG performs an interrupt operation INT (step 5).
14) Enter. This INT flip 70 knob is set at the rising edge, enabling interrupts (step 5).
I2), the INT flip 70 block is reset and waits for another interrupt.

Now, when entering INT (step 514), check the switch SB that detects the initial load state (step 515), and if it is 0FF (not an initial charge), supply power to a photometering circuit (not shown), etc. Start photometry with SI6. After that, in step S17, the AE
The calculation is performed, display data necessary for the display circuit is prepared, and sent out in step St8. Thereafter, the main switch SM is checked in step S19, and if it is OFF, data for turning off the light is sent out as display DATA in step S20, power supply is stopped, and photometry is stopped in step S21. After that, step SI2. Proceed to S13. If the main switch SM is ONL in step S19, the switch Sl is checked (step 326). S21. S12. Proceed to S13. Further, if it is ONt in step S26, the release switch 82 is checked in step S22. If it is ON, exposure control (step 523) is performed, and step S
Proceed to step S17, but if it is OFF, do nothing and step S17
Proceed to and perform the AE calculation again.

On the other hand, if the switch SB for detecting the initial load portion is ON in step S15, the second value, aperture value, and MODE OFF information information 5 data = "High" for initial load are sent out in step S24. Initial loading is performed to control the shutter mechanism using the second value and aperture value (step 525).Then, the switch SB is checked again in step SI5, and the photometry is performed in step SI6 depending on the state of the switch SH. Enter the start.

To move from step S13 to step S514, as shown in FIG. 44, depending on the SM, St, and SR switches, SM is
When F, St, SB switch is 5°°°1″″1.7
．． 4qf(Kmlo"ff/,?,
I'm here. Therefore, INT is applied only to ON of SM.
A Set signal is generated and an interrupt (INT) operation begins.

Further, when SM is ON, the St and SB switches are activated, and an INTset signal is generated by Sl or SB to enter an interrupt (INT) operation.

Although not shown, the SB switch is turned on when it detects the presence of film and that the back lid is closed, and turned off when a film counter (not shown) reaches 1.

FIG. 43 is a flowchart showing the operation for detecting camera shake. In step S31, the CPU 10 reads necessary information such as focal length from the lens. Then, in step S32, a TV value for shutter control is calculated by exposure calculation, and a TVL value of a camera shake warning limit is calculated from lens information. Then, in step S33, TV and T
Comparing the size with VL, if TV<TVL, YES, the process proceeds to step S34, and if TV>TVL, NO, the process proceeds to step S35. In step S34, the LOWSS signal is set to "High" to vibrate the marks CAI and CA2 to issue a camera shake warning, and in step S35, the LOWSS signal is set to "Low" to turn off the marks CA1 and CA2.

Figure 44 shows cputo and switches St, S2゜SB, S
Indicates the relationship with M.

Note that the location of the override display section may be different depending on the override setting mode and the AE exposure value display mode.

For example, when setting an override, the override value is brought to the center of the display. Also, while displaying the AE exposure value, bring the AE exposure value to the center of the display and move the override value to the periphery.

let it be placed

In each case, by moving important values as close to the center of the visual field as possible, the movement of the eyes required to view the display can be reduced, making the display easier to see.

Table 1 <Combination of r2n and B-> Bl -r51-r53. r61-r65B2-r
54 B3-r55-r58. 'r67, r68B4 -
rl -r29 B5 -r30~r43 B6-r59. r60 B7 -r44~r50 B8 -r66 Table 2 Table 2 (Continued) Table 2 (Continued) Effects of the Invention As detailed above, this invention displays the override amount and the metered manual deviation amount in the same manner. Since the information is selectively displayed on the device, the display device can be made smaller, and unnecessary data is not displayed, making the display easier to see.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing an example of a camera to which the present invention is applied, FIG. 2 a is a front view of the finder of the camera shown in FIG. 1, and FIG. FIG. 2C is a diagram showing an example of all the segments displayed on the internal display section of the display device of the present invention, and FIG. 3 is a block diagram showing an embodiment of the present invention. , Fig. 4 is a detailed circuit diagram of the oscillation divider section in Fig. 3, Fig. 5 is a detailed circuit diagram of the common driver in Fig. 3, and Fig. 6 is a detailed circuit diagram of the segment driver in Fig. 3. , Fig. 7 is a detailed circuit diagram of the data latch section in Fig. 3, and Fig. 8 is a detailed circuit diagram of the decoder section in Fig. 3.
Figure 9 shows the switch circuit SWt in Figure 8.
10 is a circuit diagram showing details of symbols in the circuit, FIG. 11 is a detailed circuit diagram of the data conversion section,
Figure 2 is a detailed circuit diagram of the switch circuit SW2 in Figure 8, Figures 13, 14 and 15 are detailed circuit diagrams of the segment decoder in Figure 8, and Figure 16a is the output of Figure 8. A detailed circuit diagram of the control section, Figure 16 is a detailed circuit diagram of a part of the circuit in Figure 8, Figures 17 to 20 are diagrams showing the relationship between input signals and displays, and Figures 21 to 20 are diagrams showing the relationship between input signals and displays. Figure 23 is a detailed circuit diagram of the data conversion section in Figure 8, and Figure 24 is a detailed circuit diagram of the data conversion section in Figure 8.
Detailed circuit diagrams of the voltage generating section shown in Figures 25 to 27
The diagrams are waveform diagrams of the main parts of the circuit in Figure 3, Figure 28a,
Figures 34-a, 34-35 are diagrams showing various aspects of display, Figure 36 is a diagram showing the relationship between signals and registers, and Figures 37-a, b, c, and 35 are diagrams showing various aspects of display. Figure 38a, b, Figure 39a. FIG. 40 is a flowchart of the CPU showing the display selection operation, and FIG. 41 is a diagram showing various aspects of display.
FIG. 42 is a flowchart showing the operation of the CPU shown in FIG. FIG. 4... External display section, 6... Internal display section, IO...
CPU. 22... Data latch, 23... Decoder, 24...
...Segment driver.

Claims (1)

[Claims] (1) An override amount calculation means, a metered manual deviation amount calculation means, a set of display means provided in common for each of the above calculation means, and a metered manual deviation amount calculation when the metered manual is set. and control means for displaying the result calculated by the means on the display means, and for switching to display the result calculated by the override amount calculation means on the display means in cases other than when the metered manual setting is set. A camera display device characterized by: