JPS61141423A - Dipslay device of camera - Google Patents

Abstract

PURPOSE:To make possible the intuitional and visual recognition of a warning for a camera shake by providing a warning signal generating means for generation the warning signal in the low-speed second stage and a display control means for lighting up alternately two display patterns by a warning signal. CONSTITUTION:The camera shake display is constituted of three segments and displays the camera shake by lighting up alternately the two segments among said segments. More specifically, a CPU10 reads the necessary information such as focal length from a lens and calculates a TV value for controlling the shutter by exposure calculation and calculates the TVL value of the warning limit for the camera shake from the lens information. The CPU compares whether the TV is larger than the TVL or vice versa. The CPU brings an LOWSS signal to a 'High' if TV<TVL and emits the warning for the camera shake by oscillating marks CA1, CA2. The CPU brings the LOWSS signal to a 'Low' and puts outs the marks CA1, CA2 is TV>=TVL.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a display device for a camera, and more particularly to a display device with a warning display for camera shake.

Conventional technology There are two ways to display warnings on cameras: visually by using light such as LEDs, and audibly by using sounds such as buzzers.
The symbol simply lit up or flashed. In particular, camera shake warning displays when taking pictures include a buzzer sound,
Various methods have been implemented, such as displaying the flashing LED dots and the time of 0 camera shake seconds, but all of them have problems such as not being able to intuitively know what the display is unless you know the display contents in advance. There were drawbacks.

As for the display using pictograms, etc., the use of mountains or dolls has been put into practical use as a distance display in a distance setting camera that uses visual measurement. Also, there are some that display flash photography information, and one that shows the exposure control mode with a picture is published in Japanese Patent Application Laid-Open No. 1986-
78033, etc., but none have been used as a camera shake warning.

OBJECT OF THE INVENTION It is an object of the present invention to provide a display device that allows a camera shake warning to be visually recognized intuitively.

Structure of the Invention The camera display device of the present invention is provided in the camera, and includes a display means for displaying at least two display patterns of substantially the same shape side by side, and a warning signal generating means for emitting a warning signal when the speed is low. The present invention is characterized by comprising display control means that alternately lights up the two display patterns in response to a warning signal.

Embodiment FIG. 1 is a diagram showing the external appearance of a camera to which this invention is applied, where ■ is the camera body, 2 is the shutter button, 3 is an interchangeable lens, and the interchangeable lens 3 contains data about the lens, such as the maximum aperture value. A device is provided that outputs data indicating such information as an electrical signal to the camera body. Further, the shutter button 2 is provided with a photometric switch S1 and a release switch S2, which are operated according to the amount of depression of the button, by a known method.

Reference numeral 4 denotes an external display section, which displays the calculated EV value and operation mode, as well as various other data that will be described in detail later.

5 is a finder, and within the field of view of this finder 5 is provided an internal display section 6 (see FIG. 2) for displaying data and the like displayed on the external display section 4.

SM is the main switch.

Figure 2 shows the details of the display on the external display section 4.
．． 9AE%-)'! iJTI7) PROGRAMS,
There is one. When AE mode is program mode (hereinafter referred to as P mode), PrlOGRAM
is displayed, and S is turned off. In the aperture priority mode (hereinafter referred to as A mode), A is displayed, and PrtOGR and MS are turned off. M and S are displayed in the manual mode (hereinafter referred to as M mode) and in the shutter speed priority mode (hereinafter referred to as S mode), respectively. Below that is the ISO mark for ISO mode, and just below that is the 7 segment 4 digit SS, ISO, CTR display, and to the right of that,
There is a setting indicator TAI. Below that is a bar that only turns off when the camera's main switch SM is turned off.
7 segment 2 digit F, +/~ across the display area.
There is a display section, and on the right side of it there is a setting instruction mark TA2. To the left of the 2 digits is an aperture value discrimination mark F, and further to the left is a +/- sign for override setting.
There is a mark.

Furthermore, FIG. 2C shows the details of the display on the internal display section 6.
Starting from the left end, there are 2 adjacent images for displaying camera shake (camera shake).
Mark CAI has two camera shapes.

There is CA2, followed by 7 segment 4 digit SS.

There are display sections for rso and CTR, and then S, P, and A for displaying AE momo. The S mark consists of a 7-segment arrow pointing toward the 4-digit side to indicate that the time is prioritized.
Similarly, the A mark is located immediately to the right to indicate aperture priority.
The segment consists of an arrow pointing toward the 2-digit side. The P mark has nothing to do with prioritizing both aperture and seconds, so there is no arrow between S and A. The 7 segment 2 digits on the right side for the AE momo display display the F value and the +/- value in the +/- mode. Immediately to the right is the M for displaying AE Momo.
There is a mark. This is because the metered manual display lights up at the same time, so it is displayed near the meter display to make it easier to understand. To the right are the override and metered manual symbols, tens and -, followed by a seven-segment numerical band.

This numerical band is used to display +/- values during AE mode (P, A
.

(S mode only) and metered manual value display in AE mode (M mode only).

Finally, there are the ASI and AS2 marks that indicate the metering mode. During average metering, only ASI lights up, and during partial metering,
Both ASI and AS2 are lit.

Figure 32 a, b and Figure 33 a, b are displaying auto (-ride), but the place where the override value is displayed in the infinder internal display is override (+/
-) mode and AE mode are different. This is an attempt to display the information near the center of the display section to make it easier to understand when the automatic ride mode is displayed.

FIG. 3 shows the overall configuration of the control device related to the above-mentioned camera display. CPU10, which uses a central control microcomputer that controls the operation of the entire camera, is supplied with power 1E from the battery port, main switch SM pulled up by resistor R, reference oscillator XL1 for operating CPU10, and peripheral circuits. A group of control signals (especially regarding display).

C8, PWC, serial data 5DATA necessary for serial data transfer, and a normal clock SCK are connected to the peripherals.

An outline of the operation of CPU10 will be described later.

On the other hand, the display circuit section 20 receives the power supply 1E from the battery 11, the main switch SM, the signals C8 and PWC from the CPU10,
5DATA, SCK, Me ff11m XL2. A reference power supply 21 for driving the liquid crystal is input, and the output is as follows.
There is a drive output group for the common and segment electrodes of the external display section 4 and the internal display section 6 using a liquid crystal display. The drive output terminal group is connected to the external display section 4 of the camera and the external display section 6 inside the fine knob, which are connected in parallel.

Inside the display circuit 20, there is a data latch section 22 that latches norial data. Decoder section 23 that decodes the latched data. Segment driver unit 2 that drives the LCDs of external and internal display units 4 and 6 using decoded signals
4. Common driver section 25 that drives the common section of the LCD
．． Oscillation frequency dividing section 26 that creates operating clocks for each section. L.C.
There is also a voltage generating section 27 that generates a driving voltage of D.
1. Fig. 4 is a detailed diagram of the oscillation frequency dividing section 26 shown in Fig. 3, which consists of an inverter (181-stage oscillation section) using an external crystal oscillator XL2 and a flip-flop (FFj) that divides this reference oscillation. The flip-flop FFI is provided with a reset terminal R so that it can be initialized by installing a battery.

FIG. 5 is a detailed diagram of the common driver section 25.
, VLCD2. Each voltage of VDD is connected to analog switch A.
φ through SI-AS4 and PchFET FPl, FP2. , φ1° timing to output to COMI and C0M2. Nantes Gate NA1.2. NOR gates NR1, NR2 and inverter IN3.4 are gates for creating timing, respectively.

FIG. 6 is a part of a detailed diagram of the segment driver section 24,
Vl, CD2. A φ9. φ1. Among the timings of the segment data S2n, 52n
It is configured to be driven in accordance with the -1 state. Nant gates NΔ3 to NΔ7 and inverter IN6.7 are S2
φ3. φ,
. It constitutes a clock generator to create clocks with four types of phase differences.

The entire segment driver section is of the type shown in FIG. 6, in which clock selectors, analog switches, and PchFETs are provided for the same number of SEG output terminals, and a clock generator is added.

FIG. 7 is a detailed diagram of the data latch unit 22. There are seven 8-bit soft registers SRI to SR7 that manually receive serial data 5DATA from CPU10, and the parallel outputs of these soft registers are Seven 8-bit latches LTI to LT that latch on falling edge
7 is connected.

The reset R manual power is applied to the jlO data of the latch LTI, and the set S manual power is applied to the "11 data", respectively, 310 data, and the j11 data is the power-on reset P.
It is reset and set by the On signal. Therefore, the initial state is NO=“LO”, jl I=”High
” is.

On the other hand, the serial clock SCK from the outside is passed through the OR gate ORI as the φS signal (NOR game) NR3 to NR
9, and also serves as the φλ power of the counter decoder CD. When the set input S of the counter decoder CD is “High”, the output B51 of the counter decoder CD
-BS7 are all “High” and S input is “Low”
o, every 8 pulses of φλ force sequentially changes from BSI to B
One of the signals up to S7 becomes "Low".

When any one of BSI to BS7 is "Los", one of the corresponding Noah gates NR3 to N1 (9 becomes active, and the Noah gate's human power φS
A signal is input manually to one of the serial registers SRI to SR7. The external control signals pwc and cs from the CP LJ register 0 are logically summed by the OR gate OR3 to become a p-cs multiplied signal, which is input to the other input of the OR gate ORI and the S signal of the counter decoder. In addition, it becomes the human power of one side of the OR gate OR2, and the OR logic is taken with the other human power BS7, and the flip-flop FF
It becomes one input of 0 manual power of 3 and Nantes gate NA8. Flip-flop FF3 is set manually by FOR signal S
and the q output is connected to the other input of NA8. Further, the small output φ in FIG. 4 is connected to the φλ force of the flip-flop FF3.

FIG. 8 is a detailed block diagram of the decoder section 23 shown in FIG. 3, and shows switch circuits SWI, SW2 . Data converter DCI-DC
4. Segment decoder sections SD1 to SD6. It is composed of an output control section CTLI. The switch circuit SWI has the outputs j12 to j of the decoder 22 as human power.
16. j22-j27. j32-j37. j4
0~''47, 25 lines, 4 outputs j50-j53 of the decoder 22 as human power in the data conversion unit DC3, and outputs jto, jz, jz, of the decoder 22 in the data conversion unit DC4.
)1j20. +21.
j54-j57. +60- +67°370~
A total of 53 of the 24 pieces of 377 are the latches LTt~ in Figure 7.
It is connected to the output of T7. Also, data conversion unit DC4
Two signals SM and DW of the main switch shown in FIG. 3 are input to the main switch. As shown in FIG. 4, output controller section CTLII has φ14 connected as an input, and 70 outputs 81 to S70 are connected to the segment driver section 24.

FIG. 9 is a detailed diagram of the switch circuit SWI in FIG. 8,
jn from data latch 22 (n = 12 to 47 (excluding 17, 20.2 +, 30.31)) → Pn
(n= 12~47 (+7.20, 30°3
25 signals to (excluding 1)) are switched by FOM, CTR, and [50° SS signals using 25 Nant gate NAs. FON, CTR.

When the l5O9SS signal is “Low”, the Pn signal is “
If igh', the jn signal is cut off, but the FON.

When the CTR, ISO, and SS signals are “Higb”, Pn
= jn, and the switch is turned on.

FIG. 1O is a diagram explaining the symbols used in FIGS. 11, 13 to 15, and 23, including A, B, and C.

For each input of J, the same function as the Nantes gate is shown by placing an O mark at the intersection of the arrow with the output Q. That is, Q=BID.

FIG. 11 is a detailed diagram of the data conversion unit DC3 in FIG.
The logic of outputs pi to p9 is shown for inputs 350 to j53. This output is powered by the switch circuit SW2 in FIG.

FIG. 12 is a detailed diagram of the switch circuit SW2 of FIG. 8, in which human power p1 to p9 are used to switch q71 to q78 . It represents the logic switched to q82 to q89. The human p signal is input to the Nantes gate,
When the switching signal MON and the +/-ON signal are "Low", the output q signal becomes "High" and the p signal is cut off. M.O.
When the N, +/-ON signal is "High", the output q signal becomes equal to the human power p signal, and the switch is turned on.

Figure 13 shows the segment decoder section 5DI-8D in Figure 8.
In the detailed diagram of 4, the output "■~r2" for human power ql-q39
It shows the logic of 9. This figure shows segment decoder section S.
Since the basic configurations of DI to SD4 are the same, they are shown in the same drawing, but the necessary parts of 5DI to SD4 are extracted from this drawing. This output is an input to the output control section CTLI shown in FIG.

141Q is a detailed diagram of the data converter Dc2 in FIG. 8,
The logic of outputs 440 to Q62 is shown for human power p12 to l)+6. This output is the input to the segment decoder SD5 shown in FIG.

FIG. 15 is a detailed diagram of the segment decoder section SD5 of FIG. 8, in which inputs q40-q62 . The logic of outputs 130 to r43 is shown for q71 to q78. This output is an input to the output control section CTLI shown in FIG.

FIG. 16a is a part of a detailed diagram of the output control section CTL1 of FIG. 8, in which the output of 51-S70 is obtained by the outputs of the segment decoder sections 5DI-8D6 and data conversion section DC4 and the clock φI4.

In this figure, r2n and B11 are shown in arbitrary combinations, but in reality they are connected in the combinations shown in Table 1.

Table 1 shows a truth table by replacing the circuit diagram of FIG. 16a with logical expressions. Furthermore, a combination of r2n and B- is specifically shown. (1≦−≦8).

(1≦21≦68) r69 is shown in FIG.

FIG. 16 shows input r69 and output s69. It shows the logic to s70.

FIG. 17 shows the relationship between the output ql-q, 39 of the data conversion unit DC1 of the decoder unit 23 and the characters displayed on the display units 4 and 6, and the inputs p22 to DC1 to the data conversion unit DC1.
p27. p32-p37, p40-p47. When Ql-(139 is output according to the state of CTR, Ql ~
The displayed characters are controlled depending on the state of Q39, "Low" or "High".

That is, if the output Ql is "High", the SDI will be displayed, and therefore the display unit 4 (top and 6) will display the lθ° digit as 0°.If q2 is "High", the IOo digit will display as 2.
1. Data are given as p22 to p27 for the shutter speed SS value, 932 to p37 for the ISO value, and p40 to p47 and the CTR signal for the CTR value. Also, I) 22~
When p27, p32 to p37, and p40 to p47 are all "High", no output is produced for that data. Therefore, for example, when the data of 1)22 to p27 for the shutter speed SS value is displayed, other data of I)32 to p37. It is constituted by a data converter DC4 and a switch circuit SWI so that p40 to p47 are all set to "High". (9th
(See Figures 1 and 21) Examples of contents that can be displayed are shown in Figure 18. There are 36 types of SS values, 31 types of IsO values, and 100 types of CTR values.

19 and 20 are diagrams showing the relationship between the data of the data conversion unit DC2 and the switch circuit SW2 and the characters displayed on the display units 4 and 6.
p12-p16 and SW2 pi-p9, MON, +
/-q40-q62. depending on the ON state. q71～q
78. The outputs of q82 to q89 output data similar to that shown in this figure. For F value, p12 ~ pl 6, for override value and metered manual value, p1 ~
Each data is given on p.9.

FIG. 2(2) is a part of a detailed diagram of the data converter DC4 of FIG. 8, and shows switch switching signals MON, 4-/-ON, and FON of switch circuits SW+ and SW2.

CTR, ISO, SS logic and CTL 1 part σN
, the logic of the OFF signal and the logic of the OFF V LCD signal applied to the voltage generator 27 in FIG. 3, respectively. The human input signal is the output signal jl O, N of the data latch section
1. +55. +56. j60= +67°+70. +
71 and Ex II (No. i, SM, PWC.

FIG. 22 is a part of a detailed diagram of the data conversion section DC4 of FIG. 8, and shows the logic of the B1-B8 signals of the CTLI section.

The input signal is the output signal j20. of the data latch section. j55
~j57. j61− +64°+70 to core 4 and external signal PWσ.

FIG. 23 is a part of a detailed diagram of the data converter DC4 in FIG. 8, and shows the logic of the signals "51 to "69 of the control unit CTLI.The input signal is the output signal j of the data latch unit.
21. j54～j57゜j70～j73. j75～j7
7 and the output signal q40 of the DC2 section. and external signal 1 starvation
It is. In FIGS. 21 to 23, the data conversion section D in FIG.
Contains all C4.

FIG. 24 is a detailed diagram of the voltage generating section 27. By creating a reference voltage VLCD by externally connecting a diode DI and a resistor R1 between 1E and GND, and supplying it to the booster circuit 27a (the part surrounded by the broken line) including the conode capacitor C1°C, (+E -V LCD) double voltage (10E -V LC
DI) is generated. Both VLCD and VLCDI are led to VLCD0 and VLCD2, respectively, by an output control circuit made of an analog switch and a PchFET.

V LCD0 and V LCD2 change their outputs depending on the state of 0FFVLCD. OP F Vl, CD /+
<When “Low” (7), VLCDO=VLCD,
VLCD2=VLCDl, and 0FFV LCD is '
When “High”, V LCD0 = V LCD2
= V DD In addition, the booster circuit section 27a obtains a clock from φ6 in FIG. 8, and thereby switches the connection of the conode capacitors 〇+ and Cy to perform boosting. Further, FOR is a terminal for starting the booster circuit, and is started by POr (output) shown in FIG.

FIG. 26 is a time chart of the data latch section 22 of FIG. 7. External signals pwc and cs- both become “Low”, and when SCK falls, the norial reno star 5ltl
-5117 data will be rewritten.

At the falling edge of the first 8th pulse of SCK, the contents of SRI are rewritten by 4 times, and from the 9th pulse, the contents are rewritten every 8 pulses in order from the 9th pulse to noft train stars SR2 to SR7. At the rising edge of the 49th pulse immediately after SR6 is rewritten, R57 becomes "Low" and at the same time the rewriting of SR7 begins, in flip-flop FF3, in order to read 0 manual force at the rising edge of φ, σ of F'F3 is changed. The output is”
BS7 becomes "Low" and does not change until BS7 becomes "High" again.

d-output “2°08 signal 2 to 1・LTcHp<tbx
.

is created, and the contents of serial registers 5rtl to SR7 are taken into the latches of Tl-LT7.

FIG. 25 is a time chart showing the general operation of the entire apparatus from the time after the N oil was deposited on the camera. Immediately after the battery is installed, the display circuit section 20 is initialized by the POI' (signal.
LCDI becomes earth GND level, OF F V
LCD M “High” Therefore, no voltage is applied to the liquid crystal. Then XL of CPU10
I starts oscillating, and CPU10 starts operating. After a while, the oscillation 1WXL2 of the display circuit section 20 starts oscillating, and the clock φ.

~φ14 starts to start. When the clock φ starts operating, the data latch unit 22 starts operating, and when the norial data comes from CPolo, it operates as shown in FIG. 26. When the clock φ starts operating, the voltage generating section 27 shown in FIG. 24 starts operating, and after a short period of time, the potential of the signal VLCDI becomes stable. After that, OF F V LC as necessary.
If D is set to “Low”, the liquid crystal drive voltage, VLCD
O, VLCD 2 is supplied to display sections 4 and 6.

28 to 35 and 37 to 39 show various display modes of the external display section 4 and the internal display section 6, and except for FIG. The figure shows the display on the internal display section 6.

Figures 28a and 28b are AE displays in program mode, showing auto second time 1/250, auto aperture value 5°6, program PROGRAM, and reverse discharge.

The mark ASI at the right end of FIG. 28 is a metering mode display and indicates average metering.

Figures 29a and 29b show the AE display in aperture priority mode, where the aperture setting mark indicates the set aperture value of 5.6 and the auto second time of 1/250, and the aperture priority A and crane represent the AE mode. .

FIGS. 30a and 30b are AE displays in the tweeter time priority mode. When the glossy second setting mark is pressed, the set glossy seconds value is 1/250 and the auto aperture value is 5°6.

FIGS. 31a and 31b are AE displays in manual mode.

The setting of the glossy seconds and aperture value is 8" and the aperture value is set to 1.4, and the manual mode is M, and the mouth indicates the AE mode. The right end of the internal display is This is the partial metering mark of the metering mode, and the left side of it is the error amount of the manual setting value with respect to the appropriate value, which is the so-called metered manual indication value, +6
．． This indicates that there is a difference in indication of 5EV. Also, the mark on the left side is a mark indicating camera shake (hand shake) warning, and 2
The two marks will light up alternately.

FIGS. 32a and 32b are displays during override setting. Represents the override direction and absolute fik1.5E■.

FIGS. 33a and 33b show the AE mode display after override setting. An override direction indicator is added compared to FIG. 28. Also, the internal display shows the absolute value of 1.5 EV of override. However, +1 and 5 are blinking on the internal display.

FIGS. 34a and 34b are displays during ISO setting.

+50 mark and IsO value of 100 are displayed.

However, the ISO mark does not light up on the internal display.

FIGS. 37a and 37b show hand shake (camera shake) warning displays. In the internal display section 6, mark CA of the leftmost camera
1. CA2 lights up alternately to indicate movement.

FIG. 37C shows the display on the external display section 4.

FIG. 35 is a display in standby mode.

Only the bar display was covered with hail, and all other lights were off. Functions other than camera display are in a stopped state.

Description of Operation> - Overall Operation - The basic operation of the display circuit section 20 will be explained. When the DC voltage +E is supplied from the power supply 11, the momentary F generated by the power-on reset circuit 40 (the right end of FIG. 4)
The OR signal causes the flip-flop FFI (FIG. 4) of the frequency division stage and the flip-flop of the clock generator of the segment driver section 24 to be activated.
1-tube FF2 (FIG. 6), flip-flop FF3 of the data circuit 23. The latch LTI (FIG. 7) and the starting FET 27b (FIG. 24) of the voltage generator 27 are each set to the initial state. In the launch LTl, each data terminal is jlo-“Low”.

jll - Set to “High”. flip flop FFI
.

In FF2, the output state is set to Q=“Low” and σ−“High”
”.In FF3, set the output state to Q-“l-1-1
i”.

Set 1=“Low”. In the voltage generating section 27, FET
When 27b is turned ON for a moment, the charge is churned in the capacitor C, and the level of VLCDI becomes the GND level. In this state, the crystal oscillation 1 of the oscillator 41 (FIG. 4)
5XL2 has not started oscillation, there is no circuit operation at all, and the internal state resulting from the initial setting value and undefined state is waiting for the oscillation chamber of XL2 to stop (=oscillation rise of φ). One way, -11-VDD, V through the COM and SEG terminals on the LCD display side of the external display section 4.6.
l, C2, Vl, DO are given in an undefined state (COMI is VLCD2° C0M2 is VLCDO, 5
EGn is VDD or VLCD2) depending on the state of S2n and 52n-l.
F V LCD is jl O="Low", jl-"Hi
Due to the initial setting of ``high'', the switch circuit 1 in FIG. 24 is set to ``High'' through AND gate A50.
') V LCD2 = V LCD0 = V DD, and the voltages applied to each terminal of the LCD display on the inner and outer mounting portions 4.6 are equal, and there is no DC voltage application condition that is harmful to the liquid crystal.

Next, the crystal oscillator XL2 starts oscillating and φ. When a clock enters the flip-flop FFI in the frequency dividing stage, all parts start operating at the same time.

The clock φ enters the flip 70 block FF3 of the data launch unit 22 and serves to generate an L, TCH pulse when the communication of the normal data from CI)tJlO starts.

The clock φ6 enters the booster circuit of the voltage generator 27 and is input to C1.
, Cf is switched to perform boost operation.

Clock φ9. φ,. enters the common driver section 25 and segment driver section 24 and becomes a clock for the liquid crystal drive waveform.

The clock φ14 is input to the output control unit CTLI of the decoder unit 23 and is used to control the blinking state of the display contents.

The operation after the rise of oscillation of the crystal oscillator XL2 will be explained first with respect to the voltage generator 27. The clock φ8 input to the booster circuit 27a in FIG. 24 starts boosting operation, and the initial VLCD
What was the ILCD display level (V DD-2V
LCD) level and stabilize it. From then on,
It continues to work without interruption until the power supply voltage drops and it stops operating, or the oscillation circuit stops, causing the lifting and lowering operation to stop. On the other hand, the data latch circuit 22, which has started operating due to the leak φ, causes the terminals NO and HIf to
lol.

At the moment when a signal other than "High" is input and latched, OF
VLCD1. VLCDO = Wait for VLCD output. These are common drivers 25. The internal and external display sections 4 are guided by the segment driver 24 as a voltage for driving the liquid crystal.
．． A liquid crystal display is performed based on the latched data.

Next, the data latch section 22 will be explained with reference to FIG. 26. This circuit starts operating when both the pwc and -cs multiplied signals become "Low". vWτ is, for example, a timing signal for supplying power to a photometry circuit of a camera (not shown),
The photometering circuit starts operating when We-'Low' is set. Also, the buzzer is a signal to determine the other party for serial data communication, and is also used as a CI signal for other circuits in the camera (not shown). 'There is one for each from UlO.C
“-“Low” selects the other party for serial data communication.

When either pwc or τhyakusu is “High”, P・C
8 signal is “High”, the counter decoder CD is set, and all BSI-B57 outputs are “High”.
It is said that Also, the output φ8 of OR1 (or game) is “I-
l-1i", Nant Gate NA8°8"1°"°
When “0° pins 5', 1, and 71 are all “Low”, the counter decoder CD enters the operating state, and the OR gate ORI and OR gate OR2 open, and SCK and BS7
The signal becomes detectable. BSII at the rising edge when the first SCK pulse is input! + becomes “Low” and Noah Gate NR3 opens. Since the φλ force of the shift register SRI rises at the fall of the first pulse, only one shift register S RI M takes in the contents of 5DATA at that time. The data at this time is NO. Then a second pulse comes and the same operation is repeated. At the falling edge of the eighth pulse, eight pieces of data /J are taken into the shift register SRI, and the eighth data is called j177. Until this time, the signal BSI is "Low".

When the next ninth pulse rises, BSI becomes "High", BS'2 becomes "Low", NOR gate NIL3 closes, and NOR gate NR4 opens. Since the φλ force of the knot resistor Sn2 rises at the fall of the 9th pulse, the 5D at that time
Only one shift register SR2 takes in the contents of ATA. The data at this time is 320. Thereafter, the process continues in the same manner, and at the rise of the 49th pulse, BS6 becomes "High", BS7 becomes "Ov", NOR gate NR8 closes, and NOR gate Nr19 opens. Furthermore, or gate OR2
The output becomes “Low”. The contents of shift register SR7 will be taken in from 370 to 77 up to the 56th pulse, but 1 after the 56th pulse will be taken in.
, TCH output remains High'', and data is not fetched from each shift register SR to latch LT.
2, the output of the OR gate OR2 becomes "Low", but the rise of the clock φ causes the output of the flip-flop I♂
F3 takes in “Lo” of D input, and 1 output is “H”.
However, since the other input of the Nant gate NA8 becomes "Low" before the σ output changes, the L T CH output remains High.

Here, the output of the OR gate OR2 becomes "High" depending on whether the 57th pulse comes or whether either pwc or cs becomes "High". At this moment, the σ output of flip-flop FF3, which is the other human power of Nantes gate NA8, is "H trend h", so the output of Nantes gate NA8 is LT.
CH becomes “L ov”. This-I(ight)-“L
The falling edge of “ow” is a latch signal, and the data stored in shift renostar 5RI-5L (at 1:00 at 7 is latched L).
TI to T7 are latched into the data memory. After that, with the rise of the clock φ, the flip-flop FP3 takes in “lligh” of 0 manual power, and the σ output becomes “Low”.
”, and the counter decoder CD is pwc, cs
o It is set at "High" and each returns to its initial state.

The above is an overview of the operation of the data latch. If the number of clock bytes for Norial data communication is insufficient, the last latch pulse LTC-1-1 will not output, so no data error will occur, and even if the number of clock bytes exceeds, it will automatically start at the 57th pulse. Naturally, no abnormality will occur if it is cut. Also, clocks within the same byte are
Since UfIIJ processes the data without interruption, it completely prevents abnormalities in data communication.

On the other hand, even if the external signals PWτ, US, SCK, and 5DATA operate normally, if the internal φ is not operating, “1
100 “The pulse stopped coming out, Noftrenosta SRI~S
Latch the data captured in It 7 from LTI to LT7
It will not be possible to latch on. This means that if it is considered that the liquid crystal drive waveform does not operate when φ is not operating, a DC voltage will be applied to the liquid crystal. Therefore, at that time, NO-"Lov", jl l-"High
It is necessary to maintain "OF V LCD-" and set it to "High" so that no voltage is applied to the liquid crystal.For this reason, external data is not taken in when the clock φ is not operating.

Next, the common driver section 25 and the segment driver section 2
I will explain about 4.

In Figures 5, 6, and 27, Nant Gate N
A1. NA2. Noah gate Null, NR2, inverter N3. The analog switch ASI-AS4゜Pch PET FPl,
Controls each switch of FP2. The input signal of the gate circuit is φ9. Tomorrow at φ1o, due to this timing, C0M
2. The outputs of COMI change as shown in FIG. 27. The signals C0M2 and COMI have the same period as the clock φ1°, and are shifted from each other by 1/4 period.

The output value has three levels: VDD, VLCD0, and VLCD2.

In Fig. 6, four types of clocks generated by the clock φ and φ, 0 processed by the clock generator composed of the inverter IN5 and the flip-flop PF2 are generated by the clock selector composed of the Nantes gates NA3 to NA7. select. The selection conditions are S2n,
52n-1, and by this condition, 5E
The output waveform of Gn is determined.

This state is shown in FIG. 27, and each state is different depending on four types of states determined by S2n and 52n-1.

The period is clock φ,. , and there is a shift of 1/4 period from each other. The output values are VDD and V
It has two LCD levels. signal COMI,
The potential difference between 2 and segment signal 5EGn is 2 X V
The LCD display lights up depending on the waveform of the portion that becomes LCD2. COM, 5EGn (LH), 5EGn
The segment of the LCD display to which a voltage of (HH) is applied lights up, and 5EGn (, HL
), an LCD to which a voltage of 5EGn (HH) is applied
The display segment lights up. For 5EGn (LL), the segment will not light up even for COMI and C0M2.

In other words, the 52n-1 signal is a signal that controls lighting of the segment for COMI, and 52n-1=“Low”
When , it is OFF, and when S 2n -1 = "High", it is ON. The S2n signal is a signal that controls lighting of the segment for C0M2, and is turned off when 52n="Lov-" and turned on when 52n="High".

Data latched in Figure 7 jlO~j17°j20~
j27. j30-j37. j40～j47゜j50～j
57. j60-j67,. 70-j77 is jl 7. j
30. All except 3 bits of j3l are input to the indicator decoder section in FIG. SWI.

SW2. DCI to DC4 and SDI to SD6 are simply gate circuits and have no timing relationship at all.

The explanation is below.

First, the contents of the serial data will be explained.

jl O, N I is a signal for controlling the supply of the liquid crystal driving voltage, and the liquid crystal driving voltage stops only when jlo-“Low” and jllr “High”, and the voltage applied to the liquid crystal becomes O.

j12 to 316 are data signals regarding the aperture value of the camera (
(see Figures 9, 14, 15, and 20),
There are 23 types. When all 16 are "High", nothing is displayed.

j20 is a signal related to a warning of insufficient battery voltage in the camera (see Figure 22), and j20-“High
”, all the displays displayed repeatedly blink at the cycle determined by φ14.

j2 This is a hand shake (camera shake) warning signal (see Figure 23), and becomes "High@" when the shutter speed becomes slower than near the limit that causes hand shake (camera shake).

At this time, the camera shake mark CA1 on the internal display section 6 in the viewfinder. CA271 (lights up alternately).

”22 to j27 are data trusts regarding the Nyatta second time value (
(see Figures 9, 13, 17, and 18),
There are 36 types. Also, j22 to j27 are all High
”, nothing is displayed.

Numerals 332 to 37 are data signals related to the ISO value of film sensitivity (see FIGS. 9, 13, 17, 1, and 18), and there are 31 types. Further, when all of 32 to j37 are "High", no display appears.

j40 to j47 are data signals (
(see Figures 9, 13, 17, and 18),
There are 100 types from 0 to 99.

Also, nothing is displayed when j40 to j47 are "High".

350 to j53 are data signals related to override values and metered manual deviation amounts (see Figures 11, 12, and 19 and 20), and there are 9 types of override values depending on the content to be displayed.
1 and 14 types of metered manual deviation values are switched and sent from the CPU. j50～j
When all 53 are "High", no display appears. For switching the display contents, see j55. The receiver has the j56 signal (described later).

354 to 356 are 5IGN signals (see Figures 21, 22, and 23) related to the override value, the sign of the metered manual deviation amount, and signal switching, and j54 is "+" and " −” Signal related to the sign,
j55 and 356 are signals for switching data between the override value and the metered manual deviation amount for each external display and internal display.

j57 is a signal used to temporarily display the so-called preview (see Figures 22 and 23), which is used to check the depth of field by narrowing down the aperture of the lens before taking a picture. Sometimes this signal becomes "High", causing the aperture mark F on the external display section 4 to blink and the set value range indication mark TAI.

Controls the lighting of the bar at TA2.

j60 is an ISO display priority signal l5OPRI. This means that the main switch SM is OFF, and OFF
Even if the LCD signal is "High" and the liquid crystal drive voltage is stopped, when this signal becomes "High", the liquid crystal drive voltage is increased by the segment driver 24. The 0FFV LCD signal is set to “L” so that it is supplied to the common driver 25.
ow” (see Figure 21) This signal is not used alone, but is sent from cpulO as well as the ISO display mode and ISO value data at the same time as this signal. This is the sound immediately after.

j61 is a blinking signal of the deviation amount of the metered manual M'dMOVER (see Figure 22), and whether this signal is "I-
The deviation value of the metered manual flashes at "l-1i".

j62 is a shift signal 5HIF to blink the program mode mark during the camera's program mode software.
T (see Figure 22), j62 or “II igh”
This mark will blink. here,
Software refers to a state in which the combination of the aperture value and the second value in the program mode is changed and operated. In addition, if necessary, all AE
The mode can be blinked.

j63 is the control interlocked warning signal Not, C0NT (22nd
(see figure), and this signal goes “High” when an exposure value that exceeds the aperture value and second value that can be controlled by the camera is required.
h”, and the aperture value and/or second value flashes on the calculation control value side depending on the AE mode to issue a warning.

j64 is the brightness out-of-linkage warning signal BV (see Figure 22), and when the brightness value exceeds the brightness value that the camera can measure, this signal becomes "Ilight" and the ASI and AS2 during the metering mode display. flashes to warn you.

j65 is the bulb time signal BULB (see Figure 21), and the camera switches the 4-digit, 7-segment display content from the flashing seconds display (buLb) to the bulb exposure seconds count display during bulb exposure. ”, the valve count will be displayed, and the contents of j40~]47 will be displayed.

j66 is an all-lights-off signal ALLOFF (see Figure 21), which is a signal that controls the waveform of the SEG terminal for driving to an all-OFF waveform (see Figure 27, 5EGn (LL)), and is "Low". The OFF display will appear. However, the camera marks CAI and CA2 cannot be controlled.

j67 is an all-on signal ALLON (see Fig. 21), which turns all the waveforms of the SEG terminals for driving into ON waveforms (see Fig. 21).
(See Figure 5EGn(HH)).
-l-1i” all display ON.

However, the camera mark CA1. CA2 cannot be controlled.

j70. j71 is the camera operation mode signal CALL M
ODE (see Figures 19, 20, and 21), and the camera is not operating even in normal AE mode, main switch SMh<ON, 5TANDBY%-mode, ISO
■so mode for settings/display, +/+ for general settings/display
There are four states: /- mode, and the display contents can be changed according to each mode. (See Figures 28 to 35)j72. j7
3 is the camera's AE mode signal AEMODE (see Figures 22 and 23), which has four states: program mode, aperture priority mode, glossy second priority mode, and manual setting mode. Switch the displayed content.

j74 is the IsO output when prompting to set the ISO value
This is the warning signal ISOARM (see Figure 21 tKl), and when this signal becomes “High”, the IS
The O mark and ISO value flash.

Noah 5 is a mode light-off signal MODE OFF (see FIG. 23), and when this signal becomes "High", the AE momo display being displayed is turned off. Turn off the mode display when loading film into the camera.
Make it.

j76 and j77 are photometry mode switching signals AVE/5POT
(See Figure 23), and when the partial metering mode is selected between the average metering mode and the partial metering mode (either 376 or j77 or i becomes "Low"), the viewfinder's internal display Turn on AS2 in section 6. ASI is always lit during AE mode.

The DC4 also uses the external signals SM and FWU as data, and is connected to the data code conversion section (Fig. 23) and the L of the display section 4.6 regarding the display of the shutter time value, aperture value, etc. outside the numerical band.
A decoding section (FIG. 22) for controlling blinking of each display segment of the CD display, and two signal switching sections SW1. S
It is divided into three parts: a decoat part (Fig. 21) related to W2.

Figure 21 is created mainly with SWI and SW2 switching signals, and FOM, CTR, ISO, and SS signals are SWI and SW2 switching signals.
, MON, +/-□H signal controls SW2. In addition, the σN and OFF signals are commands to control C'rLl and display an ON display and an OFF display for all segments. Furthermore, the 0FFVLCD signal is "
When "High", the LCD drive power supply and LCD drive circuit are turned off.The purpose of this is to prevent DC voltage from being applied to the LCD when the XL2's primary oscillation is stopped, and to turn off the main switch SM of the camera. This is a reduction in power consumption.

On the other hand, CALL MODE signal 370.371 indicates four camera operation modes, j70, Y ""-"Hi
gh” is the AE mode deactivation for normal shooting.j70
・When j71='l-1-1i" f! It is called ISO mode for setting ISO sensitivity. j7o-371-"High
” is called the STAN BY mode, which is a camera standby state. j70/j71 - When it is “High”, it is called the +/- mode for setting the override amount.

To explain the signals for SWI and SWZ according to the above four modes (see Figure 21), during AE mode, Y
WC becomes “°Low” (the camera starts operating).
Then, the FON signal becomes “High” and SWI works,
Aperture pure information j12 to j16 is selected and decoded and displayed. When the PWC becomes “)I igh- (the camera is in standby mode), the FON signal goes to “Lo”.
v'', and the aperture value information is erased by SWI.

On the other hand, when PWC is “Lov” and Colo 5 is “Lov” (
During normal operation), the SS signal becomes "High" and the glossary second and hour reports j22 to j27 are selected and decoded and displayed. At this time, Ike's CTR signal and ISO signal are “L 01
”, and the timer count information and iSO value information are SW
It is erased by I.

When PWC- is "Low" and j65 becomes "High" (during valve counting), the CTR signal becomes "High" and timer count information j40 to j47 are selected and decoded and displayed. At this time, the other SS signals and ISO signals are "Low", and the glossy seconds and ISO signals are low.
Value information is erased by SWI.

Also, the +/-ON signal is Low, but the MON signal is p.
wc- is “Low” and j50 or j56 data is “Low”
If it is "High", it is "High", so the value information of the deviation amount of the meter to manual is selected and decoded and displayed by SW2, but the value information of the override is erased.

In 150 mode, SS, CTR, PON, MON.

All +/-ON signals are "Low", only the ISO signal becomes "High", SWI operates, and the tSO value h!
1Nj32~13°/+(illtlゎ, 7-□y8ゎ).At this time, other numerical ranges are erased.

5 During TANDBY mode, SS, CTR, FON, I
The SO, MON, ←/-ON signals are all "Low", and all numerical bands are erased.

In ÷/- mode, SS, IsO, CTR, FON, M
All ON signals become “Ow” and PWC becomes “L ov”
At this time, the +/-ON signal becomes "I-l-1i".

At this time, override information j50 to j53 are selected and decoded and displayed.

Figure 22 shows a control signal for the blinking display of each display segment. When outputs 81 to B8 become "I (high"), if the corresponding segment (see Table 1) lights up, The segment will flash.

The B8 signal is a signal that causes the F mark on the external display section 4 to blink, and is mainly controlled by 357 data.

The B7 signal is the 7th segment of the LCD of the internal display section 6.
This is a signal that flashes the numbers 8 and 8, and the col and 2 second digits between them, mainly j55. j56. It is controlled by the data of j61.

The B6 signal is a signal that blinks ASI and AS2 on the internal display section 6, and is mainly controlled by j64 data.

The B5 signal is a signal that causes numbers 5 and 6 of the 7 segments, cal, and I to blink on both the external and internal display sections 4 and 6, and is mainly controlled by the j63 data.

The B4 signal is a signal that blinks the external/internal display section 4.6 and segments 1 to 4 of 67, and is mainly controlled by data 363 and j74.

The B3 signal is a signal that causes the AE mode display section of both the external and internal display sections 4.6 to blink, and is mainly controlled by the j62 data.

The B2 signal is a signal that causes the ISO mark on the external display section 4 to blink and is mainly controlled by the data of the core 4.

The Bl signal is the CAlt! among the segments other than the segment output from 88 to B2. : There is no particular data signal that causes all of the signals except CA2 to blink. However, including Bl, blinking is controlled by j20 data from 82 to B8.

FIG. 23 shows a decoder for seven segments for displaying numbers in the inner/outer representation section 4.6, except for 1 to 8 and col, I, col, and 2. Serial data j54 to j57. j70-j73. j75-j77, j
21. The output is controlled by the external signal "Vc" and the decoded DC2 output signal q40, and the outputs are from r51 to "69", and when each output becomes "HIGH", each corresponding segment lights up.

FIG. 9 shows SW1, which selects signals.

The input signals are the aperture values of j12 to j16, and the aperture values of j22 to j16.
These are the shutter time value of j27, the tSO value of j32 to j37, and the timer count value of j40 to j47, and there are a FON signal, CTR signal, ISO signal, and SS signal to select each of them. When each selection signal is “High”, it is NAND
The gate opens and the output data p becomes human power data j. On the other hand, when it is "Low", the NAND gate closes and the output data p becomes "High".

(Example) When FON is "high", outputs p12 to p16 transmit inputs j12 to j16 as they are.

When F ON = "Low", all outputs p12 to pt6 become "Ilight".

Next, although there are no detailed diagrams, DCI will be explained.

DCI is serial data j2 processed by SWI
2-j27. j32-j37. p22-p27. corresponding to j40-347. p32-p37, p40-p47
ql-4 which corresponds to 7 segments and 4 digits.
Data conversion i! with 39 data as output! ! (decoder). Figure 17.

Figure 18 is for explaining the concept of DCI,
The input data is 36 types of Nyak second time values (SS values) (buLb-1/4000) corresponding to p22 to p27 and ALL
High, IsOSS value type corresponding to p32 to p37 (
ISO6~l5O6400) and ALLHigh, p4
Timer count value (CTR value) 1 corresponding to 0 to p47
00 species (01-99”) and A L L High
There is 1.

For example, data p27~corresponding to SS value rbuLbJ
When p22 = 'LLLLLL' is input (other data p32 to p37 at that time. p40 to p47 are A L
Processed with DC4 and SWI to make it L High. ) Output data is q7 data "b" for segment decoder SDI, Q18 data " for Sn2"
Similarly, q29 data is "U" for Sn2, and q39 data is "b" for Sn4.

In addition, data p37 to p corresponding to the tSO value r200J
32="LHHHLL"' is input, other data at that time 922-p27. p40-p47 are ALLI-1
Processed with DC4 and SWI to make it bright. )
The output data is ql for the segment decoder SDI.
For data, q8 data is output for Sn2, q21 data is output for Sn2, and data for Sn4 is not output.

Also, P22-p27, p32-p37, p
When all of p40 to p47 are "High", no output is output to the segment decoders 5DI-8D4.

All segments for 5DI-Sn4 are turned off.

It is composed of a gate circuit having the above configuration.

Next, segment decoders SDI to SD4 shown in FIG.
I will explain about it. The data signals of qt to q39 obtained in the previous section are converted to SDI for qt-47 and Sn for q8 to q08.
2, q19 to Q29 to Sn2, and q30 to Q39 to S
Enter in n4. The inside of the 5DI-8D4 is basically the same, but among the 14 terminals, the terminals to which the corresponding data signals are not input are pulled up to the +1 source side in each block. The human power of this circuit is configured so that an effective output can be obtained when it goes to "Low". For example, S0
When the q7 data signal (b of buLb) is output for 1,
“5 manpower becomes °Low”. At this time, other SDI inputs 91 to q6 and the manpower being bulldozed become “High.”
h”, but the outputs (c), (d), (e), (f), and (g) related to the line that became “Low” all become “High” and the outputs (a), ( b), (h
) line is.

This output is (c), (d), (e)
, (f), (g) are "3~r" in terms of SDI terminals.
7, which is input to the next stage CTLI and connected to the liquid crystal display. This r output corresponds to the liquid crystal segment approximately l to I (see Fig. 16a, Figs. 2, c, and Table 2). The output here (c), (d),
(e), (f).

(g) corresponds to the numerical segment name of each of the seven segments, and represents the character "6" (see Figure 2).

Furthermore, for example, for SO3, the q21 data signal (“2
”) appears, the ■ input becomes “Low” (a).

(b), (d), (e), (g) are “High”
Then the character "2" will be displayed.

p12 to p16 obtained by SWt enter the decoder DC2 shown in FIG. When pie~p12='LLLLL', the output is Q40, and a "Low" output is output. q
The output of 40 goes to segment decoder SD5, while
Output to decoder DC4.

Other outputs are connected exclusively to SO2.

The contents of the outputs of q40 to q62 based on the data of 912 to p16 include 23 types of aperture values shown in the concept of SO2 shown in FIGS. 19 and 20. These are subjected to a segment decoder in a part of SO2 (input part of q40 to q62) shown in FIG. 15, and outputs of r30 to r43 are obtained.

For data j50 to j53, decoder D in FIG.
There is C3. j50 data is decimal data,
A p1 output and a p2 output are obtained.

j51=353 data represents the information of θ~6, its output is p3~p9, and the output is "High" and becomes an active state part. This output is input to the switch SW2 in FIG. 12, and the output light is switched according to the selection information MON, +/-ON. When MON is “High”, +/-ON is “Lo”
w", and the outputs of p2 to p9 are inverted and q82 to
It is output to q89, but q7t to q78 are all “Hf
becomes “gh”.-Rikishi/-When ON is “High”, M
ON is Low @, and the output of pl-97 is inverted and output to q71-q77, but q82 to q89 all become “High” and q78 becomes “Loo”.
・MON・ 11+/
- When both ON are “Low”, q71-478°48
The outputs of 2 to Q89 all become "High".

The output of SW2 is Q71 to q78 to SO2, q82 to Q
89 is output to SO6.

The contents of q71 to q7g and Q82 to q89 output by SW2 are as shown in Figs.
~q89 corresponds to seven types of integer digit numerical values for metered manual values (including override values) and one type of decimal display.

Although the contents of SO6 are not shown, the basic idea is the same as that of SDI to SD4 in FIG. 13, and is shown in FIG.

The gate configuration is such that there is a relationship between the data shown in FIG. 20 and the output display example.

Finally, the "
1 to "69 and B1-88. When the ON and OFF signals and the clock of φ14 are input, the output control section CT
LI will be explained.

The internal configuration of CTL I is already shown in FIG.

r69→S69. Except for the configuration of the S70 portion, the configuration is basically as shown in FIG. 16a. First, in Figure 16, when a "High" signal is input to r69, the gates for 869 and 870 open and the clock of φ14 opens.
“High” and “Low” are repeated, but S69 and 5
70 outputs in reverse phase. In this way, the corresponding CA1.
The CA2 mark lights up alternately, giving the impression that the camera mark is blurring. Regarding circuits for signals other than r69, logical expressions and truth tables showing the relationship between the output S and the input r are shown in Table 1.

As this table shows, “When the immediate signal becomes “Low”, the output S
All except S69.570 are "High" and the displayed content is CA1. It lights up except for CA2.

Next, when the image signal is “High”, the OFF signal is “H”.
When the display becomes "high", all the outputs S except for S69 and S70 become "Low", and all the displays except for CAI and CA2 turn off.

When Bm (Bl-88) becomes “Low” when the ON signal is “High” and the OFF signal is “Low”, the output S-
", and according to the display information given by the serial data.
The display will light up according to the displayed content.

The σ signal is “High”, the OFF signal is “L ov”,
When any part of Bm (Bl-88) becomes “High” by DC4, r in the same group will be determined according to the combination of B and r under the truth table in Table 1.
The output S corresponding to .phi., 4 flashes according to the display contents at that time in accordance with the clock of .phi.,4.

For example, when the B6 signal is “High” and the other I31~
BS, B7. When the B8 signal is “Low”, the corresponding outputs S59 of r59 and r60 in the B6 signal group
and seo repeats “High” and “Low”.

However, if the states of ``59 and r60 are ``Low,'' S59 and 860 cannot become ``High.'' Therefore, As2 and AS corresponding to S59 and S60
If I is lit, it will change to flashing.

The outputs 5l-970 obtained from the above CTLl are input to each segment driver (Fig. 6), and output as a liquid crystal drive waveform (see Fig. 27) to the final output SEG terminal (SEGI-8EG35). .

The relationship between CTLI output S and SEG terminal is not shown in Table 2.

The names of the segments shown in this table are the same as the names of all the segment diagrams shown in FIG. 2C.

1. When starting the camera - When the camera is started by turning on the main switch SM, an interrupt is generated to the CPU 10, the CPU 10 is released from the stopped state, and the camera starts operating according to the program in the internal ROM. At the same time, voltage is supplied to a photometric circuit (not shown), but it takes several thousand milliseconds for the photometric circuit to operate reliably and provide the necessary data to the CPU 10. do.

However, the CPU 10, which operates at high speed, has communicated serial data with the display circuit section one or more times at this point. The content of the serial data communication (see Figure 36) is mainly exposure information - shutter time, aperture value, etc., but if the photometry circuit etc.
1' Accurate values of these exposure information cannot be obtained when the device is not constantly operating. Therefore, it is not good to carry out norial data communication in this state because it not only has no meaning but also results in erroneous display. Therefore, at startup, C
Until PU10 takes in accurate information and completes the calculation, it is possible to avoid displaying a troublesome inaccurate value on the display by sending data to turn off the lights or data for standby display. . The display section of the embodiment has a structure in which the previous display is maintained unless new serial data communication occurs. There is no particular problem as long as no real data is exchanged until the calculation is completed using this, but the CP
Since the U10 program is designed to create a program flow with as few special exceptions as possible, a method of serial data communication at regular intervals is better in the sense that it does not increase the capacity of the ROM for the program. Therefore, the above method becomes better.

Immediately after the battery is installed in the camera, a voltage of 10 E is applied to the CPU 10 and the display circuit section 20, and each starts operating. Each circuit has a separate crystal oscillator XL1. XL2
, and starts operating independently, but in this case, XLI
Generally speaking, XL has a higher frequency than XL2.
I starts oscillating early. After the oscillation starts, the CPUIG starts operating according to the program in the internal ROM, but since there is little work to be done immediately after the battery is installed, it stops functioning after several tens of seconds, and waits for it to be woken up again. There is. Generally, at this point, the XL of the display circuit section 20 is
2 oscillation rise (generally roomsec ~ I sec
degree) is not guaranteed. When XL2 of the display section is not oscillating, serial data communication with CPU10 is not received, and the clock φ shown in FIG. 7 is not generated, so the operation is as shown in the time chart shown in FIG. 26. LTCH pulse will not be generated unless Also, even if XL2 is oscillating, there is no communication of serial data, and the display circuit section 2
Do not rewrite data within 0. (PW in Figure 7
Since C, CS, 5DATA, and SCK do not come, BS7 does not occur, and the configuration is like L'l' (, II pulse does not occur), so in the above cptrto operation, This is not a good idea because the display content continues to be displayed indefinitely, indicating that the battery is installed. Therefore, as shown in Fig. 7 of this circuit, the jlO reset, jl 1 set, and the power-on reset circuit shown in Figs. 24 and 25 are used to reset the LCD.
One countermeasure is to prevent the initial indefinite display by turning off the driving power. Furthermore, if the power-on reset circuit does not work for some reason, or if it is not good for the light to remain off for a long time, serial data communication from CPU10 will continue until the guaranteed start-up time of XL2 after battery installation. As a result, as soon as the oscillation of XL2 starts, normal operation starts and the display contents change immediately. The contents of the serial data at this time may be data for turning off the light, data for standby display, or any other arbitrary data.

Therefore, the CPU operates by performing serial data communication using display data from the time it performs necessary processing immediately after the battery is installed until the guaranteed start-up time of the XL2 oscillation, and after a predetermined period of time, if necessary. All you have to do is come into a stopped state and stop the function by 4 degrees. However, the CPU 10 must prohibit interrupt operations during the guaranteed rise time of the XL2 oscillation.

- Before the CPUIO stops - Immediately before the CPUIO stops operating, the CPU 10 sends standby mode display data to the display. After that, until CPU10 is activated again, there is no data transfer, so the display remains unchanged and the standby mode display continues. Immediately before the main switch SM is turned off and the CPUI O stops operating, display data for the lights-out mode is sent from the CPUTO to the display in the same way as above. After that, there is no data transfer until the main switch SM is turned on again, so the display remains unchanged and the lights continue to go out.

-ALLON and ALLOFF- Norial data jlo and 01 are the highest priority data that completely turn off the LCD power supply.

The light is turned off when jlO−jll=“High”.

On the other hand, the data of 366 and j67 should be checked for wiring.
It was prepared for the 11th
This is second priority data. When j67="High", all segments light up, j66="Low"
”, a waveform in which all segments are turned off is output from the COM and SEG terminals. When each waveform is applied to a properly connected LCD, it will display whether all segments are turned on or all turned off. However, If the connection with the LCD is misaligned, a part of the LCD may turn off or turn on, or the brightness may be different from other segments, clearly indicating that the connection is abnormal.

Also, as a method of providing signals for serial data communication, 5DA
By connecting the TA line to →-E through a small resistor, that is, by pulling it up, all the Norial data becomes "High" information, the priority bit j67 comes alive, and the full lighting mode is activated. On the other hand, if you pull it down by connecting it to GND, all the serial data will become "1. ov@ information," and the priority bit, j66, will become active, and the mode will be all off. This is a check that can be done even after the camera is assembled, and is very important. This is an easy way to check.

Furthermore, there is no need to provide a dedicated terminal, which is ideal.

- Off mode and standby mode - Fig. 35 shows the display on the external display section 4 in standby mode. Only the bar is lit and all other external and internal displays are turned off. As the camera body, the CPU
l0 is in a stopped state and is waiting for an input corresponding to an interrupt instruction. Further, although power is supplied to the display circuit 20, no power is supplied to any other circuits (not shown) other than the CPU10. However, when an interrupt input such as a photometry switch is input to the CPU lO, power is supplied, other circuits also start working, and the camera function starts.

On the other hand, the display in the lights-out mode turns off all displays.

The method is to turn off the LCD drive power by 0FFV LC.
Set D to “Ilight”. At this time, the operation of the camera body is only in a stopped state where the CPU 10 is waiting for an input interrupt from the SM#a child, and no power is supplied to any other circuits except for the display circuit (not shown).

In standby mode and off mode, only the main switch SM is active in the camera's off mode. On the other hand, in the standby mode, an operation start switch such as a photometer switch (not shown) comes into play. In addition, the current consumption is lower in the off mode, which is energy saving, and the electrician's input to the liquid crystal is zero in the off mode, so the liquid crystal has a good shelf life.

- Manually configurable data indication marks - Figure 29 a, b
In the A mode, since the aperture can be set, the mark 4TA2 on the aperture value side is lit, and the dark mark TAIi on the shutter speed side, which cannot be set, is turned off.

Similarly, in the S mode, that is, the shutter priority mode shown in Fig. 30a and b, since the shutter speed can be set, one mark TAI on the negative side is lit, and the aperture value side, which cannot be set, is lit. The dark blue mark TA2 goes out.

In FIGS. 31a and 31b, in manual (M) mode, since both values can be set, both beak marks TA1. TA2
lights up to indicate that both can be set.

In the P mode shown in FIG. 28, there are no numerical values that can be set, so both marks are turned off to clearly indicate their meaning.

Note that these marks can be turned on or off using jt2. j73
Use the AE mode information as is to control it.

However, if a function (not shown) for determining the presence or absence of a lens determines that there is no lens, the aperture of the lens cannot be set. Therefore, in this case, the setting mark TA2 regarding the aperture is specially set not to light up regardless of the mode. This is controlled by the q40 signal shown in FIG.

1-Open F value display - The aperture value display is a 7-segment numerical display as shown in FIGS. 28 to 31. The contents of the aperture value are shown in FIG. Here, the rQ40J signal indicates a state equivalent to no lens by displaying -1. rq43J~rq62J is 0.5
This is the aperture value rounded up for each EV. On the other hand, lens open F
Values include numerical values such as 3, 5, and 45, which have traditionally been shallow. However, since these values are not multiplied by the aperture value of 0 and SEV, these values are treated as special and prepared as rq41J and rq42J signals. In this way, the result of calculation by CPU+O or the set aperture value is the aperture value (judgment is made by an unillustrated aperture signal), and furthermore, it is 3.5 or 4.5 in this embodiment. In some cases, instead of the normal display of 3.4 or 48, it is displayed as 3.5 or 4.
A display signal is given from CP[JlO to display 5 etc. Further, when the result of the calculation performed by the CPU 10 or the set aperture value is not the aperture value, the normal display such as 3.4 or 4°8 is used for display.

The display shadows of the above two series are made to have a needle.

As an example, FIGS. 33a and 33b show display examples of the open F value.

The open F value is determined, for example, as follows.

As shown in FIG. 40, in step S1 the WJC CPU
O is open from lens 3 F ii! Read A vo and store it in an internal register. On the other hand, CPU10 determines A'vo=Av in step S3 using the calculation F*Av calculated in step S2 based on the camera settings and the value obtained from the photometry result, and if Avo=AV, the open F value is determined. Step 54) 1. Avo
If fAv, round the calculated F value Av to every 0.5EV and extract it (step S5), data of J12 to j16 (
AvDSP) is determined, and the extracted output is displayed on the display units 4 and 6 (step S6).

- Display of metered manual amount for each override - Figure 31 +6,5 is the deviation amount of metered manual, and it is always lit in manual mode, which is the only internal display of the infinder. The displayed range is +6.5
~-6.5 EV (see Fig. 20), and when that amount is exceeded, ÷6.5 and -6.5 are displayed blinking. The data at the time of blinking is M'dMOVE11 of j61 data.
is set to "I-l-1i".

Also, +1,5 in Figure 33 is the override amount,
It always appears depending on the setting when in AE mode other than manual mode. Similarly, only the internal display of the infinder is displayed.

The range to be displayed is +4.0 to -4.0 EV (see Figure 20), and settings cannot be made beyond that range. Here, the override display is constantly flashing to distinguish it from the metered manual, and at the same time draws attention to the override setting.

On the external display, +/- symbols (OR+,
OR-, 0R8) lights up, but when in metered manual mode, the +/- symbol (OR+, 01N-) lights up.

0RS) is turned off and not displayed.

The data for each quantity of override and metered manual is received and received using the same register.
A separate identification signal is required.

This signal is provided by the 5IGN signal of j54 to j56 data.

Table 3 shows the relationship between the data contents of j54 to j56 and the output display state of deafness. This makes the portions j54 to j56 of FIGS. 21 to 23 easier to understand.

-5 and A mode display- The display mode is shown in FIGS. 29 and 30.

FIG. 29 shows the display in the A mode, and the A mode display section with an arrow pointing toward the display of the manually settable aperture value is lit. Figure 30 shows the display in S mode,
Light up the S mode display with an arrow pointing toward the manually settable seconds value display. By doing this, the meaning of the mode display and the meaning of the numerical display can be understood at a glance, making the mode display very easy to use.

FIG. 38 82b shows the display contents at the time of initial loading after mounting the film. During film blank feeding, which is the initial load period, the shutter speed is 1/4000 seconds and the aperture value is controlled at the minimum value (F22 in this case). At that time, all exposure mode displays have disappeared, but this means that the j75 bit is set to "High" to erase the mode display.

Figure 38 82. (Yo,, Zu wearing 7. When it's wa□
The display contents of 1. are shown. cput by a mechanism not shown.

If it detects that there is no lens, the display j12~
All 06 are set to Low@. This is done in step SI8 of the flowchart in FIG. 41, and the display decoder that receives this outputs the 440 signal in FIG.
Set 62 to “Low”. Therefore, Display-1 is displayed as the aperture value, and the aperture chain side mark TA2 of the settable marks disappears.

Note that FIG. 42 shows another embodiment in which camera shake is displayed on the internal display section 6. In this case, as shown in (a) in the figure, it is composed of three segments, and the type of camera is indicated by lighting two of these segments. This 2
There are two types of segment selection, (b) and (C), and camera shake is displayed by lighting these two types alternately.

An outline of the operation of the control CPU I O is shown in FIG.

When the battery is installed, the cputo starts operating from a reset start (step So). At the same time, voltage is also applied to the display circuit. First, in CPU10.

Perform initial settings for both cameras (step 510)
Then, display data, turn-off data, standby data, ISO data, etc. are sent n times to the display circuit (step 5ll). (n is a value determined according to the time it takes for the display circuit to guarantee normal operation) When the transmission is finished, interrupts from a switch group (not shown) are permitted (step S l
2). If there is nothing, the internal operation clock is stopped and the system enters a stopped state (step 5I3). Among the switch groups (not shown), the photometric switch SL or the initial load switch SR has a relationship with the main switch SM as shown in FIG. 44, and the other switch groups have the same configuration as the SL and SB. When the main switch SM is OFF, the Sl and S8 inputs are pulled down and are Sl.

S11 Jinriki is dead. In this situation, it is the SM times signal that generates the INTseL signal that generates the interrupt. Main switch SM, 6<ON and INTse
When the t signal is generated, an INT flip-flop (not shown) is set, and the CPU 10 enters an interrupt operation I NT (step 514). This INT flip-flop is set at the rising edge, and when one interrupt is enabled (step 512), the INT flip-flop is reset and waits for another interrupt.

Now, when INT (step 514) is entered, check the switch SB that detects the initial load state (step 515). If it is 0FF (not in the initial state), power is supplied to the photometry circuit (not shown), etc. From this, photometry is started in step 516. After that, in step SI7, AE
The calculation is performed, display data necessary for the display circuit is prepared, and sent out in step St8. Thereafter, the main switch SM is checked in step SI9, and if it is OFF, data for turning off the light is sent as display DATA in step S20, power supply is stopped, and photometry is stopped in step 521. After that, step S12. Proceed to S+3. Also, in step 519, main switch SMh (if ONL, check switch S1 (step S26) L, OFF
At step SI6., data for standby display is sent as display DATA. S21. S12. S13
Proceed to. If it is ON L in step 826, the release switch 52 is checked in step S22.

If it is ON, perform the νW output sub-control step 523),
The process proceeds to step S17, but if it is OFF, the process proceeds to step 517 and the AE calculation is performed again.

On the other hand, if the switch 5Bh detects the initial load state in step SI5 (if ON, the second value and aperture value for initial load and the MODE OFF information 5 data "High" are sent out in step S24. An initial load is performed to control the shutter mechanism using the second value and the aperture value (step 525).After that, the switch SB is checked again in step S15, and depending on the state of the switch SH, the photometry starts in step S16. enters.

As shown in FIG. 44, moving from step S13 to step S514 depends on the switches SM, St, and SB, but SMh<O
At the time of FF, the St and SB switches are in the "Low" state, and the switch signal is dead and is L1. L, rih<-
vz, 5M0ON1. : Against -C0 only IN
'T set signal is generated and interrupt (INT) operation begins. Also, when SM is ON, S
l, SB switch comes alive and I by Sl or SB
The NTset signal is generated and interrupt ([NT) operation begins.

Although not shown, the SB switch is turned on when it detects the presence of film and that the back lid is closed, and turned off when the film counter (not shown) turns into a fly.

FIG. 43 is a flowchart showing the operation for detecting camera shake. In step S31, the CPU 10 reads necessary information such as focal length from the lens. Then, in step S32, the exposure calculation Nyorinyatta vJ's TV
In addition to calculating the value, the camera shake warning limit TVLla is calculated from the lens information. Then, in step S33, T
The magnitudes of V and TV I are compared, and if TV<TVL, the process goes to step S34, and if TV>TVL, the process goes to step S35. In step S34, t,
With the owss signal set to “High”, Marri CAI, C
A2 is vibrated to issue a camera shake warning, and in step S35, the t, owss signal is set to "Low"? -ri CAI
, turn off CA2.

FIG. 44 shows CPU10 and switch S1. S2゜SB,S
Indicates the relationship with M.

Table 1 <Combinations of r2n and Be> 81 -r51 to r53. r61-r652-r54 B3-r55-r58. r67, r68B4-rl
-r29 B5 - r30~r43 B6 -r59. r60 B7 - r44~r50 88 -r66 Table 2 Table 2 (Continued) Table 2 (Continued) Effects of the Invention As detailed above, this invention allows two adjacent patterns to alternate when notifying camera shake. Since the pattern blinks, the pattern appears to be shaking, and you can intuitively visually detect camera shake.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing an example of a camera to which the present invention is applied, FIG. 2 a is a front view of the finder of the camera shown in FIG. 1, and FIG. FIG. 2C is a diagram showing an example of all the segments displayed on the internal display section of the display device of the present invention, and FIG. 3 is a block diagram showing an embodiment of the present invention. , Fig. 4 is a detailed circuit diagram of the oscillation divider section in Fig. 3, Fig. 5 is a detailed circuit diagram of the common driver in Fig. 3, and Fig. 6 is a detailed circuit diagram of the segment driver in Fig. 3. , Fig. 7 is a detailed circuit diagram of the data latch section in Fig. 3, and Fig. 8 is a detailed circuit diagram of the decoder section in Fig. 3.
(Schematic diagram; FIG. 9 is a detailed circuit diagram of the switch circuit SWI in FIG. 8; FIG. 10 is a circuit diagram showing details of symbols in the circuit; FIG. 11 is a detailed circuit diagram of the data conversion section; The figure is a detailed circuit diagram of the switch circuit SW2 in FIG.
Figures 14 and 15 are detailed circuit diagrams of the segment decoder in Figure 8, Figure 16a is a detailed circuit diagram of the output control section in Figure 8, and Figure 16 is the circuit in Figure 8. 17 to 20 are diagrams showing the relationship between human input signals and displays, and Figures 21 to 23 are detailed circuit diagrams of parts of
24 is a detailed circuit diagram of the voltage generation section of FIG. 3, FIGS. 25 to 27 are waveform diagrams of the main parts of the circuit of FIG. 3, and FIG. Figure a, Figures 28 to 34 a, Figures 34 and 35 are diagrams showing various aspects of display, Figure 36 is a diagram showing the relationship between signals and renostars, and Figures 37 a and b. , c, Fig. 38 a, b, Fig. 39
Diagram a. FIG. 40 is a flowchart of the CPU showing the display selection operation, and FIG. 41 is a diagram showing various aspects of display.
FIG. 42 is a flowchart showing the operation of the CPU shown in FIG. 42 is a diagram showing another aspect of hand shake display, FIG. FIG. 4... External display section, 6... Internal display section, lO...
CPU. 22...Data latch, 23...Decoder, 24...
・Segment driver, CA1. CA2 ・Mark for camera shake display, j21・
Shake warning signal. Patent Applicant: Minolta Camera Co., Ltd. Agent Patent Attorney: N. Yamashita and 2 others Figure 2 O Figure 2 - ISO Figure 2 C 1/Figure 28 (o) Pe-do 1/250 F5.6 AVE, Fe:,
::: C=, :E, Mouth pipe Fig. 29 (a) A"E-do (/250 F5.6 AVε1・J"sE, G public S, S mouth Fig. 30 (a) S-E-) '1/250 F5.6 AVE, Et
S:j@l:”':mouth, 1.(j Fig. 31 (0) M morph' 8” Fl, 4 5POT theta-+
6.5EV C0゛° Between the eyebrows + S, S section Fig. 32 (0) Ic + #, -I Fig. 33 (a) PROGRAM = 1 r4 n It L 1. e II j, f , F, r:, aE, s-, t IJ yu s-, +2.
@-, B Fig. 34 (a) Fig. 34 (b) l j"f 1-1 j -1-1 Fig. 35 Fig. 36 Fig. 37 C PROGRAM Fig. 37 0 JLJ W" in CAI, 8 Figure 37 b CA2 i Figure 38 0 '1Ll (JIJ IF (' Figure 39 G; z5, - Figure 40 Figure 41 Figure 42 (a) (b) (C) Figure 43Figure 44

Claims (1)

[Claims] (1) A display means provided in the camera that displays at least two display patterns of approximately the same shape side by side, and a warning signal generation means that emits a warning signal when the speed is low; the two display patterns are alternately displayed by the warning signal. 1. A display device for a camera, comprising: display control means that lights up.