JPS61141431A - Display device of camera non-interlocked to photometry - Google Patents

Abstract

PURPOSE:To display distinctly the discrimination of whether interlocking to photometry or interlocking to control by flickering a photometry mode mark when the luminance exceeding the range of interlocking to photometry of the camera is measured. CONSTITUTION:The signal for warning the out of the interlocking to the control of a data latch part 22 existing in a display circuit part 20 rises to a 'High' and the warning is given by the flockering of the numeric value on the calculation control value side of the paerture value and/or second time value according to an AE mode when such as exposure value at which the aperture value or second time value controllable by the camera is required. The signal for warning the out of the interlocking to luminance rises to the 'High' and the warning is given by the flockering of AS1 and AS2 in the display of a photometry mode display at such a luminance value at which the luminance value measurable by the camera is exceeded.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION This invention relates to a display device that indicates that the photometry is outside the interlocking range.

PRIOR ART Conventionally, there is no known technique for displaying a clear distinction between the case where the subject brightness exceeds the photometry interlocking range of the camera and the case where it is outside the control/interlocking range.

It is known that an override display means is provided and the display state of the display means is changed when the subject brightness exceeds the photometry interlocking range of the camera. In this case, it was difficult to understand which state the display means was displaying.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a display device that can clearly display areas outside the photometry interlocking range.

Structure of the Invention The present invention includes a display means for displaying a mark representing a photometry mode, a means for detecting that the photometry interlocking range is exceeded, and a display control means for changing the display state of the display means based on a detection signal from the detection means. A special embodiment characterized by For example, a device is provided that outputs data indicating the open aperture value, etc., to the camera body as an electrical signal. Further, the shutter button 2 is provided with a photometric switch S+ and a release switch s2, which operate according to the amount of depression of the button, by a known method.

Reference numeral 4 denotes an external display section, which displays the calculated EV value and operation mode, as well as various other data that will be described in detail later.

5 is a finder, and within the field of view of this finder 5 is provided an internal display section 6 (see FIG. 2) for displaying data and the like displayed on the external display section 4.

SM is the main switch.

FIG. 2 shows details of the display on the external display section 4, and from the top there are PROGRAMS for displaying the AE mode. When the AE mode is program mode (hereinafter referred to as P mode), PROGRAM is displayed and S is turned off, and when the AE mode is in aperture priority mode (hereinafter referred to as A mode), A is displayed and PROGRAM is displayed.
Turn off R and MS. M and S are displayed in the manual mode (hereinafter referred to as M mode) and in the shutter speed priority mode (hereinafter referred to as S mode), respectively. Below that is the ■SO mark in SOS-mode, and immediately below there is a 7-segment, 4-digit SS, ISO, and CTH display.
To the right of it is a setting instruction mark TAI. Below that, there is a bar display that only turns off when the camera's main switch SM is turned off, and a 7-segment, 2-digit F, +/- display, and to the right of it is a setting display. There is an instruction mark TA2. To the left of the two digits is an aperture value discrimination mark F, and further to the left end is a +/- mark, which is a sign when setting an override.

Furthermore, FIG. 2C shows details of the display on the internal display section 6.
Starting from the left end, there are 2 adjacent images for displaying camera shake (camera shake).
Mark CAI has two camera shapes.

There is CA2, followed by 7 segment 4 digit SS,
) ISO, C'! 'H display section, followed by S, P, and A for AE mode display. S
The mark is made up of a 7-segment arrow pointing toward the 4-digit side to indicate shutter speed priority, and similarly, the A mark is made up of a 7-segment arrow pointing toward the 2-digit side immediately to the right to indicate aperture priority. . The P mark has nothing to do with prioritizing both aperture and seconds, so there is no arrow between S and A. A
The 7 segment 2 digits on the right side for E mode display display the F value and the +/- value in +/- mode. Immediately to the right is the M mark for AE mode display. This is because the metered manual display lights up at the same time, so it is displayed near the meter display to make it easier to understand.

To the right are the override and metered manual symbols, tens and -, followed by a seven-segment numerical band. This numerical value band displays +/- values during AE mode (P, A.

(Only in S mode) and also displays the metered manual value in <AE mode (Only in M mode).

Finally, there are the ASI and AS2 marks that indicate the metering mode. During average metering, only ASI lights up, and during partial metering,
Both ASI and AS2 are lit.

Figure 32 a, b and Figure 33 a, b are showing overrides, but in the internal display of the finder, the place where the override value is displayed is the override (+/-
) mode and AE mode. This is an attempt to display information near the center of the display section during override mode display to make it easier to understand.

FIG. 3 shows the overall configuration of the control device related to the above-mentioned camera display. The CPU10, which uses a central control microcomputer that controls the operation of the entire camera, is supplied with a power supply element E from a battery 11, a main switch SM pulled up by a resistor R, a reference oscillator XL1 for operating the CPU10, and peripheral circuits. A group of control signals (especially regarding display).

cs, pwc, serial data 5DATA necessary for norial data transfer, and serial clock SCK are connected to the peripherals.

An outline of the operation of CPU10 will be described later.

On the other hand, the display circuit section 20 receives the power supply element E from the battery 11, the main switch SM, and the signals ■, doqσ, and 5 from the CPU10.
DATA, SCK, reference oscillator XL2. A reference power source 2I for driving the liquid crystal is input, and outputs include a group of driving outputs for common and segment electrodes of the external display section 4 and internal display section 6 using a liquid crystal display. The drive output terminal group is connected to the external display section 4 of the camera and the external display section 6 inside the finder, which are connected in parallel.

Inside the display circuit 20, there is a data latch section 22 that latches serial data. Decoder section 23 that decodes the latched data. Segment driver unit 2 that drives the LCDs of external and internal display units 4 and 6 using decoded signals
4. Common driver section 25 that drives the common section of the LCD
．． Oscillation frequency dividing section 26 that creates operating clocks for each section. L.C.
There is also a voltage generating section 27 that generates a driving voltage of D.

FIG. 4 is a detailed diagram of the oscillation frequency dividing section 26 shown in FIG.
I). The flip-flop FFI is provided with a reset terminal R so that it can be initialized by installing a battery.

FIG. 5 is a detailed diagram of the common driver section 25.
, VLCD2. Each voltage of VDD is connected to analog switch A.
It is configured to output to COMI and C0M2 at timings of φ, , φ16 through SI to AS4 and PchFETs FPI and FP2. Nantes Gate NAI, 2. NOR gates NR1, NR2 and inverter IN3.4 are gates for creating timing, respectively.

FIG. 6 is a part of a detailed diagram of the segment driver section 24,
VLCD2. Segment data S2n, 52n- of the timings of φ1o, which are processed by flip-flop FF2, are analog switch AS5 and PchFET EP3 that switch each voltage of VDD.
It is configured to be driven according to the state of No. 1. Nando game) NA3 to NA7 and inverter IN6.7 are 62n
, S20-1 constitutes a clock selector, and an inverter ■N5. Flip-flop FF2 is φ,,φ,
. A clock generator is configured to create clocks with four types of phase differences.

The entire segment driver section is of the type shown in FIG. 6, in which the clock selector, analog switch, and PchFET are provided except for the SEG output terminal, and a clock generator is added.

FIG. 7 is a detailed diagram of the data latch unit 22. There are seven 8-bit shift registers 5RI-SR7 that receive serial data 5DATA from CPolo, and the parallel outputs of these shift registers are latched at the falling edge of the LTCH signal. Seven 8-bit latches LTI to LT7
is connected to.

A reset R input is applied to the JIG data of the latch LTI, a set S input is applied to the jII data, and the power-on reset F is applied to the j0 data and j11 data, respectively.
It is reset and set by the OR signal. Therefore, the initial state is jlQ=“Low”, jl l =@)I
It is igh@.

On the other hand, the serial register SCK from the outside sends the φ$ scratch signal that passed through the OR gate ORI to the NOR gates NR3 to NR.
9, and also serves as the φλ power of the counter decoder CD. When the set human power S of the counter decoder CD is “High”, the output BSI of the counter decoder CD
~BS7 are all “High” and S input is “Low”
``, every 8 pulses of the φλ force sequentially goes from BSI to BS7 to Low''.

When any one of BSI to BS7 is “Low@”,
One of the corresponding NOR gates NR3 to NR9 becomes active, and the φ8 signal, which is the input of the NOR gate, is sent to one of the serial registers 5RI-5R7.
Enter the λ force. External control signal vWτ from CPU1O
, τ are logically summed by the OR gate OR3 to form a p-cs multiplied signal, which is input to the other input of the OR gate ORI and the S input of the counter decoder. Also, it becomes one input of OR gate OR2, and the other input BS7
An OR logic is performed with these, and this becomes the D input of the flip-flop FF3 and one input of the Nandt gate NA8. In the flip-flop FF3, the FOR signal is input to the set input S, and the ζ output is connected to the other input of NA8. or,
A small output φ in FIG. 4 is connected to the φλ force of the flip-flop FF3.

FIG. 8 is a detailed block diagram of the decoder section 23 of FIG. 3, and is a detailed block diagram of the switch circuit SW1. SW2. Data converter DCI-DC
4. Segment decoder sections SDI to SD6. It is composed of an output control section CTL1. The switch circuit SW+ has outputs 02-j of the decoder 22 as inputs.
16. j22-j27, j32-j37. j40～
The data converter DC3 receives the outputs of the decoder 22 as inputs, and the data converter DC4 receives the outputs of the decoder 22 (jlo, jl 1゜co2).
0. j21. j54-j57. j60～
j67゜24 pieces from j70 to j77, a total of 53 pieces, are the 7th
It is connected to the output of latch LTI-LT7 in the figure. or,
Two signals SM and PWCO from the main switch shown in FIG. 3 are input to the data converter DC4. From FIG. 4, the output controller section CTLl has φ1. are connected as inputs, and 70 outputs, 81 to S70, are connected to the segment driver section 24.

FIG. 9 is a detailed diagram of the switch circuit SW+ in FIG. 8,
jn from data latch 22 (n = 12 to 47 (excluding 17, 20, 21, 30.31)) - Pn
(25 signals to 25 NAND games) NA
For use with FOM, CTR, ISO.

It is switched by the SS signal. FON, CTR.

When the ISO and SS signals are low, the Pn signal goes high and the jn signal is cut off, but the FON signal goes high.

2” when CTR, ISO, and SS signals are “High”
=5"(!: tt')・X4yfM), °t""1
“6.1 Figure 1O is a diagram explaining the symbols used in Figure 1+, Figures 13 to 15, and Figure 23.
,B,C.

For each human power of D, the same function as the Nantes gate is indicated by placing an O mark at the intersection of the arrow with the output Q. That is, Q
= 100 τ1-.

FIG. 11 is a detailed diagram of the data conversion unit DC3 in FIG.
The logic of outputs pi to p9 is shown for inputs j50 to j53. This output is powered by the switch circuit SW2 in FIG.

FIG. 12 is a detailed diagram of the switch circuit SW2 of FIG. 8, in which human power p1 to p9 are used to switch q71-q78 . It represents the logic switched to q82 to q89. When the input p signal is input to the Nant gate and the switching signal MON and +/-ON signal are "Low", the output q signal becomes "HIgh" and the p signal is cut off. M
When the ON and +/-ON signals are high, the output q signal becomes equal to the input p signal, and the switch is turned on.

Figure 13 shows the segment decoder section 5DI-8D in Figure 8.
In the detailed diagram of 4, outputs r1 to r2 for inputs q1 to Q39.
It shows the logic of 9. This figure shows segment decoder section S.
Since the basic configurations of DI to SD4 are the same, they are shown in the same drawing, but the necessary parts of 5DI to SD4 are extracted from this drawing. This output is an input to the output control section CTLI shown in FIG.

FIG. 14 is a detailed diagram of the data converter DC2 of FIG. 8, showing the logic of outputs q40-462 for inputs p12-p16. This output is from the segment decoder SD in Figure 8.
5 input.

FIG. 15 is a detailed diagram of the segment decoder section SD5 in FIG. 8, in which manual power q40 to q62. For q71-q7B, the logic of outputs r30 to r43 is shown. This output is an input to the output control section CTL shown in FIG.

FIG. 16a is a part of a detailed diagram of the output control section CTL1 of FIG. 8, in which an output of 5l-370 is obtained by the outputs of the segment decoders SD1 to SD6 and the data conversion section DC4 and the clock φ14.

In this figure, r2n and Bs are shown in arbitrary combinations, but in reality they are connected in the combinations shown in Table 1.

Table 1 shows a truth table by replacing the circuit diagram of FIG. 16a with logical expressions. Furthermore, a combination of r2n and B- is specifically shown. (1≦■≦8).

(1≦21≦68) r69 is shown in FIG.

FIG. 16 shows input r69 and output s69. It shows the logic to s70.

FIG. 17 shows the relationship between the outputs q1 to q39 of the data conversion unit Del of the decoder unit 23 and the characters displayed on the display units 4 and 6, and the relationship between the inputs p22 to p to the data conversion unit DCl.
27. p32 to p37, B40 to p47.0 When q1 to q39 are output according to the state of TR, ql to q3
The displayed characters are controlled according to the "Low" or "HIgh" state of 9.

That is, if the output qt is "High", the SDI is displayed, and therefore, if the IO2 digit of the display section 4 (and 6) is "High", the display of the 10 DEG digit is 2. For the Nyatta speed SS value, see p22 to p27, I
Data is given in 932 to p37 for the SO value, and p40 to p47 and the CTR signal for the CTR value. Also, p22~p27゜p32~p37, B40~p
47 are all "High", the configuration is such that no output is produced for that data. Therefore, for example, when the data of p22 to p27 for the Shabuta speed SS value is displayed, other data of p32 to p37. p40～
It is composed of a data conversion IDC4 and a switch circuit SWI so that p47 are all set to 'High'. (See Figures 9 and 21) The contents that can be displayed are illustrated in Figure 18, and regarding the SS value. There are 36 types of ISO values, 31 types of ISO values, and 100 types of CTR values.

19 and 20 are diagrams showing the relationship between the data of the data conversion unit DC2 and the switch circuit SW2 and the characters displayed on the display units 4 and 6.
p12-p16 and SW2 pl-p9・MON・+
/-Depending on the ON status!
Q40-q62. q71-q7 g, q82-q
The output of 89 outputs data as shown in this figure. Data is given at p12 to p16 for the F value, and p1 to p9 for the override value and metered manual value.

FIG. 21 is a part of a detailed diagram of the data converter DC4 of FIG. 8, and shows switch switching signals MON, +/-ON, and FON of switch circuits SW1 and SW2.

CTR, ISO, SS logic and CTLI section ON,
The logic of the OFF signal and the logic of the 0FFVLCD signal applied to the voltage generator 27 in FIG. 3 are shown, respectively. The input signal is the output signal 10. of the data latch section. jl 1.
j55. j56. j60～ j67゜j70
．． J71, foreign fi1148, SM, PWC.

FIG. 22 is a part of a detailed diagram of the data converter DC4 of FIG. 8, and shows the logic of the B1-B8 signals of the CTL1 section.

The input signal is the output signal j20. of the data latch section. j
55~js7. jat-js4゜j70 to core 4 and external signal PWC.

FIG. 23 is a part of a detailed diagram of the data conversion section DC4 of FIG. 8, and shows the logic of the r51 to r69 signals of the control section CTLI. The input signal is the output signal j of the data latch section
21. j54～j57゜jγ0～j73. j75～j7
7 and 002 section output signal q40. and external signal pwc
It is. In FIGS. 21 to 23, the data conversion section D in FIG.
Contains all C4.

FIG. 24 is a detailed diagram of the voltage generating section 27. Create a reference voltage VLCD by externally connecting a diode DI and a resistor R1 between +E and GND, and connect a capacitor C+.

By supplying the voltage to the booster circuit 27a (the part surrounded by the broken line) including C2, the voltage doubled (+E-VLCD) (10E-
V LCDI). Both V LCD and V LCDI are led to V LCD0 and V LCD2, respectively, by an output control circuit made of an analog switch and a PchFET.

V LCD0 and V LCD2 change their outputs depending on the state of 0FFVLCD. OF F V LCD is °L
ow”, VLCDO=VLCD, VLCD2
= VLCD1, 0FFVLCD “High”
(f) At the time, V LCD0 = V LCD2 =
It becomes VDD.

Further, the booster circuit section 27a obtains a clock from φ in FIG. 8 to switch the connection of the capacitors 〇+ and Cm to boost the voltage. Further, FOR is a terminal for starting the booster circuit, and the booster circuit is started by the FOR output shown in FIG.

FIG. 26 is a time chart of the data latch section 22 of FIG. 7. External signals pwc and ① both become “Low”, and serial register 5RI-8 is activated at the falling edge of SCK.
The data in R7 will be rewritten.

The contents of SRI are all rewritten at the falling edge of the first 8th pulse of SCK, and from the 9th pulse onwards, they are rewritten every 8 pulses in order from shift renostars SR2 to SR7. Immediately after SR6 is rewritten, BS7 becomes 'Low' at the rising edge of the 49th pulse, and at the same time as the rewriting of SR7 begins, flip-flop FF3 reads the D input at the rising edge of φ□, so the σ output of FF3 is changed. is “Lo
w" and does not change until BS7 becomes "High" again.

The LTCH pulse is created by the 1 output and the p-cs signal, and the contents of the 5RI-SR7 serial register are transferred to the LTI
-It will be taken into the latch of LT7.

FIG. 25 is a time chart showing the overall general operation from after the battery is installed in the camera. Immediately after the battery is installed, the display circuit section 20 is initialized by the FOR signal. Signal VLC
DI becomes earth GND level and 0FFVLCD becomes “
It becomes H4gh'. Therefore, no voltage is applied to the liquid crystal. After that, the CPU IOXL1 starts oscillating, and the CPUIO starts operating. After a while, the oscillator XL2 of the display circuit section 20 starts oscillating, and the clock φ is generated.

~φ, 4 starts to start. When the clock φ starts operating, the data latch section 22 starts operating, and when the norial data comes from the CPU 10, it operates as shown in FIG. 26. When the clock φ starts operating, the voltage generating section 27 shown in FIG. 24 starts operating, and after a short period of time, the potential of the signal VLCDI becomes stable. After that, use 0FFVLCD as necessary.
If you set it to “Low”, the LCD drive voltage・V LCD0・
V LCD2 to display parts 4 and 6
1 is supplied.

28 to 35 and 37 to 39 show various display modes of the external display section 4 and the internal display section 6, and except for FIG. The figure shows the display on the internal display section 6.

Figures 28a and 28b are AE displays in program mode, showing auto second time 1/250, auto aperture value 5°6, program PROGRAM, and reverse width.

The mark ASI at the right end of FIG. 28 indicates the photometry mode and indicates average photometry.

Figures 29a and 29b show the AE display in aperture priority mode, where the aperture setting mark indicates the set aperture value of 5.6 and the auto second time of 1/250, and the aperture priority A and D represent the AE mode. .

FIGS. 30a and 30b are AE displays in the shutter speed priority mode. When the shutter speed setting mark is turned on, the set shutter speed value is 1/250 and the auto aperture value is 5.6 degrees, and the shutter speed priority is indicated by S and AE mode.

FIGS. 31a and 31b are AE displays in manual mode.

The setting mark for the shutter speed and aperture value indicates the set shutter speed value 8" and the set aperture value 14, and the manual mode M and mouth indicate the AE mode. The right end of the internal display is the partial metering mark for the metering mode. The left side is the error amount of the manual setting value with respect to the appropriate value, which is the so-called metered manual indication value, +6.5EV
This indicates that there is a difference in indication. Further, the mark on the left end is a mark indicating a camera shake (hand shake) warning, and the two marks are lit alternately.

FIGS. 32a and 32b are displays during override setting. Override direction and absolute amount! , represents 5EV.

FIGS. 33a and 33b are AE momo displays after override setting. Compared to FIG. 28, an override direction + has been added. The internal display also displays the absolute override amount of 1.5 EV. However, +1.5 is blinking on the internal display.

FIGS. 34a and 34b are displays during ISO setting.

The ISO mark and ISO value 100 are displayed.

However, the ISO mark does not light up on the internal display.

37a and 37b are camera shake (camera shake) warning displays. On the internal display section 6, the leftmost camera mark CA
1. CA2 lights up alternately to indicate movement.

FIG. 37C shows the display on the external display section 4.

FIG. 35 is a display in standby mode.

Only the bar display was dimmed, and all other lights were off. Functions other than camera display are in a stopped state.

<Operation Description> - Overall Operation - The basic operation of the display circuit section 20 will be explained. When the DC voltage +E is supplied from the power supply 11, the momentary F generated by the power-on reset circuit 40 (right end in Figure 4)
The OR signal causes the flip-flop FFI of the frequency division stage (FIG. 4), the flip-flop FF2 of the clock generator of the segment driver section 24 (FIG. 6), and the flip-flop FF3 of the data latch circuit 23 to be activated. Latch LT
I (Fig. 7), starting FET 27b of the voltage generating section 27 (
(Fig. 24) are each set to the initial state. Latch LTl
Then set each data terminal to j10="Low".

Set jr + = 'High'. flip flop F
FI.

In FF2, set the output state to Q = “Low” - = “High”
Set the output state to Q="High" in FF3.
”.

Set σ1 to “Low”. In the voltage generation section 27, FET
By turning on 27b for a moment, capacitor C! is charged with electric charge, and the level of VLCDI becomes the GND level. In this state, since the crystal oscillator XL2 of the oscillator 41 (Fig. 4) has not started oscillating, there is no circuit operation at all, and the oscillation rise of XL2 ( Waiting for the oscillation rise of =φ. In one direction, VDD, VLD2. V
Although the LDO is given in an undefined state, (COMI is VLCD2°C0M2 is VLCDO, 5EGn is S2
VDD or V LCD2 depending on the state of n, 52n-1
) 0FFVLCD input to the voltage generator 27 is jlo
= "Lov", j11 = "High" initial settings, AND gate A50° inverter I50. or gate 0
V LCD2 = V LCD0 by the switch circuit of FIG.
= V DD, and the voltages applied to each terminal of the LCD display on the inner and outer mounting portions 4.6 are equal, and there is no DC voltage application condition that is harmful to the liquid crystal.

Next, the crystal oscillator XL2 starts oscillating and φ. When a clock enters the flip-flop FFI in the frequency dividing stage, all parts start operating at the same time.

The clock φ enters the flip-flop FF3 of the data latch section 22 and serves as a serial signal from the CPU10.

The clock φ enters the booster circuit of the voltage generator 27, and Ct
, Ct is switched to perform boost operation.

Clock φ8. φ1o enters the common driver section 25 and segment driver section 24 and becomes a clock for the liquid crystal drive waveform.

The clock φ, 4 is input to the output control unit CTLI of the decoder unit 23 and is used to control the blinking state of the display contents.

The operation after the rise of the oscillation of the crystal oscillator XL2 will be explained first with respect to the voltage generating section 27.The clock φ6 inputted to the booster circuit 27a in FIG. 24 starts the boosting operation, and the initial VLCD
What was the ILCD display level (V DD-2V
LCD) level and stabilize it. From then on,
It continues to work without interruption until the power supply voltage drops and it stops operating, or the oscillation circuit stops, causing the lifting and lowering operation to stop. On the other hand, the data latch circuit 22 which starts operating with the clock φ causes the terminals jlo and j11 to become "L".
ov”.

At the moment when a signal other than "High" is input and latched, OF
= VLCDl, VLCDO = VLCD Wait for output. These are common drivers 25. The voltage is guided by the segment driver 24 and applied to the LCD display of the inner and outer display sections 4.6 as a voltage for driving the liquid crystal, and a liquid crystal display is performed based on the latched data.

Next, the data latch section 22 will be explained with reference to FIG. 26. This circuit starts operating when both the PWC and (2) signals become "Low". PWC is, for example, a timing signal for supplying power to a photometry circuit of a camera (not shown), and is V7.
The photometry circuit starts operating when τ=“Low”. Also, ■ is a signal that determines the other party for serial data communication, and is also used for other circuits in the camera (not shown).
One for each comes out from Ul0. v”=”L
ow” selects the other party for serial data communication.

pwc, τ100) When either is “High”, P・C
8 signal is “High”, the counter decoder CD is set, and all BSI to BS7 outputs are “High”.
It is said that Also, the output φS of the OR gate ORI is “H”.
The output LTCH of the Nant gate NA8 is also “High”. Both pwc and τ
At the time of "v", the counter decoder CD enters the operating state, and the OR gate ORI and OR gate OR2 open and the SC
The signals of K and BS7 become detectable. At the rising edge when the first pulse of SCK is input, BSI goes to °L ov" and NOR gate NR3 opens. At the falling edge of the first pulse, the φ input of the not register SRI rises, so 5DAT at that time
The contents of A are taken into only one shift register S Rl b4. The data at this time is jlO. Then a second pulse comes and the same operation is repeated. At the falling edge of the 8th pulse,
Eight pieces of data are taken into the shift register SRI, and the eighth data is called j17. Until this time, the signal BSI is "Low".

When the next ninth pulse rises, BSI becomes "High", BS2 becomes "LO low", NOR gate NR3 closes, and NOR gate NR4 opens. Since the φ input of shift register SR2 rises at the fall of the 9th pulse, 5DATA at that time
The shift register SR2 takes in only one content. The data at this time is j20 and 9′・lu*IJ[l: “1”
Pa“X[l7)tlQ.

Then, BS6 becomes "H4gh", BS7 becomes "Low", Noah Gate NR8 closes, and Noah Gate NR9 opens. Further, the output of the OR gate OR2 becomes "Low".

The contents of the shift register SR7 are taken in from j70 to j77 up to the 56th pulse, but the LTCH output remains "High" from the first pulse until the 56th pulse, and the data is transferred from each shift register SR to the latch LT. Data is not taken in. The output of OR gate OR2 becomes "Low" due to OR gate OR2 opening at exactly the 49th pulse, but with the rise of clock φ!, 7-lip flop FF3 takes in "°Low" of 0 manual power. 1 output becomes "High". However, the other input of Nant gate NA8 becomes "Low" before the ζ output changes, so the TCH output becomes "High".
h" is maintained.

Here, the output of the OR gate OR2 becomes "High" depending on whether the 57th pulse comes or whether pwc or cs becomes "High".At this moment, the output of the OR gate OR2 becomes "High".
Since the C output of the flip-flop FF3, which is the other input, is also "High", the output LTCH of the Nant gate NA8 becomes "Low". This “High”→“
The falling edge of "Low" is a latch signal, and the data stored in shift registers SRI to SR7 at 1 o'clock is latched to L.
It is latched into the data memory of TI-LT7. After that, with the rise of the clock φ, the flip-flop FF3 takes in the "old gh" of the D input, and the 1 output becomes "LO", and the counter decoder CD is set to "High" of either pwc or cso, Each returns to its initial state.

The above is an overview of the operation of the data latch. Here, if the number of clock bytes for serial data communication is insufficient, the last latch pulse LTCH will not be output, so no data abnormality will occur, and if the number of clock bytes exceeds 5.
It is automatically turned off at the 7th pulse, and naturally no abnormality occurs.

Further, since the clock within the same byte is processed so as not to be interrupted on the sending CPU side, it is completely prevented from abnormalities in data communication.

On the other hand, even if the external signals PWC, C8, SCK, and 5DATA operate normally, if the internal φ is not operating, the
TCH pulse is no longer output and shift register 5RI-
The data taken into SR7 cannot be latched into latches LTI to LT7. This means that if it is considered that the liquid crystal drive waveform does not operate when φ is not operating, a DC voltage will be applied to the liquid crystal. Therefore, at that time, jl O=”Lov”, j 11=”Hi
gh” and set 0FFVLCD=“High” so that no voltage is applied to the liquid crystal.

Therefore, when the clock φ is not operating, external data is not taken in.

Next, the common driver section 25 and the segment driver section 2
I will explain about 4.

In Figures 5, 6, and 27, Nant Gate N
AI, NA2. Analog switch ASI-AS4゜Pch FET FPI, F by a gate circuit consisting of NOR gate NRI, NR2, and inverter TN3.1N4.
Controls each switch of P2. The input signals of the gate circuit are φ,, φ1°, and due to this timing, C0M2
．． The outputs of COMI change as shown in FIG. 27.

Signals C0M2 and COMI are clocks φ,. The period is the same as that of , and there is a shift of 1/4 period from each other.

The output value has three levels: VDD, VLCD0, and VLCD2.

In FIG. 6, four types of clocks generated by a clock φ processed by a clock generator composed of an inverter INS and a flipflop FF2, and a clock φ1° are selected by a clock selector composed of Nant gates NA3 to NA7. The selection conditions are S2n,
52n-1, and by this condition, 5E
The output waveform of Gn is determined.

This state is shown in FIG. 27, and each state is different depending on four types of states determined by S2++ and 52n-1. The periodic beam a ts φ,. are the same as and each other is l/4
There is a difference of four Ff periods. The output value is VD
It has two levels: D, VL, and CD2. Signal C
0M1.2 and segment signal S E G n
, the potential difference with i is 2 X V
The LCD display lights up depending on the waveform of the portion that becomes LCD2. 5EGn (LH), 5EGn for COMI
The segment of the LCD display to which the voltage of (HH) is applied lights up, and 5EGn (HL) for C0M2
, 5EGn (HH), the segment of the LCD display to which the voltages of 5EGn (HH) are applied lights up. 5EGn(LL) is C
The segment will no longer light up for OMI and C0M2 as well.

In other words, the 52n-1 signal is a signal that controls lighting of the segment for COMI, and 52n-1="Lov'"
When , it is OFF, when 52n-1 = 'High', it is ON
become. The S2n signal is a signal that controls the lighting of the segment for C0M2, and is OFF when 52n="Low".
, 52n = “High”, it is turned ON.

Data latched in Figure 7 jlO~07゜ko20~
j27. j30~ j37. j40- j47゜j50~ Ko57. j60~ j67,. 70～
j77 is 07. j30. All bits except 3 bits of j31 are input to the decoder section shown in FIG. SWI.

SW2. DCI-DC4, 5DI-SD6 are simply gate circuits and have no timing relationship at all.

The explanation is below.

First, the contents of the serial data will be explained.

jt o, jt t are signals that control the supply of liquid crystal drive voltage, jlO=“Low”, jl 1=-
Only when the voltage is "High", the liquid crystal drive voltage stops and the voltage applied to the liquid crystal becomes zero.

02 to 06 are data signals regarding the aperture value of the camera (9th
(see Figures 14, 15, and 20), and 23
There are different types. Further, when all of j12 to j16 are "High", nothing is displayed.

j20 is a signal related to a warning of insufficient battery voltage in the camera (see Figure 22), and j20="High"
All the displays displayed at this time repeat blinking at a period determined by φ, 4.

j21 is a hand shake (camera shake) warning signal (see FIG. 23), which becomes "High" when the shutter speed becomes slower than near the limit that causes hand shake (camera shake).

At this time, the camera shake mark CA1 on the internal display IIB6 in the viewfinder. CA2 lights up alternately.

j22 to j27 are data signals (
(see Figures 9, 13, 17, and 18),
There are 36 types. Also, j22 to j27 are all “High”
”, nothing is displayed.

j32 to j37 are data signals related to the ISO value of film sensitivity (FIGS. 9, 13, and 17).

(see Figure 18), and there are 31 types. Also, j32~j
When all 37 are "H4gh", nothing is displayed.

j40 to j47 are data signals (
(see Figures 9, 13, 17, and 18),
There are 100 types from 0 to 99.

Further, when all of j40 to j47 are "High@", nothing is displayed.

j50 to j53 are data signals regarding the override value and the metered manual deviation amount (see Figures 1+, 12, and 19.20), and depending on the content to be displayed, the 9 types of override values and the metered manual The 14 types of deviation amount values in the manual are switched and sent from the CPU. When all of j50 to j53 are "High", nothing is displayed. For switching the display contents, please refer to j5.
5. The receiver has the j56 signal (described later).

j54 to j56 are 5IGN signals (see Figures 21, 22, and 23) related to the override value, the sign of the metered manual deviation amount, and signal switching, and j54 is "+" and " −” Signal related to the sign, j
55 and j56 are signals for switching data between the override value and the metered manual deviation amount for each external display and internal display.

j57 is a signal used to display the so-called preview moment (see Figures 22 and 23), which is used to check the depth of field by narrowing down the lens aperture before shooting. The signal becomes "High", the aperture mark F on the external display section 4 blinks, and the set number chain belt indication mark TAI.

TA2f7) Perform baro lighting control4.
1'j60 is the ISO display priority signal I5OPR+. This is main switch S
M is OFF and the OFF V LCD signal is “H”.
Even if the LCD drive voltage is stopped,
When this signal becomes "High", the liquid crystal drive voltage increases to the segment driver 24. The 0FFV LCD signal is set to “Low” so that it is supplied to the common driver 25. (Refer to Figure 21) This signal is not used alone, but the tSO display mode and ISO value data are sent to the CPU 1 at the same time as this signal.
Sent from O. In terms of camera operation, this is the situation immediately after the battery is installed.

Is j61 metered? = A blinking signal of the deviation amount of Yual M'dMOVEH (see Figure 22), and this signal is “H”.
igh", the deviation value of the metered manual flashes.

” 62 is a shift signal 5HIF for blinking the program mode mark during the shift of the camera program mode.
T (see Figure 22), and this mark flashes when the j62 is set to 'High'. Here, shift means changing the combination of aperture value and time value in program mode. This refers to the state in which the AE mode is operated.Flashing can be performed in all AE modes, regardless of the program mode, if necessary.

Colo 3 outputs the control interlocked warning signal Not, C0NT (22nd
(see figure), and this signal goes “High” when an exposure value that exceeds the aperture value and second value that the camera can control is required.
h", and the aperture value and/or second value flashes on the calculation control value side depending on the AE mode to issue a warning.

j64 is a brightness-linked warning signal BV (see Figure 22), and this signal becomes "High" when the brightness value exceeds the brightness value that the camera can measure, and the ASI and AS2 during the metering mode display. flashes to warn you.

j65 is the bulb time signal BULB (see Figure 21), which is a signal that switches the 4-digit 7-segment display content from the bulb exposure seconds display (buLb) to the bulb exposure seconds count display during the camera's bulb exposure. "The valve count will be displayed and the contents of 340 to j47 will be displayed.

Reference numeral 166 is an all-lights-off signal ALLOFF (see Figure 21), which controls the waveform of the driving SEG terminal so that it becomes an OFF waveform (see Figure 27, 5EGn (LL)). will be displayed. However, camera marks CAI and CA2 cannot be controlled.

j6711 all lighting signal ALLON (see Figure 21), which turns all the waveforms of the drive SEG terminals ON waveform (second
7 (see FIG. 5EGn(HH))), and when it is "High", all the signals are displayed as ON.

However, camera marks CAI and CA2 cannot be controlled.

j70. Mera operation mode signal CAL from j71+
L MODE (See Figures 19, 20, and 21)
In normal AE mode, main switch SM is ON.
But the camera is not working in 5TANDBY mode, I
There are four states: ISO%- mode for SO setting and display, and +/- mode for +/general setting and display, and the display contents are switched according to each mode. (See Figures 28 to 35)j72. j73 is the camera's AE mode signal AEMOD
E (see FIGS. 22 and 23), and has four states: program mode, aperture priority mode, time priority mode, and manual setting mode, and the display contents are switched according to each signal.

j74 is the ISO output when prompting to set the ISO value.
This is a warning signal ISOARM (see FIG. 22), and when this signal becomes "High", the ISO mark and ISO value in the interior and exterior display sections 4 and 6 flash.

j75 is a mode light-off signal MODE OFF (see FIG. 23), and when this signal becomes "High", the AE mode display being displayed is turned off. Turn off the mode display when loading film into the camera.
Make it.

j76, j771! Photometry mode switching signal AVE/5PO
T (see Figure 23), and when the partial metering mode is selected between the average metering mode and the partial metering mode (either j76 or 377).
]Or! 2) Turn on AS2 on the internal display section 6 of the viewfinder. ASI is AE
Always lit during mode.

The DC4 also uses the external signal SM and Tσ as data, and is connected to the data code converter (Fig. 23) and the L of the display unit 4.6 for displaying other than the numerical range such as the second time value and the aperture value.
A decoding section (Fig. 22) for controlling blinking of each display segment of the CD display, and two signal switching sections SWI, S.
It is divided into three parts: a decoding section (FIG. 21) related to W2.

Figure 21 is created mainly with the switching signals of SWI and SW2, and the FOM, CTR, 15O5SS signals are created with SW1.
, MON, +/-ON signal controls SW2. In addition, the ON and OFF signals are commands to control the CTLI and display an ON display and an OFF display for all segments. Furthermore, the OF F V LCD signal functions to cut off the liquid crystal drive power supply and the liquid crystal drive circuit when this signal is "High". The purpose of this is to prevent DC voltage from being applied to the liquid crystal when the XL2's primary oscillation is stopped, and to reduce power consumption when the main switch SM of the camera is turned off.

On the other hand, 370.371 of the CALL MODE signal represents four camera operation modes.
gh” is called the AE mode for normal shooting.j70
・When j71=“High”, I for ISO sensitivity setting
It is called SO mode. When j70 and j71 = "High", it is called 5TANDBY mode, which is a camera standby state. j
70-j71-High" is called +/- mode for override amount setting.

In line with the above four modes, S W l , , S
To explain the signals for WZ (see Figure 21), in AE mode, when PWC goes "Low" (the camera starts operating), the FON signal goes "High" and S
Wt is activated, and aperture value information j12 to j06 is selected and decoded and displayed. When - becomes "High" in plf (the camera enters the standby state), the FON signal becomes "Low" and the aperture value information is erased by SWI.

On the other hand, when pwc is "Low" and j65 is "Low" (
During normal operation), the SS signal becomes "High" and shutter time information j22 to j27 are selected and decoded and displayed. At this time, other CTR signals and ISO signals are “Low”
, timer count information and ISO price range information WI
erased by

When deTe is “Low” and j65 is “High” (
During valve counting), the CTR signal becomes "High", and timer count information 340 to j47 are selected and decoded and displayed. At this time, the other SS signals and ISO signals are "Low" and are erased by the shutter speed information and ISO value range information WI.

Also, the +/-ON signal is 'Low', but the MON signal is pwc is 'Low' and 350 or j5B data is 'Hi'.
If it is "gh", it is "High", so the value information of the metered manual deviation amount is selected and decoded and displayed by SW2, but the value information of the override is erased.

SS, CTR, FON, MON in ISOS mode.

All +/-ON signals are "Lov", only the ISO signal becomes "High", the SWI operates, and ISO value information j32 to j37 are selected and decoded and displayed. At this time, other numerical bands are erased.

5 During TANDBY mode, SS, CTR, FON, I
The SO, MON, and +/-ON signals are all "low", and all numerical bands are erased.

During +/- mode, SS, ISO, CTR, FON, M
All ON signals become “Low” and pwτ becomes “Low”
At this time, the +/-ON signal becomes ``High''.

At this time, override information j50 to j53 are selected and decoded and displayed.

Figure 22 shows a control signal for the blinking display of each display segment. If the corresponding segment (see Table 1) lights up when the output Bl-B8 becomes "High", that segment is turned on. Flashing.

The B8 signal is a signal that causes the F mark on the external display section 4 to blink, and is mainly controlled by 357 data.

The B7 signal is the 7th segment of the LCD of the internal display section 6.
A signal that flashes the numbers 8 and 8 and the col and 2 second digits between them, mainly jss, jss, j6
)l data.

The B6 signal is a signal that blinks ASI and As2 on the internal display section 6, and is mainly controlled by j64 data.

The B5 signal is a signal that causes numbers 5 and 6 of the 7 segments, cal, and I to blink on both the external and internal display sections 4 and 6, and is mainly controlled by the j63 data.

The B4 signal is a signal that causes the first to fourth segments of the seven segments to flash on both the external and internal display sections 4.6, and is mainly controlled by the data of j6s and j74.

The B3 signal is a signal that causes both the external and internal display sections 4.6 to flash, and is mainly controlled by 362 data.

The B2 signal is a signal that causes the ISO mark on the external display section 4 to blink and is mainly controlled by 374 data.

The Bl signal is a signal that causes all segments other than the segments 88 to B2, excluding CAI and CA2, to blink, and there is no particular data signal. However, including Bl, blinking control is performed by j20 data from 82 to B8.

FIG. 23 shows a decoder for the seven segments for displaying numbers in the inner/outer representation section 4.6, except for 1-8 and cot, 1, col, and 2. Serial data
54-j57, j70-j73. j75-j77
, j21. and external signal PWC1 and further decode DC2
The output is controlled by each output signal q40, and the outputs are up to r51=r69, and each output is °High.
', the corresponding segments will light up.

FIG. 9 shows SW1, which selects signals.

The input signals are the aperture values of j12 to j16, and the aperture values of j22 to j16.
These are the shutter time value of j27, the ISO value of j32 to j37, and the timer count value of j40 to co47, and there are a FON signal, a CTR signal, a tSO signal, and an SS signal to select each of them. When each selection signal is “High”, it is NAND
The gate opens and the output data p becomes input data j. On the other hand, when it is "Low", the NAND gate closes and the output data p becomes "High".

(Example) When FON=“High” Outputs p12 to pte transmit inputs j12 to j16 as they are.

When FON=“Low”, all outputs pi 2 to pi 6 become “High”.

Next, although there are no detailed diagrams, DCI will be explained.

DCI is serial data j2 processed by SWl
2-j27, j32-j37. j40~j47
p22-p27. p32~p37, p40~
p47 as input, q corresponding to 7 segment 4 digit part
Data conversion I that outputs data from 1 to q39! (decoder). Figure 17.

Figure 18 is for explaining the concept of DCI,
The input data is 1) 36 types (buLb A-1/4000) of shutter speed seconds value < SS value corresponding to 22 to p27, ALL High, and ISO corresponding to p32 to p37.
SDI species (ISO6~l5O6400) and ALLHigh
h, timer count value (C
TR value) 100 types (01 to 99 and A L High
There is h.

For example, data p27~corresponding to SS value rbuLbJ
When p22="LLLLLL" is input (other data p32 to p37 and p40 to p47 at that time are A L
Processed with DC4 and SWl to make it L High. ) Output data is q7 data “bo” for segment decoder SDI, 418 data “L” for SO2, Q29 data “U” for SO2, SC
2, it becomes Q39 data "b".

In addition, data p37 to p corresponding to the tSO value r20QJ
32="LHHHLL" is input, other data p22 to p27.32 at that time is input. p40-p47 are ALLHigh
Processed with DC4 and SWI to make it look like this. ) Output data is Ql data for segment decoder SDIg2, q8 data for SO2, and q for SO2.
21 data, and data for SC2 is not output.

Also, p22-p27. p32-p37. p40~p
When all 47 are “High”, the segment data
! There is no output for Gouda 5DI-8D4.

All segments for 5DI-8D4 are turned off.

It is composed of a gate circuit having the above configuration.

Next, segment decoders SDI to SD4 shown in FIG.
I will explain about it. The data signals q1 to Q39 obtained in the previous section are respectively 91 to q7 to SDI and q8 to Q1B to SO.
2, q19-q29 are SO2, q30-q39 are S
Input to C2. The inside of the 5DI-3D4 is basically the same, but among the 14 inputs, terminals to which no corresponding data signals are input are pulled up to the power supply side in each block. This circuit is configured so that when the input becomes 'Low', a valid output can be obtained.For example, SD
When the q7 data signal (h of buLb) is output for I,
One input becomes “Low”. At this time, other SDI inputs ql-qs and human power being pulled up become “High”.
h”, but the outputs (c), (d), (e), (D, and (g)) related to the line that became “Low” all become “High” and the other (a), (b) ), (h)
The line is "Low". This output (c), Cd
), (e), (D, (g) correspond to r3 to r7 in terms of SDI terminals, which are input to the next stage CTLI and connected to the liquid crystal display. This r output is connected to the liquid crystal segment. Approximately corresponds to l to l (Fig. 16a, Fig. 2, c)
, see Table 2). The output here (c), (
d), (e), (D.

(g) corresponds to the numerical segment name of each of the seven segments, and represents the letter "B" (see Figure 2).

Further, for example, for SO2, the q21 data signal (“2
”), the Q] input becomes “Low 7” (a).

Q), (d), (e), and (g) become "High" and the character "2" is displayed.

p12 to p16 obtained by SWI enter the decoder DC2 shown in FIG. 14. When pie~p12="LLLLL", the output is q40, which is a "Low" output. q
The output of 40 goes to segment decoder SD5, while
Output to decoder DC4.

Other outputs are exclusively connected to SO5.

The contents of the outputs of Q40 to Q62 based on the data of p12 to pte include 23 types of aperture values shown in the concept of SD5 shown in FIGS. 19 and 20. These are segment decoded by a part of Sn2 (input part of q40 to q62) shown in FIG. 15, and outputs of r30 to r43 are obtained.

For data j50 to j53, decoder D in FIG.
There is C3. j50 data is decimal data,
A pt ratio output p2 output is obtained.

The j51-j53 data represents information from O to 6, and the outputs are p3 to p9, and the output is "High" and becomes active. This output is input to the switch SW2 in FIG. 12, and the output light is switched according to the selection information MON, +/-ON. When MON is High', +/-ON is a LO violation, and the outputs of p2 to p9 are inverted and output to q82 to q.
89, but q71 to q78 are all “High
h”.-Sumo wrestler/-When ON is High”, MON
is L os'', and the outputs of p1 to p7 are inverted and q
71-q77, but all q82-q89 become "High". Moreover, q78 is °L ov'. MON.

When both +/-ON are “Low-”, q71-Q78
The outputs of ゜q82 to q89 all become "High".

The output of SW2 is q71 to q78 to Sn2, q82 to q
89 is output to Sn2.

Q71 to q78. output by SW2. The contents of Q82 to Q89 are shown in Figures 19 and 20. q71 to q78 are seven types of numerical values and one type of decimal point for override values, and q82 to Q89 are as shown in Figures 19 and 20.
Q89 has 7 types of integer digit values for metered manual values (including override values) and 1 decimal display.
Each corresponds to the species.

Although the contents of Sn2 are not shown, the basic idea is the same as that of 5DI-Sn4 shown in FIG. 13, and is shown in FIG.

The gate configuration is such that there is a relationship between the data shown in FIG. 20 and the output display example.

Finally, r made by SDI~SD6 and DC4
l~r69 and Bl~B8. The output control unit CTLI, which inputs the ON and OFF signals as well as the clock of φI4, will be explained.

CTL"M11O11"'lt* I 6E bQyF
=t・1r69-S69. 5701
The configuration basically has the configuration shown in FIG. 16, except for the configuration shown in FIG. First, in Figure 16, when a "High" signal is input to r69, the gates for S69 and 870 open and φ
, 4 repeats "High" and "Low", but S69 and S70 output in opposite phases. In this way, the corresponding CA1. The CA2 mark lights up alternately, giving the impression that the camera mark is blurring.

For circuits for signals other than r69, the output S
Table 1 shows the logical expression and truth table showing the relationship between r and input r.

As this table shows, when the 5-ma signal becomes "LO", the output S
is S69. All except S70 become "High" and all the display contents except CA1 and CA2 light up.

Next, when the m signal is “High”, the OFF signal is “H”.
When the display becomes "high", all the outputs S except for S69 and S70 become "Low", and all the displays except for CA1 and CA2 turn off.

When the W signal is “High” and the OFF signal is “Lov”, when BIl (Bl to B8) becomes “Lov”, the output S=r, and the display content is in accordance with the display information given by serial data. Lights up to display.

ON signal is "Hjgh", OFF signal is Lot", B
When any part of e(Bl-88) becomes High by DC4, the output corresponding to r in the same group will be output depending on the combination of B and r under the truth table in Table 1. S blinks according to the display contents at that time according to the clock of φ,4.

For example, when the B6 signal is “High” and the other B1 to B
5. B7. When the B8 signal is "L ov", the corresponding outputs S59 of r59 and r60 in the B6 signal group
and S60 repeats "High" and "Low".

However, when the states of r59 and r60 are "LO", S59 and 960 cannot become "High". Therefore, As2 and AS corresponding to S59 and S60
If + is lit, it will change to flashing.

The outputs 5l-970 obtained from the above CTLl are input to each segment driver (Fig. 6), and output as a liquid crystal drive waveform (see Fig. 27) to the final output SEG terminal (SEGI to SEC35). .

The relationship between the CTLI output S and the SEG terminal is shown in Table 2.

The names of the segments shown in this table are the same as the names of all the segment diagrams shown in FIG. 2C.

1. When starting the camera - When the camera is started by turning on the main switch SM, an interrupt is generated in the CPU10 and cput is executed.

Released from the stop state, the internal ROM progera.

Starts operation according to the program. At the same time, voltage is supplied to the photometric circuit (not shown), but it takes several tens of meters513c for the photometric circuit to operate reliably and provide the necessary data to the CPU tO. do.

However, the CPU 10, which operates at high speed, has communicated serial data with the display circuit section one or more times at this point. The contents of serial data communication (see Figure 36) mainly include exposure information such as shutter speed and aperture value, but when the photometering circuit etc. is not operating normally, it is difficult to confirm the accuracy of this exposure information. No value is obtained. Therefore, it is not good to carry out serial data communication in this state, as it not only makes no sense but also causes erroneous display. Therefore, at startup, until the CPU10 takes in accurate information and completes the calculation, a troublesome inaccurate value is displayed on the display by sending data for turning off the light or data for standby display. You can make things go away. The display section of the embodiment has a structure in which the previous display is maintained unless new serial data communication occurs. As long as you do not use this to communicate serial data until the calculation is complete, there will be no particular problem, but since the program flow of the CPU10 program is designed to avoid exceptions as much as possible, serial data is sent at regular intervals. The method of communication is better in the sense that it does not increase the capacity of the ROM for programming. Therefore, the above method becomes better.

Immediately after the battery is installed in the camera, a voltage of 10 E is applied to the CPU 10 and the display circuit section 20, and each starts operating. Each circuit has a separate crystal oscillator XL1. XL2
, and starts operating independently, but in this case, XLI
Generally speaking, XL has a higher frequency than XL2.
I starts oscillating early. After the oscillation starts, the CPU10 starts operating according to the program in the internal ROM, but since there is little work to be done immediately after the battery is installed, it takes several tens of seconds.
It goes into a csec hang state and stops functioning, waiting for it to be woken up again. Generally, at this point, the oscillation rise of XL2 of the display circuit section 20 (generally roomsec to 1 s)
ec degree) is not guaranteed. When XL2 of the display section is not oscillating, serial data communication with CPU10 is not received, and the clock φ shown in FIG. 7 is not generated, so the operation is as shown in the time chart shown in FIG. 26. LTCH pulse will not be generated unless Furthermore, even if XL2 is oscillating, the data in the display circuit section 20 is not rewritten unless there is serial data communication. (7th fl.
J(1) Since PWC, C5, 5DATA, and SCK do not come, BS7 does not occur and LTCH pulse does not occur.

), the operation of the CPU 10 as described above is not good because the display content continues to be an indefinite display of the battery installed state. Therefore, as shown in Fig. 7 of this circuit, the jlO reset, j11 set, and the power-on reset circuit shown in Figs. 24 and 25 are used to reset the LCD.
One countermeasure is to prevent the initial indefinite display by turning off the driving power. Furthermore, if the power-on reset circuit does not work for some reason, or if it is not good for the display to remain off, continue serial data communication from CPU10 until the guaranteed time for the XL2 oscillation to rise after the battery is installed. As soon as the oscillation of XL2 starts, normal operation starts and the display contents change immediately. The contents of the serial data at this time may be data for turning off the light, data for standby display, or any other arbitrary data.

Therefore, the CPU operates by communicating serial data using display data immediately after the battery is installed (after performing this necessary processing and until the guaranteed start-up time of the XL2 oscillation), and after a predetermined period of time, it If so, it is sufficient to enter a stopped state and stop the function.However, CPtJlo must prohibit interrupt operations within the guaranteed rise time of the XL2 oscillation.

- Before CPUIO stops - ~ Immediately before cputo stops its operation, CPUIO sends standby mode display data to the display. After that, until the CPU [O starts up again, there will be no data transfer, so the display will not change.
The standby mode display continues. Immediately before the main switch SM is turned off and CPtJlO stops operating, CPUl0 sends display data for the lights-out mode to the display in the same way as above. After that, there is no data transfer until the main switch SM is turned on again, so the display remains unchanged and remains off.

-ALLON and ALLOFF- Serial data jlO and jll are the highest priority data that completely cut off LcDlljl.

““・The light goes off when jll=“High”.

On the other hand, data 366 and j67 are prepared for connection checking and are second priority data. j67=
A waveform in which all segments light up when “High”;
When j66="Low", a waveform in which all segments are turned off is output from the COM and SEG terminals, respectively. When each waveform is applied to a normally connected LCD, it will display whether all the lights are on or all the lights are off. However, if the connection with the LCD is misaligned, a part of the LCD may turn off or on, or the brightness may be different from other segments, which clearly indicates a connection error. Become.

Also, as a method of providing signals for serial data communication, 5DA
By connecting the TA line to +E through a small resistor, that is, pulling it up, all serial data will be “
The priority bit j67 becomes active and becomes the all-lighting mode.On the other hand, when connected to GND, that is, pulled down, all serial data becomes “High” information.
J66, which is the priority bit, becomes active and becomes the all-off mode. This is a very easy check that can be done even after the camera is assembled. 1 Furthermore, there is no need to provide a dedicated terminal, which is ideal.

- Off mode and standby mode - Fig. 35 shows the display on the external display section 4 in standby mode. Only the bar is lit and all other external and internal displays are turned off. As for the camera body, CPt
JlO is in a stopped state, waiting for input corresponding to an interrupt instruction. Further, although power is supplied to the display circuit 20, no power is supplied to any other circuits (not shown) other than the CPU10. However, when an interrupt input such as a photometry switch is input to the CPU10, power is supplied, other circuits start working, and the camera function starts.

On the other hand, the display in the lights-out mode turns off all displays.

The method is to turn off the LCD drive power by 0FFV LC.
Set D to "High". At this time, the camera body operates only in a stopped state where CPU10 is waiting for an input interrupt from the 3M terminal, and power is supplied to all other circuits except for the display circuit (not shown). Not done.

In standby mode and off mode, only the main switch SM is active in the camera's off mode. On the other hand, in the standby mode, an operation start switch such as a photometer switch (not shown) comes into play. Further, the current consumption is lower in the off mode, which is energy saving, and the voltage applied to the liquid crystal is zero in the off mode, so the liquid crystal has a good shelf life.

- Manually configurable data indication marks - Figure 29 a, b
In the A mode, the aperture plated steel mark 4TA2 lights up because the aperture can be set, and the black mark TAI on the shutter speed side, which cannot be set, turns off.

Similarly, in the S mode, that is, the Nyatta priority mode shown in Figures 30a and b, since the shutter speed can be set, the gray mark TAI on the shaft speed side is lit, and the gray mark TAI on the shutter speed side, which cannot be set, is displayed. Mark TA2 goes out.

In Figure 31 a and b, in manual (M) mode, both values can be set, so both marks TAI and TA2 are displayed.
lights up to indicate that both can be set.

In the P mode shown in FIG. 28, since there are no numerical values that can be set, both marks are turned off to clearly indicate their meaning.

The lighting and extinguishing of these marks is controlled using the AE mode information according to j72.373 as is.

However, if a function (not shown) for determining the presence or absence of a lens determines that there is no lens, the aperture of the lens cannot be set. Therefore, in this case, the setting mark TA2 regarding the aperture is specially set not to light up regardless of the mode. This is controlled by the q40 signal shown in FIG.

1-Open F value display - The aperture value display is a 7-segment numerical display as shown in FIGS. 28 to 31. The contents of the aperture value are shown in FIG. Here, the rQ40J signal indicates a state equivalent to no lens by displaying -1. rq43J~rq62J is 0.5
This is the aperture value rounded up for each EV. On the other hand, lens open F
Values include conventionally popular numerical values such as 3, 5, and 4.5. However, these values are not multiplied by the aperture value for each 0.5 EV, so these values are treated as special and prepared as rq41J and rq42J signals. In this case, when the result of the calculation performed by the CPU 1O or the set aperture value is the aperture value (judgment is made by an unillustrated aperture signal), and furthermore, it is 3.5 or 45 mm in this embodiment. gives a display signal from CPUso to display 3.5 or 4.5 instead of the normal display of 3.4 or 4.8. Further, when the result of the calculation performed by the CPU 10 or the set aperture value is not the aperture value, the normal display such as 3.4 or 4°8 is used for display.

It was designed to have the above two types of display formats.

As an example, FIGS. 33a and 33b show display examples of the open F value.

The open F value is determined, for example, as follows.

As shown in FIG. 40, in step SL the control CPLII
O reads the open p4iAvo from the lens 3 and stores it in the internal register. On the other hand, the CPU 1 O uses the calculated F value Ay calculated in step S2 based on the camera settings and the value obtained from the photometry results to calculate Avo in step S3.
= Av is determined, and if Avo = AV, open F @ A
Step S4) to extract vo, if Avo≠Ay, round the calculated F value Av to every 0.5EV and extract it Step S5), determine the data (AvDSP) of 02 to j16, and output the extracted output. The information is displayed on display units 4 and 6 (step S6).

-Combined display of override amount and metered manual amount- The +6.5 in Figure 31 is the deviation amount of the metered manual, and is always lit during the manual mode, which is the only internal display of the infinder. The display range is +6.5
~-6.5EV (see Figure 20), and when that amount is exceeded, +6.5 and -6.5 are displayed blinking. As data during blinking, M'dMOVER of j61 data is set to "High".

Also, +1.5 in Figure 33 is the override amount,
It always appears depending on the setting when in AE mode other than manual mode. Similarly, only the internal display of the infinder is displayed.

The displayed range is +4.0 to -4. It is OEM (see Figure 20) and cannot be set beyond that amount. Here, the override display is constantly flashing to distinguish it from the metered manual, and at the same time draws attention to the override setting.

On the external display, +/- symbols (OR+,
OR-, 0RS) lights up, but in metered manual mode, the +/- symbols (OR+, OR+) light up.

0R8) is turned off and not displayed.

The data for each quantity of override and metered manual is received and received using the same register.
A separate identification signal is required.

This signal is provided by the 5IGN signal of j54 to j56 data.

Table 3 shows the relationship between the data contents of j54 to j56 and their output display states. This makes the portions j54 to j56 of FIGS. 21 to 23 easier to understand.

-8 and A mode display- The displayed whale is shown in Figures 29 and 30.

FIG. 29 shows the display in the A mode, and the A mode display section with an arrow pointing toward the display of the manually settable aperture value is lit. Figure 30 shows the display in S mode,
Light up the S mode display with an arrow pointing toward the display of the manually settable second time value. By doing this, the meaning of the mode display and the meaning of the numerical display can be understood at a glance, making the mode display very easy to use.

Figures 38a and 38b show the display contents at the time of initial loading after mounting the film. During the initial loading period, when the film is not advanced, the shutter speed is 1/400 (1) and the aperture value is the minimum (F22 in this case). At that time, all exposure mode displays are off; sets the j75 bit to "High" and turns off the mode display.

Figures 39a and 39b show the display contents when the lens is not attached. When the CPU10 detects that there is no lens by a mechanism not shown, all display signals 02 to 06 are set to "Low". This is done in step S+8 of the flowchart of FIG. 41, and the display decoder receives this. outputs the 440 signal in Figure 20 and turns F62 in Figure 23 =Lo
w". Therefore, Display-1 is displayed as the aperture value, and the aperture chain side mark TA2 of the settable marks disappears.

Note that FIG. 42 shows another embodiment in which camera shake is displayed on the internal display section 6. In this case, as shown in (a) in the figure, it is composed of three segments, and the type of camera is indicated by lighting two of these segments. This 2
There are two types of segment selection, (b) and (C), and camera shake is displayed by lighting these two types alternately.

An outline of the operation of the control CPU10 is shown in Fig. 4.

By installing the battery, the CPU 10 starts operating from a reset start (step SO). At the same time, voltage is also applied to the display circuit. First, the camera is initialized both inside and outside the CPU 10 (step 510), and then display data, turn-off data, standby data, ISO data, etc. are sent n times to the display circuit (step 5ll). (
(n is a value determined depending on the time required for the display circuit to ensure normal operation) When the transmission is completed, an interrupt from a switch group (not shown) is permitted (step S I 2). And if there is nothing, it will stop the internal operation clock and enter a stop state (
Step 5I3). Among the switch groups (not shown), the photometric switch Sl or the initial load switch SB has a relationship with the main switch SM as shown in FIG. 44, and the other switch groups have the same configuration as Sl and SB. When main switch SM is OFF, SL and SB large inputs are pulled down and SL.

SB large input is dead. In this state, only the SM multiplication signal generates the INTset signal that generates an interrupt. Main switch SM is turned on! When the N T set signal is generated, an INT flip-flop (not shown) is set, and the CPU 10 performs an interrupt operation INT (step 51).
4) Enter. This INT flip-flop is set at the rising edge, and interrupts are enabled (step 51).
2), the INT flip-flop is reset and waits for another interrupt.

Now, when INT (step 514) is entered, check the switch SB for detecting the initial load state (step S15), and if it is 0FF (not the initial state), power is supplied to the photometry circuit (not shown), etc., and step S16) Start metering. After that, in step SI7, AE
The calculation is performed, display data necessary for the display circuit is prepared and sent out in step 818. Thereafter, the main switch SM is checked in step SI9, and if it is OFF, data for turning off the light is sent as display DATA in step S20, power supply is stopped, and photometry is stopped in step S21. After that, step SI2. Proceed to S13. If the main switch SM is ONL in step SI9, check the switch Sl (step S26). S21. Proceed to S12.813. If it is turned on in step S26, the release switch 82 is checked in step S22. If it is ON, exposure control (step 523) is performed and the process proceeds to step S17, but if it is OFF, nothing is done and the process proceeds to step S1.
Proceed to step 7 and perform the AE calculation again.

On the other hand, if the switch SB for detecting the initial load state is ON in step S15, the second value, aperture value, and MODE OFF information 5 data = "High" for the initial load are sent out in step S24. Then, an initial load is performed to control the shutter mechanism using the seconds value and aperture value (step 525). Thereafter, in step S15, the switch SB is checked again, and step 816 is performed depending on the state of the switch SB.
Starts photometry.

The transition from step S13 to SI4 depends on the SM, SL, and SB switches, as shown in FIG.
At F, the St and SB switches are in the "Low" state and are dead as switch signals. Therefore, S
Only when M turns ON, an INT Set signal is generated and an interrupt (INT) operation is started. Also, when SMh (ON), the Sl and SB switches come alive and the INTset signal is generated by St or SH, and an interrupt (INT) operation is started.

Although not shown, the SB switch is turned on when it detects the presence of film and that the back lid is closed, and turned off when a film counter (not shown) reaches 1.

FIG. 43 is a flowchart showing the operation for detecting camera shake. In step S31, CPIJIO reads necessary information such as focal length from the lens. Then, in step S32, the TV for shutter control is set by exposure calculation.
In addition to calculating the value, the TVL value of the camera shake warning limit is calculated from the lens information. Then, in step S33, the magnitudes of TV and TVL are compared, and if TV<TVL, YES, the process proceeds to step S34, and if TV>TVL, no, the process proceeds to step S35. In step S34, the LOWSS signal is set to "High" and the marks CAI and CA2 are set to "High".
j to issue a camera shake warning, and in step S35, the LOWSS signal is set to "Lo" and marked CA1. Turn off CA2.

Figure 44 shows CPUIG and switches St, S2゜SB, S
Indicates the relationship with M.

Table 1 <Combination of r2n and B-> Bl-r51-r53. r61~r65B2 -r54 B3 - r55~r5g, r67,, r68B4 -
rl ~r29 B5 -r30-r43 B6-r59. r60 B7 -r44 to r50 B8 -r66 Table 2 Table 2 (Continued) Table 2 (Continued) Effects of the Invention This invention provides that the metering mode mark displayed according to the metering mode of the camera is the metering range of the camera. Since the light blinks when the luminance exceeds 200 kHz, it is intuitively obvious that this is a warning related to photometry, and the distinction between photometry interlocking and control interlocking is clearly displayed.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing an example of a camera to which the present invention is applied, FIG. 2 a is a front view of the finder of the camera shown in FIG. 1, and FIG. FIG. 2C is a diagram showing an example of all the segments displayed on the internal display section of the display device of the present invention, and FIG. 3 is a block diagram showing an embodiment of the present invention. , Fig. 4 is a detailed circuit diagram of the oscillation divider section in Fig. 3, Fig. 5 is a detailed circuit diagram of the common driver in Fig. 3, and Fig. 6 is a detailed circuit diagram of the segment driver in Fig. 3. , FIG. 7 is a detailed circuit diagram of the data latch section in FIG. 3, FIG. 8 is a detailed circuit diagram of the decoder section in FIG. 3, and FIG. 9 is a detailed circuit diagram of the switch circuit SWI in FIG. 8. , FIG. 1O is a circuit diagram showing details of symbols in the circuit, FIG. 11 is a detailed circuit diagram of the data conversion section, FIG. 12 is a detailed circuit diagram of the switch circuit SW2 of FIG. 8, FIG. 14 and 15 are detailed circuit diagrams of the segment decoder of FIG. 8, FIG. 16a is a detailed circuit diagram of the output control section of FIG. 8, and FIG. Figures 17 to 20 are diagrams showing the relationship between input signals and display, Figures 21 to 23 are detailed circuit diagrams of the data conversion unit in Figure 8, and Figure 24 is a detailed circuit diagram of the data conversion unit in Figure 8. is a detailed circuit diagram of the voltage generation section in Figure 3,
Figures 5 to 27 are waveform diagrams of the main parts of the circuit in Figure 3, Figure 28a, Figures 28 to 34a, and Figure 34.
FIG. 35 is a diagram showing various aspects of display, FIG. 36 is a diagram showing the relationship between signals and registers, FIG. 37 a, b, c, FIG. 38 a, b, and FIG. 39 a. FIG. 40 is a flowchart of the CPU showing the display selection operation;
141 is a flowchart showing the operation of the CPU in FIG. 3, FIG. 42 is a diagram showing another aspect of camera shake display, FIG. 43 is a flowchart of the CPU showing the operation of camera shake display, and FIG. 44 is a flowchart showing the operation of the camera shake display. FIG. 2 is a circuit diagram showing details of a part of the CPU. 4... External display section, 6... Internal display section, 10...
CPU. 22... Data latch, 23... Decoder, 24...
...Segment driver. Patent Applicant Minolta Camera Co., Ltd. Agent Patent Attorney Aoyama Ao 2 others Figure 2 O Figure 20 SOS SOS, 23t 440 Beichi 2 Rei No. SOS 0.5 1.5 8.5 Days 3.5 5 .5 Figure 19 Figure 28 (0) P@-)? 1/250 F5.6 AVE; J5;
:: II 5. ;E, 0 Fig. 29 (a) A: E knee) l/250 F5.6 AVEJ″S'
G55650 Figure 30 (a) S@-1'1/250 F5.6 AVE, Yo°5.
:j@5. sEe mouth Figure 31 (a) Mmo)? 8" Fl, 6.5EV in 4 5POT notor cQ#・1.': Hard+8.5, therefore Fig. 32(a) IC+ 10.# Fig. 33(a) PROGRAM )rs n rt L LI II Lf, j IE'r::::::j 1111 3,5 +:
, 50 Fig. 34 (a) Fig. 34 (b) 1 g”1 rs 1-#S Fig. 35 Fig. 36 Fig. 37 C Fig. 37 0 CAI dead JLF [;J L', 80 Fig. 37 b A2 Fig. 38 0 呵DDrj,),)口 Fig. 39 0 Cabinet: S5-Prison mouth Fig. 40 Fig. 41 Fig. 42 (a) (b) (C) Fig. 43

Claims (1)

[Claims] (1) A display means for displaying a mark indicating the photometry mode;
What is claimed is: 1. A non-photometering display device for a camera, comprising means for detecting that the photometry range is exceeded; and display control means for changing the display state of the display means based on a detection signal from the detection means.