JPS61141424A - Display device - Google Patents

Abstract

PURPOSE:To make possible the execution of the test for all segment display and all segment erasure without providing separately test terminals by providing a register to store temporarily the serial data to control the display of a display means and feeding an all display signal or all erasure signal to the register. CONSTITUTION:The serial data j10, i11 are the most preferential data to turn off an LCD power source from the root. Whether all lighting up or all turning out is displayed when the respective waveforms are impressed to normally connected LCDs. An SDATA line is connected through a small resistor to +E, namely, said line in pulled up as one of ways to impress a serial data exchange signal. All of the serial data are then 'High' information and j67 which is the preferential bit is enabled, by which an all lighting up mode is set. On the other hand, all of serial data are 'low' information when said line is connected to a GND, i.e., when the line is pulled down. The j66 which is the preferential bit is then enabled and an all putting out mode is set.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a display device, and in particular to a display device that displays a desired pattern by selectively lighting a plurality of segments. The present invention relates to a display device that can be tested by turning off the light.

Prior art and its problems For example, in a display device that displays numbers by selectively driving display segments arranged in a Japanese character shape, in order to check whether or not each display segment is malfunctioning, A method is used to display or erase all display segments simultaneously.

In order to perform this type of test, conventionally, a predetermined test terminal was provided and a command signal for displaying all segments or a signal for erasing all segments was manually input.

However, this method requires the provision of separate terminals, which is uneconomical in terms of space and cost.

Purpose of the Invention The present invention provides a display device that displays a desired pattern by selectively displaying a plurality of display segments, which can display all segments and erase all segments without separately providing a test terminal. The object of the present invention is to provide a display device that can perform the following tests.

Structure of the Invention The display device of the present invention includes a display means having a plurality of display segments and a register for temporarily storing serial data for controlling the display of the display means, and transmits an all display signal or an all erase signal to the register. The present invention is characterized in that by sending a message, all segments of the display means are displayed or erased.

Embodiment FIG. 1 is a diagram showing the external appearance of a camera to which the present invention is applied. 1 is the camera body, 2 is a shutter button, 3 is an interchangeable lens, and the interchangeable lens 3 contains data about the lens, such as the maximum aperture value. A device is provided that outputs data indicating such information as an electrical signal to the camera body. Further, the shutter button 2 is provided with a photometric switch Sl and a release switch S2, which are operated according to the amount of depression of the button, by a known method.

Reference numeral 4 denotes an external display section, which displays the calculated EV value and operation mode, as well as various other data that will be described in detail later.

5 is a finder, and within the field of view of this finder 5 is provided an internal display section 6 (see FIG. 2) for displaying data and the like displayed on the external display section 4.

SM is the main switch.

Figure 2 shows details of the display on the external display section 4, and the PROGRAMS for AE momo display is shown from above.
There is one. When the AE mode is a program mode (hereinafter referred to as P mode), PROGRAM is displayed and S is turned off, and when the AE mode is in aperture priority mode (hereinafter referred to as A mode), A is displayed and PROCR and MS are turned off.

M and S are displayed in the manual mode (hereinafter referred to as M mode) and in the shutter speed priority mode (hereinafter referred to as S mode), respectively. Below that is S in iSOS mode.
There is an O mark, and immediately below it is a 7 segment 4 digit SS.
There are display sections for ISO and CTR, and on the right side there is a setting instruction mark TAI. Below that, there is a bar display that only turns off when the camera's main switch SM is turned off, and a 7-segment, 2-digit F, +/- display, and to the right of it is a setting display. There is an instruction mark TA2.

To the left of the two digits is an aperture value discrimination mark Fh<, and further to the left end is a +/- mark, which is a sign when setting an override.

Furthermore, FIG. 2C shows details of the display on the internal display section 6.
Starting from the left end, there are 2 adjacent images for displaying camera shake (camera shake).
Mark CAI has two camera shapes.

There is CA2, followed by 7 segment 4 digit SS.

There are ISO and CTR display sections, and then there are S, P, and A for AE momo display. The S mark consists of a 7-segment arrow pointing toward the 4-digit side to indicate shutter speed priority.
Similarly, the A mark is located immediately to the right to indicate aperture priority.
The segment consists of an arrow pointing toward the 2-digit side. The P mark has nothing to do with prioritizing both aperture and seconds, so there is no arrow between S and A. The 7 segment 2 digits on the right side for the AE momo display display the F value and the +/- value in the +/- mode. Immediately to the right is the M for displaying AE Momo.
There is a mark. This is because the metered manual display lights up at the same time, so it is displayed near the meter display to make it easier to understand. To the right are the override and metered manual symbols, tens and -, followed by a seven-segment numerical band. This numerical value band displays +/- values during AE mode (P, A.

(Only in S mode) and also displays the metered manual value in <AE mode (Only in M mode).

Finally, there are the ASI and AS2 marks that indicate the metering mode. For average metering, only ASI lights up, and for partial metering,
Both A'S l and AS2 are lit.

Figure 32 a, b and Figure 33 a, b are showing overrides, but in the internal display of the finder, the place where the override value is displayed is the override (+/-
) mode and AE mode. This is an attempt to display information near the center of the display section during override mode display to make it easier to understand.

FIG. 3 shows the overall configuration of the control device related to the above-mentioned camera display. CPUI O using a central control microcomputer that controls the operation of the entire camera
is supplied with power +E from the battery 11, and is a group of control signals to the main switch SM pulled up by a resistor R, and the reference oscillator XL19 for operating the CPU10 to peripheral circuits (particularly regarding the display).

cs, pwτ, and the normal data 5DATA, '8C and serial clock S required for serial data transfer.
Connects CK to the surrounding area.

An outline of the operation of CPU10 will be described later.

On the other hand, the display circuit section 20 receives a power supply from the battery 11 and signals from the main switch SM, cputo,
5DATA, SCK, reference oscillator XL2. A reference power supply 21 for driving the liquid crystal is input, and outputs include a group of driving outputs for common and segment electrodes of the external display section 4 and internal display section 6 using a liquid crystal display. The drive output terminal group is connected to the external display section 4 of the camera and the external display section 6 inside the camera, which are connected in parallel.

Inside the display circuit 20, there is a data latch section 22 that latches serial data. Decoder section 23 that decodes the latched data. Segment driver unit 2 that drives the LCDs of external and internal display units 4 and 6 using decoded signals
4. Common driver section 25 that drives the common section of the LCD
．． Oscillation frequency dividing section 26 that creates operating clocks for each section. L.C.
There is also a voltage generating section 27 that generates a driving voltage of D.
j Figure 4 is a detailed diagram of the oscillation frequency division section 26 in Figure 3, which includes a one-stage inverter (INl) oscillation unit using an external crystal oscillator XL2 and a flip-flop (FFI) that divides this reference oscillation. It consists of a frequency division stage composed of. The flip-flop FFI is provided with a reset terminal R so that it can be initialized by installing a battery.

FIG. 5 is a detailed diagram of the common driver section 25.
, VLCD2. VDD voltage analog switch A
C0M1. through SI-AS4 and PchFET FPl, FP2 at timings of φ, , φ1°. It is configured to output to C0M2. Nantes Gate NAI, 2. (Noa game) NRI, 2 and inverter IN3.4 are gates for creating timing.

FIG. 6 is a part of a detailed diagram of the segment driver section 24,
VLCD2. Segment data S2n, 52n- of the timings of φ, 1φ1° processed by flip-flop FF2 for analog switch AS5 and PchFET EP3 that switch each voltage of VDD.
It is configured to be driven according to the state of No. 1. Nant gates NA3 to NA7 and inverter IN6.7 are S2n
, 52n-1 constitutes a clock selector, and the inverter INS and flip-flop FF2 are φ9. It constitutes a clock generator for creating clocks with four types of phase differences from φ1°.

The entire segment driver section is of the type shown in FIG. 6, in which the clock selector, analog switch, and PchF'ET parts are removed by the number of SEG output terminals, and a clock generator is added.

FIG. 7 is a detailed diagram of the data latch unit 22. There are seven 8-bit soft registers 5RI-8R7 that receive serial data 5DATA from CPolo, and the parallel outputs of these shift registers are connected to the falling edge of the LTC14 signal. Seven 8-bit latches LTI~
Connected to LT7.

The reset 8 manual power is applied to the jlO data of the latch LTI, and the set S input is applied to the jll data, respectively.
It is reset and set by the OR signal. Therefore, the initial state is NO="Low" and NI="High".

On the other hand, the serial clock SCK from the outside is passed through the OR gate ORI as a φS signal to the Norgelt NR3 to NR.
9, and also serves as the φλ power of the counter decoder CD. When the set human power S of the counter decoder CD is “High”’, the output BS of the counter decoder CD
I to BS7 are all “High” and the S input is “Lo”.
When the voltage reaches ``w'', one of the signals from BSI to BS7 becomes ``Low'' every 8 pulses of the φλ force.

When any one of BSI to BS7 is “Low”,
One of the corresponding NOR gates NR3 to NR9 becomes active, and the φS signal, which is the input of the NOR gate, is transferred to one of the serial registers SRI to SR7.
Enter into the input. External control signal PWτ from CPU10
, ■ are logically summed by OR gate OR3 and become p
-cs times the signal, which is input to the other input of the OR gate ORI and the S input of the counter decoder. It also becomes one input of the OR gate OR2, performs an OR logic with the other input BS7, and becomes the D input of the flip-flop FF3 and one input of the Nant gate NA8. The FOR signal is input to the set power S of the flip-flop FF3, and its output is connected to the other power of NA8. Further, the φ output of FIG. 4 is connected to the φλ force of the flip-flop FF3.

FIG. 8 is a detailed block diagram of the decoder section 23 of FIG. 3, and is a detailed block diagram of the switch circuit SW1. SW2. Data converter DCI-DC
4. Segment decoder sections SDI to SD6. It is composed of an output control section CTL1. The switch circuit SWI receives outputs 12 to 12 of the decoder 22 as inputs.
j16. j22γ j2r, j32~ Ko37.
25 pieces of j4Q~+47, data conversion section DC3
- has four outputs j50 to j53 of the decoder 22 as input, and the data converter DC4 has the output jl of the decoder 22.
o, jll.

+20. j□l, j54〜,5□,,6o〜,6□,
70 to j77, 53 in total, are connected to the outputs of latches LTI to LT7 in FIG. Further, two signals SM and PWC from the main switch shown in FIG. 3 are input to the data converter DC4. Output controller CT
From Figure 4, φ and 4 are connected to LI as inputs,
Seventy 5t-570 outputs are connected to the segment driver section 24.

FIG. 9 is a detailed diagram of the switch circuit SWI in FIG. 8,
jn from data latch 22 (n = 12 to 47 (excluding +7.20.2 +, 30.31)) - P
n (n= 12~47 (+7.20, 30°3
FOM, CTR, ISO using 25 Nant gate NAs.

It is switched by the SS signal. FON, CTR.

When the l5O0SS signal is “Low”, the Pn signal is “Low”.
High” and the jn signal is cut off, but the FON.

Pn when CTR, ISO, SS signal is “High”
= jn, and the switch is turned on.

FIG. 10 is a diagram explaining the symbols used in FIG. 11, FIGS. 13 to 15, and FIG. 23, including A, B, and C.

For each input of D, the same function as the Nantes gate is indicated by marking the intersection of the arrow with the output Q. That is, Q
=B-D.

FIG. 11 is a detailed diagram of the data conversion unit DC3 in FIG.
The logic of outputs pi to p9 is shown for inputs j50 to j53. This output serves as an input to the switch circuit SW2 shown in FIG.

FIG. 12 is a detailed diagram of the switch circuit SW2 of FIG. 8, in which the input pt-99 is switched from q71 to q78 . Represents the logic switched to Q82-q89. The input p signal enters the Nantes gate,
When the switching signal MON and the +/-ON signal are "Low", the output q signal becomes "I-l-1i" and the p signal is cut off.

When MON, +/-ON signal is “High”, output q
The signal becomes equal to the input p signal and the switch is turned on.

Figure 13 shows the segment decoder sections SD■ to SD in Figure 8.
In the detailed diagram of 4, outputs rl-r2 for inputs q1 to q39.
It shows the logic of 9. This figure shows segment decoder section 5.
Since the basic configuration of the DI-5D4 is the same, they are shown in the same drawing, but each of S1 to S70 is a necessary part extracted from this drawing. This output is an input to the output control section CTL1 shown in FIG.

FIG. 14 is a detailed diagram of the data converter DC2 of FIG. 8, showing the logic of outputs q40 to Q62 for inputs p12 to p16. This output is from the segment decoder SD in Figure 8.
5 input.

FIG. 15 is a detailed diagram of the segment decoder section SD5 of FIG. 8, in which inputs q40 to q62. For Q71 to Q78,
It shows the logic of output r30 Nr43. This output is an input to the output control section CTLl shown in FIG.

FIG. 16a is a part of a detailed diagram of the output control section CTLl of FIG. 8, in which outputs S1 to S70 are obtained by the outputs of the segment decoder sections 5Di-8D6 and the data conversion section DC4 and the clock φ14.

In this figure, r2n and Bm are shown in arbitrary combinations, but in reality they are connected in the combinations shown in Table 1.

Table 1 shows a truth table by replacing the circuit diagram of FIG. 16a with logical expressions. Furthermore, the combination of r2n and Bm is specifically shown. (1≦m≦8).

(1≦21≦68) r69 is shown in FIG.

The 16th diagram shows input r69 and output s69. It shows the logic to s70.

FIG. 17 shows the data conversion section DC1' (7) of the decoder section 23.
) shows the relationship between the outputs q1 to q39 and the characters displayed on the display units 4 and 6, and shows the relationship between the outputs q1 to q39 and the characters displayed on the display units 4 and 6.
2-p27. p32-p37, p40-p47. CT
When Ql-q:39 is output according to the state of H, q1
The displayed characters are controlled depending on the "Low" or "High" state of ~Q39.

That is, if the output ql is "High", the display unit 4 (and 6) will display the lθ° position as 0°, and if 2 is High, then the display will be 10-0. The display will be 2.
1. 1122-p27 for shutter speed SS value, p32-I)37 for ISO value, p40-p4 for CTR value
7 and CTR signals respectively. Also, p22
When p27, p32 to p37 and p40 to p47 are all "High", no output is produced for that data. Therefore, for example, when data from 922 to p27 for the Nyabuta speed SS value is displayed, other data from p32 to p37. It is constituted by a data converter DC4 and a switch circuit SWI so that MO to p47 are all set to "High". (See FIGS. 9 and 21) The contents that can be displayed are illustrated in FIG. 18. There are 36 types of SS values, 31 types of SO values, and 100 types of CTR values.

19 and 20 are diagrams showing the relationship between the data of the data conversion unit DC2 and the switch circuit SW2 and the characters displayed on the display units 4 and 6.
p12-p16 and SW2 pi-p9, MON, +
/ -q40 to q62 depending on the ON state. q71-
q78. The outputs of q82 to Q89 output data as shown in this figure. p12 to p16 for F value, p1 for override value and metered manual value
Data are given on p.9.

FIG. 21 is a part of a detailed diagram of the data converter DC4 of FIG. 8, showing switch switching signals MON, +/-ON, FON of switch circuits SWI and SW2.

CTRjSO,SS logic and CTLI part σN,O
The logic of the FF signal and the 0 applied to the voltage generator 27 in FIG.
Each shows the logic of the FFVLCD signal. The input signals are output signals jlo, koIt, j55 .
j56, j60 to J67゜jro, j'i'l, external signals, SM, PW 100.

FIG. 22 is a part of a detailed diagram of the data conversion section DC4 of FIG. 8, and shows the logic of the B1-88 signal of the CTLI section.

The human input signal is the output signal j20. of the data latch section. j55
~j57. j61~j64°j70~]74 and the external signal PWC.

FIG. 23 is a part of a detailed diagram of the data conversion section DC4 of FIG. 8, and shows the logic of the r51 to r69 signals of the control section CTLI. The input signal is the output signal j of the data latch section
21. j54～j57゜j70～j73. j75～j7
7 and the output signal q40 of the DC2 section. and external signal
It is. In FIGS. 21 to 23, the data conversion section D in FIG.
Contains all C4.

FIG. 24 is a detailed diagram of the voltage generating section 27. Create a reference voltage VLCD by externally connecting a diode D1 and a resistor R1 between +E and GND, and connect a capacitor C+.

By supplying the voltage to the booster circuit 27a (the part surrounded by the broken line) including CI, the voltage doubled (+E-V LCD) is
E-V LCDI). VLCD and VLC
DII; and V LCD0 and V LCD, respectively, by output control circuits made with analog switches and PchFETs.
2.

V LCD0 to V LCD2i! , 0FFV The output changes depending on the state of the LCD. When OF F V LCD is “Low”, V LCD0= V LCD,
V LCD2 = V LCDI, 0FFV LC
When D is “High” +7>, V LCD0 = V
LCD2 = V DD.

In addition, the booster circuit section 27a obtains a clock from φ in FIG. Boosting is performed by switching the connection of Ct. Further, FOR is a terminal for starting the booster circuit, and the booster circuit is started by the FOR output shown in FIG.

FIG. 26 is a time chart of the data latch section 22 of FIG. 7. External signals PWτ, τ” both become “Low”, and at the falling edge of SCK, serial register 5RI-8
The data in R7 will be rewritten.

The contents of SRI are all rewritten at the falling edge of the first 8th pulse of SCK, and from the 9th pulse onwards, they are rewritten in order in shift registers SR2 to SR7 every 8 pulses. At the rising edge of the 49th pulse immediately after SR6 is rewritten, BS7 goes low, and at the same time as SR7 rewriting begins, flip-flop FF3 changes F'F3 to read the D input at the rising edge of φ. σ output is “L”
OW” and does not change until BS7 becomes “High” again.

01″”P°C3('iゞ1°19・LTCH7</L
,X.

is created, and the contents of the SRI to SR7 serial registers are taken into the latches of LTI to LT7.

FIG. 25 is a time chart showing the overall general operation from after the battery is installed in the camera. Immediately after the 74 cell is installed, the display circuit section 20 is initialized by the FOR signal. Signal VL
CDI becomes earth GND level, OF F V L
CD becomes ``High''.Therefore, no voltage is applied to the liquid crystal.Then, the CPU I0)XLl starts oscillation, and CPUl0I!l< starts to operate.After a while, the display circuit section 20 Oscillator XL2 starts oscillating, clock φ.

~φ14 starts to start. When the clock φ starts operating, the data latch section 22 starts operating, and when serial data comes from CPU10, it operates as shown in FIG. 26. Ria
When the switch φ6 starts operating, the voltage generating section 27 shown in FIG. 24 starts operating, and after a short period of time, the potential of the signal VLCDI becomes stable. After that, set 0PFVLCD to “L” as necessary.
ow", the LCD drive voltage, VLCDO, VL
CD2 is supplied to display sections 4 and 6.

28 to 35 and 37 to 39 show various display modes of the external display section 4 and the internal display section 6, and except for FIG. The figure shows the display on the internal display section 6.

Figures 28a and 28b are AE displays in program mode, showing auto second time 1/250, auto aperture value 5°6, PROGRAM of the program, and diagrams.

The mark ASI at the right end of FIG. 28 indicates the photometry mode and indicates average photometry.

Figures 29a and 29b are AE displays in aperture priority mode, showing the aperture setting marker, set aperture value 5.6, and auto second time 1/250. represent.

FIGS. 30a and 30b are AE displays in the shutter speed priority mode. When the second time setting mark is pressed, the set second time value is 1/250 and the automatic aperture value is 5°6, and S and ■, which give priority to the second time, represent the AE mode.

FIGS. 31a and 31b are AE displays in manual mode.

The glossy second time and aperture value setting mark indicates the set glossy second time value 8" and the set aperture value 14, and the manual mode M and the figure represent the AE mode. The right end of the internal display indicates the partial metering mode in the metering mode. The left side is the error amount of the manual setting value with respect to the appropriate value, which is the so-called metered manual indication value, +6.5EV
This indicates that there is a difference in indication. Further, the mark on the left end is a mark indicating a camera shake (hand shake) warning, and the two marks are lit alternately.

FIGS. 32a and 32b are displays during override setting. Represents the override direction and absolute 1i1.5EV.

FIGS. 33a and 33b are AE momo displays after override setting. An override direction indicator is added compared to FIG. 28. The internal display also displays the absolute override amount of 1.5 EV. However, +1 and 5 are blinking on the internal display.

FIGS. 34a and 34b are displays during ISO setting.

The ISO mark and ISO value 100 are displayed.

However, the ISO mark does not light up on the internal display.

FIGS. 37a and 37b show hand shake (camera shake) warning displays. On the internal display section 6, mark CA on the leftmost camera
I and CA2 light up alternately to indicate movement.

FIG. 37C shows the display of the external display NS4.

FIG. 35 is a display in standby mode.

Only the bar display was dimmed, and all other lights were off. Functions other than camera display are in a stopped state.

<Operation Description> - Overall Operation - The basic operation of the display circuit section 20 will be explained. When the DC voltage +E is supplied from the power supply 11, the momentary F generated by the power-on reset circuit 40 (right end in Figure 4)
The OR signal causes the flip-flop FFI of the frequency division stage (FIG. 4), the flip-flop FF2 of the clock generator of the segment driver section 24 (FIG. 6), and the flip-flop FF3 of the data latch circuit 23 to be activated. latch[,
TI (Figure 7), starting FET 27b of voltage generator 27
(FIG. 24) are each set to the initial state. Latch T
In l, each data terminal is j10="Low".

Set N1="High". Flip-flop FFI.

In FF2, set the output state to Q=“Low” and ζ-=”High.
Set the output state to Q="High" in FF3.
“.

Set = “Low”. In the voltage generation section 27, FET
27b is turned on for a moment, the capacitor C1 is charged with electric charge, and the level of VLCDI becomes the GND level. In this state, since the crystal oscillator XL2 of the oscillator 41 (Fig. 4) has not started oscillating, there is no circuit operation at all, and the oscillation rise of XL2 ( Waiting for the oscillation rise of =φ. In one direction, VDD, VLD2.
Although VLDO is given in an undefined state, (COMI
is VLCD2゜coM2 is VLCDQ, 5EGn is S
VDD or V LCD depending on the state of 2n, 52n-1
2) OFFVLC manually supplied to the voltage generation section 27
Due to the initial setting of jlO="Low" and j11="High", D is set as AND gate A50° and inverter I50. VLCD2=VLCDO which is set to “High” through the OR gate 050 by the switch circuit in FIG.
=VDD,! - The voltages applied to each terminal of the LCD display in the inner and outer display sections 4.6 are equal, and there is no direct current voltage application that is harmful to the liquid crystal.

Next, the crystal oscillator XL2 starts oscillating and φ. When a clock enters the flip-flop FFI of the frequency dividing stage, all parts start operating at the same time.

The clock φ enters the flip-flop FF3 of the data latch section 22, and functions to generate an LTCH pulse when the norial data communication from the CPU10 starts.

The clock φ is input to the booster circuit of the voltage generator 27'), C
By switching the + and Ct capacitors, boost operation is performed.

Clock φ1. φ1° enters the common driver section 25 and segment driver section 24 and becomes a clock for the liquid crystal drive waveform.

The clock φ14 is input to the output control section CTLI of the decoder section 23 and is used to control the blinking state of the display contents.

The operation after the rise of oscillation of the crystal oscillator XL2 will be explained first with respect to the voltage generating section 27.
The clock φ6 that has entered starts the boost operation, and the initial V L
CDI terminal was at GND level (V DD-
2V LCD) level and stabilize. Thereafter, it continues to work without interruption until the power supply voltage drops and it stops operating, or the oscillation circuit stops, causing the lifting and lowering operation to stop. On the other hand, the data latch circuit 22, which starts operating in response to the clock φ, causes the terminals jlO and jlll to go 'Low'.

The moment a signal other than "High" is input and latched, 0FFVLCD becomes "Low" and the analog switch on the right side of Figure 24 switches, and VLCD2 = VLC.
D1. VLCDO=VLCD f7) Wait for output. These are common drivers 25. The internal and external display sections 4 are guided by the segment driver 24 as a voltage for driving the liquid crystal.
, 6, and a liquid crystal display is performed based on the latched data.

Next, the data latch section 22 will be explained with reference to FIG. 26. This circuit starts operating when both the pwc and cs multiplied signals become "Lov". yWe is, for example, a timing signal for supplying power to a photometric circuit of a camera (not shown), and is
The photometry circuit starts operating when W is set to “Low”. The signal σ is a signal that determines the other party for serial data communication, and one signal is output from the CPU 10 to other circuits in the camera (not shown). eq=
At “Low”, the other party for serial data communication is selected.

When either pwc or cs is “High”, P・C
8 signal is “High”, the counter decoder CD is set, and all BSI to BS7 outputs are “High”.
”. Also, the output φS of the OR gate OR+ is “H”.
The output LTCH of the Nant gate NA8 is also “High” 'T: pwc, cs
7 are all “Low”, the counter decoder CD becomes the operating state and the OR gate OR
I and OR gate OR2 open, and the signals SCK and BS7 become detectable. At the rising edge when the first pulse of SCK is input, BSI becomes "Low" and NOR gate NR3 opens. At the falling edge of the first pulse, shift register SRI's φ
Since the input rises, only one shift register SRI takes in the contents of 5DATA at that time. The data at this time is j
It is lO. Then a second pulse comes and the same operation is repeated. At the falling edge of the eighth pulse, eight pieces of data are taken into the shift register SRI, and the eighth data is called 07. Until this time, the signal BSI is "Low".

When the next 9th pulse rises, BSI becomes °High, B S,2 becomes "L, ow", NOR gate NR3 closes, and NOR gate NR4 opens. At the fall of the 9th pulse, φ input of shift register SR2 5D at that time to rise up
Only one shift register SR2 takes in the contents of ATA. The data at this time is j20. From then on, the process continues in the same way, and at the rise of the 49th pulse, BS6 becomes H4gh".
BS7 becomes “Low”, Noah gate NR8 closes,
Noah game) NR9 opens. Further, the output of the OR gate OR2 becomes "Low". The contents of shift register SR7 are taken in from 570 to j77 up to the 56th pulse, but the data from LTC until the 56th pulse after the first pulse is taken in.
H output remains High, and each shift register S
Data is not fetched from R to latch LT.

The output of the OR gate oR2 becomes "Low" due to the OR gate OR2 opening at the 49th pulse, but the flip-flop FF3 receives the D input's "Low" due to the rise of the clock φ2, and the output becomes "High".
become. However, since the other input of the Nant gate NA8 becomes "Low" before the q output changes, the LTCH output remains "High".

Here, the output of the OR gate OR2 becomes "High" depending on whether the 57th pulse comes or whether either pwc or υ了 becomes "High". At this moment, one output of the flip-flop FF3, which is the other input of the NAND gate NA8, is also "High", so the output L T CH of the NAND gate NA8 becomes "Lah". This “High
The falling edge of ``→''Low'' signals the latch, and the data temporarily stored in the nft registers 5RI-SR7 is latched into the data memory of the latches LTI-LT7.Then, the rising edge of the clock φ causes the flip-flop F to be latched.
F3 takes in the “old gh” of the D input, and the σ output is “Lo”
w”, and the counter decoder CD is pwc, c
So is set to either "High", and each returns to its initial state.

This is an outline of the operation of the data latch. Here, if the number of clock bytes for Norial data communication is insufficient, the last latch pulse LTCH will not be output, so no data abnormality will occur, and even if the number of clock bytes exceeds 5.
It is automatically turned off at the 7th pulse, and naturally no abnormality occurs.

Furthermore, since the clock within the same byte is processed so as not to be interrupted on the sending CPU side, abnormalities in data communication are completely prevented.

On the other hand, even if the MIE signals PWc, C8, SCK, and 5DATA operate normally, if the internal φ is not operating, the L
TCH pulse stopped coming out, Soft Renostar 5RI-5
The data taken into R7 cannot be latched into latches LTI to LT7. This means that if it is considered that the liquid crystal drive waveform does not operate when φ is not operating, a DC voltage will be applied to the liquid crystal. Therefore, at that time, jl O='Low', N I='High'
It is necessary to maintain the voltage and set OFVLCD="High" so that no voltage is applied to the liquid crystal. For this reason, external data is not taken in when the clock φ is not operating.

Next, the common driver section 25 and the segment driver section 2
I will explain about 4.

In Figures 5, 6, and 27, Nant Gate N
A1. NA2. Noahgelt NR1, NR2, inverter IN3. FETs FPl, F of analog switches ASI to AS4゜Pch are controlled by the gate circuit composed of IN4.
Controls each switch of P2. The input signals of the gate circuit are φ and φ1°, and due to this timing, C0M2
．． The outputs of COMI change as shown in FIG. 27.

Signals GO, M2, and COMI have the same period as the clock φ1°, and are shifted from each other by 1/4 period.

The output value has three levels: VDD, VLCD0, and VLCD2.

In Fig. 6, four types of clocks generated by the clock φ processed by the clock generator composed of the inverter INS and the flip-flop PF2, and φ10 are configured by the Nant gates NA3 to NA7, and by the a clock selector. select. The selection condition is S2n
, 52n-[, and by this condition, 5
The output waveform of EGn is determined.

This state is shown in FIG. 27, and each state is different depending on four types of states determined by S2n and 52n-1.

The period is the same as that of the clock φ, 0, and there is a shift of 1/4 period from each other. The output values are VDD and V
It has two LCD levels. Signal C0M1.
The potential difference between 2 and segment signal 5EGn is 2 x V
The waveform rises to the part that becomes LCD2, and the LCD display lights up. 5EGn (LH), 5EG for C0M1
The segment of the LCD display to which a voltage of n (III-1) is applied lights up, and 5EGn for C0M2
(HL), 5EGn (HH) segments of the LCD display to which voltages are applied are lit. 5EGn(LL
), the segment will not light up even for COMI and C0M2.

In other words, the 52n-1 signal is a signal that controls lighting of the segment for COMI, and is OFF when 52n-1="Low" and ON when 52n-1="High". The S2n signal is a signal that controls the lighting of the segment for C0M2, and is OFF when 52n="Low".
When 52n='High', it is turned ON.

Data latched in Figure 7 jlO−jl7゜j20~
j27, j30~j37. j40～j47゜ko5
0~ko57. j60~ j67,. 70～j7
7 is 07. j30. All except the 3 bits of j31 are input manually to the decoder section shown in FIG. SWt.

SW2. DCI to DC4 and SDI to SD6 are simply gate circuits and have no timing relationship at all.

The explanation is below.

First, the contents of the serial data will be explained.

310, jll is a signal that controls the supply of liquid crystal drive voltage, j10=“Low”, jll=“High
The liquid crystal driving voltage stops only when the voltage is "h", and the voltage applied to the liquid crystal becomes 0.

j12 to j16 are data signals regarding the aperture value of the camera (
(see Figures 9, 14, 15, and 20),
There are 23 types. Also, j+2 to j16 are all “High”
Nothing is displayed when .

j20 is a signal related to a warning of insufficient battery voltage in the camera (see Figure 22), and j20="High"
All the displays displayed at this time repeat blinking at a period determined by φ, 4.

j21 is a hand shake (camera shake) warning signal (see FIG. 23), which becomes "High" when the shutter speed becomes slower than near the limit that causes hand shake (camera shake).

At this time, the camera shake mark CA1 on the internal display section 6 in the viewfinder. CA2 lights up alternately.

j22 to j27 are data signals (
(see Figures 9, 13, 17, and 18),
There are 36 types. Also, j22 to j27 are all “High”
'', nothing is displayed.

332 to j37 are data signals regarding the ISO value of film sensitivity (FIGS. 9, 13, and 17).

(see Figure 18), and there are 31 types. Also, J32~j
When all 37 are "High", nothing is displayed.

j40 to j47 are data signals (
(see Figures 9, 13, 17, and 18),
There are 100 types from 0 to 99.

Further, when all of j40 to j47 are "High", nothing is displayed.

50 to j53 are data signals regarding the override value and the deviation amount of the metered manual (see Figures 11, 12, and 19.20), and ``jt6M*1=t
e″Ct ” y 4 FO* 9 M
i and 14 types of metered manual deviation values are switched and sent from the CPU. j50~j5
When all 3 are "High", nothing is displayed. For switching the display contents, see j55. The receiver has the j56 signal (described later).

354 to 56 are the override value, the sign of the metered manual deviation amount, and the 5IGN signal (see Figures 21, 22, and 23) related to signal switching, and 354 is "+" and the signal related to the sign of “-”, j
55 and j56 are signals for switching data between the override value and the metered manual deviation amount for each external display and internal display.

j57 is a signal used to display the so-called preview moment (see Figures 22 and 23), which is used to check the depth of field by narrowing down the lens aperture before shooting. Sometimes this signal becomes "High", causing the aperture mark F on the external display section 4 to blink and the set value range indication mark TAI.

Controls the lighting of the bar at TA2.

j60 is the ISO display priority signal I5OPR+. This means that the main switch SM is OFF and 0FFVL
Even if the CD signal is H4gh'' and the liquid crystal drive voltage is stopped, the 0FFV LCD signal is set so that when this signal goes high, the liquid crystal drive voltage is supplied to the segment driver 24 and common driver 25. Lo
w” (see Figure 21) This signal is not used alone, but data on the ISO display mode and ISO value is sent from the CPU 10 at the same time as this signal. In terms of camera operation, this means that the battery is installed. This is the state immediately after.

Noro 1 is a blinking signal of the deviation amount of metered manual M'dMOVEH (see Figure 22), and this signal is @H4.
gh”, the deviation value of the metered manual flashes.

]62 is a shift signal 5HIF for blinking the program mode mark during the shift of the camera's program mode.
T (see FIG. 22), and when j62 is "High", this mark blinks. Here, the shift refers to a state in which the combination of the aperture value and the glossy second value in the program mode is changed and operated. Incidentally, all AE modes can be blinked as needed, regardless of the program mode.

j63 is the control interlocked warning signal Not, C0NT (22nd
(see figure), and this signal goes “High” when an exposure value that exceeds the aperture value and second value that the camera can control is required.
h”, and the aperture value and/or second value flashes on the calculation control value side depending on the AE mode to issue a warning.

j64 is the brightness out-of-linkage warning signal BV (see Figure 22), and when the brightness value exceeds the brightness value that the camera can measure, this signal becomes "I (high"), and the ASI while the metering mode display is displayed. and AS2 flashes to warn you.

Column 5 is the bulb time signal BULB (see Figure 21), which is a signal that causes the camera to switch the display contents of 4 digits and 7 segments during bulb exposure from the shutter seconds display (buLb) to the bulb exposure seconds count display. At "High", the valve count is displayed and the contents of j40 to j47 are displayed.

j66 is an all-lights-off signal ALLOFF (see Figure 21), which controls the waveform of the drive SEG terminal so that it becomes an OFF waveform (see Figure 27, 5EGn (LL)). will be displayed. However, camera marks CAI and CA2 cannot be controlled.

j67 is an all-on signal ALLON (see Fig. 21), which turns all the waveforms of the SEG terminals for driving into ON waveforms (see Fig. 21).
(See Figure 5EGn(HH)).
When set to “High”, all are displayed as ON.

However, the camera mark CA1. CA2 cannot be controlled.

j70. j71 is the camera operation mode signal CALL M
ODE (see Figures 19, 20, and 21), normal AE mode, 5TANDBY mode in which the camera is not operating even if the main switch SM is ON, ISO mode for tSO setting and display, +/general +/ for setting/displaying
- There are four modes, and the display contents can be switched by one according to each mode. (See Figures 28 to 35)j72. Core 3 receives the camera's AE mode signal AEMODE (Figures 22 and 23).
(see figure), program mode, aperture priority mode,
There are four states: shutter speed priority mode and manual setting mode, and the display contents are switched according to each signal.

j74 is the rso output when prompting to set the ISo value
This is a warning signal rsOARM (see FIG. 22), and when this signal becomes "High", the ISO mark and ISO value in the interior and exterior display sections 4.6 flash.

j75 is r--do light off signal MODE OFF (23rd
(see figure), and when this signal becomes "High", the AE mode display being displayed turns off. Turn off the mode display when loading film into the camera.
Make it F.

j76 and j77 are photometry mode switching signals AVE/5POT
(See Figure 23), and when the partial metering mode is selected between the average metering mode and the partial metering mode (either j76 or 377 or ! becomes "Low"), the viewfinder's internal display Turn on AS2 in section 6. ASI is always lit during AE mode.

The DC4 also uses the external signal SM and the ``W people'' as data, and includes a data code converter (Fig. 23) and a display section 4.6 L C for displaying outside the numerical range such as the shutter speed value and aperture value. , a decoding unit (Fig. 22) for controlling blinking of each display segment of the D display, and two signal switching units SW.
It is divided into three parts: a decoding part (FIG. 21) related to I and SW2.

FIG. 21 is created mainly with switching signals of SWI and SW2, and includes FOM, CTR, [sO, SS signals i! SW
+, MON, +/-ON signals control SW2. In addition, the σN and OFF signals are commands to control the CTLI and display an ON display and an OFF display for all segments. Furthermore, the OF F V LCD signal functions to cut off the liquid crystal drive power supply and the liquid crystal drive circuit when this signal is "High". The purpose of this is to prevent DC voltage from being applied to the liquid crystal when the XL2's primary oscillation is stopped, and to reduce power consumption when the main switch SM of the camera is turned off. On the other hand, j70.371 of the CALL MODE signal represents four camera operation modes, but ■・j71="High
h” is called the AE mode for normal shooting.
・When j71=“High”, I for ISO sensitivity setting
It is called SO mode. When j70 and j71 = "High", it is called 5TANDBY mode, which is a camera standby state. j7
0.j71-When it is "High", it is called +/- mode for setting the override amount.

To explain the signals for SWI and SW2 according to the above four modes (see Figure 21), during AE mode, v
We becomes “Low” (the camera starts operating).
Then, the FON signal becomes “High” and SWI works,
Aperture value information [2 to j16] is selected and decoded and displayed. When YW becomes "High" (the camera enters a standby state), the FON signal becomes "Low" and the aperture value information is erased by SWI.

On the other hand, when pwc is "Low" and 365 is "Low" (
During normal operation), the SS signal becomes "High" and the shutter speed information j22 to j27 are selected and decoded and displayed. At this time, other CTR signals and ISO signals are “Lo”.
and the timer count information and ISO value information are SWl
erased by

When PWτ is “Low” and 365 is “High” (
During valve counting), the CTR signal becomes "High" and timer count information j40 to j47 are selected and decoded and displayed. At this time, the other SS signals and ISO signals are "Low", and the shutter speed information and SO value information are erased by SWI.

Also, the +/-ON signal is "Low", but the MON signal is PWC is "Low" and j50 or 356 data is "Hi".
If it is "gh", it is "High", so the value information of the metered manual deviation amount is selected and decoded and displayed by SW2, but the value information of the override is erased.

In 150 mode, SS, CTR, FON, MON.

All +/-ON signals are “Low”, and 150 signals “
““”““°゛””1°゛so”.

Information j32 to j37 are selected and decoded and displayed. At this time, other numerical bands are erased.

5 During TANDBY mode, SS, CTR, FON, I
The SO, MON, and +/-ON signals are all "Low" and all numerical bands are erased.

During +/- mode, SS, ISO, CTR, FON, M
All ON signals become “Low” and PW() becomes “Lo
w'', the +/-ON signal becomes High.

At this time, override information j50 to j53 are selected and decoded and displayed.

Figure 22 shows a control signal for the blinking display of each display segment. When the output B1-88 becomes 'H4gh', if the corresponding segment (see Table 1) is lit, that segment is Flashing.

The B8 signal is a signal that causes the F mark on the external display section 4 to blink, and is mainly controlled by 357 data.

The B7 signal is the 7th segment of the LCD of the internal display section 6.
This is a signal that flashes the numbers 8 and 8, and the col and 2 second digits between them, mainly j55. j56. It is controlled by the data of j61.

The B6 signal is a signal that blinks ASI and AS2 on the internal display section 6, and is mainly controlled by j64 data.

The B5 signal is a signal that causes external/internal display sections 4.6 and 67 segments 5 and 6, col, and l to blink, and is mainly controlled by the j63 data.

The B4 signal is a signal that causes 7 segments 1 to 4 to blink on both the external and internal display sections 4.6, and is mainly used for j63. It is controlled by the data of j74.

The B3 signal is a signal that causes both the external and internal display sections 4.6 to flash, and is mainly controlled by 362 data.

The B2 signal is a signal that causes the ISO mark on the external display section 4 to blink and is mainly controlled by 374 data.

The B1 signal is a signal that causes all segments other than the segments 88 to B2 to flash except for CAI and CA2, and there is no particular data signal. However, including Bl, the blinking control is controlled by the j20 data from 82 to B8.

FIG. 23 shows a decoder for seven segments for displaying numbers in the inner/outer representation part 4.6, except for 1 to 8 and cot, I, col, and 2. Serial data j54 to j57. j70~jrs, j75~j7
7, j21. and external signal PWC1 and further decode DC
The output is controlled by each of the two output signals q40, and the outputs range from r51 to r69, and each output is “High”.
h”, each segment corresponding to it lights up.

FIG. 9 shows SW1, which selects signals.

The input signal is the aperture value of j12 to j16, 122 to
Shutter time value of j27, ISO value of j32 to j37,
These are the timer count values j40 to j47, and there are a FON signal, a CTR signal, an ISO signal, and an SS signal to select each of them. When each selection signal is "High", the NAND gate opens and the output data becomes p; human data j; on the other hand, when the selection signal is "Low", the NAND gate closes and the output data becomes p.
= “High”.

(Example) When FON=“High” Outputs p12 to p16 transmit inputs 02 to j16 as they are.

When FON="Low", outputs p+2 to pt6 are all H
It becomes “high”.

Next, although there are no detailed diagrams, DCI will be explained.

DCI is serial data j2 processed by SWl
2-j27. j32-j37. j40~j47
p22-p27, p32-p37, corresponding to
This is a data converter (decoder) that inputs p40 to p47 and outputs data of ql-439 corresponding to the 7-segment 4-digit part. Figure 17.

Figure 18 is for explaining the concept of DCl,
The human power data includes 36 kinds of shirt time values (SS values) corresponding to p22 to p27 (buLb-1/4000) and ALL
High, p32-p371. :handle! SOS
S value type (ISO6~l5O6400) and ALLHigh
, timer count value (CT
R value) 100 types (0” to 99”) and ALL High
There is 1.

For example, data p27~corresponding to SS value rbuLbJ
When p22="LLLLLL" is input (other data I at that time) 32 to p37. p40~I) 47 is ALLH
Processed with DC4 and SWI to make it bright. )
The output data is q7 for segment decoder SDI.
Data “b”, Q+8 data “shi” for Sn2
, Q29 data "U'" for Sn3, and q39 data "b" for Sn2.

Also, data p37 to p corresponding to the ISO value r200j
32 = "LHHHLL" is input, other data at that time I) 22 to p27. p40-p47 are ALLHigh
It is processed using DC4 and SWI so that it becomes h. ) The output data is qt data for segment decoder SDI, q8 data for Sn2, and Q for Sn3.
21 data, and data for Sn2 is not output.

Also, p22-p27. p32-p37, p4
When all of p0 to p47 are "High", no output is output to the segment decoders 5DI-5D4.

All segments for 5DI-6D4 are turned off.

It is composed of a gate circuit having the above configuration.

Next, segment decoders SDI to SD4 shown in FIG.
I will explain about it. The data signals q1 to 439 obtained in the previous section are respectively Ql-47 to SDI and q8 to q18 to Sn.
2, Q19 to q29 to Sn3, and q30 to Q39 to S
Input to n2. The inside of the 5DI-8D4 is fundamentally the same, but among the 14 inputs, terminals to which no corresponding data signals are input are pulled up to the power supply side in each block. This circuit is configured so that when the input becomes "Low", a valid output can be obtained. For example, S.D.
When the q7 data signal (b of buLb) is output for l,
Self-lighting human power becomes “Lot”. At this time, other SDI inputs ql-qe and inputs that are pulled up become “High”.
Outputs (c), (d), (e), (f), (g
) are all “High” and the other (a), (b),
(h) The line is “L ov”. This output (c),
(d), (e), (f), and (g) correspond to SDI terminals r3 to r7, which are the next stage CTL terminals.
Human power is applied to I, which leads to a liquid crystal display. This r output corresponds approximately 1:1 to the liquid crystal segment (see Fig. 16a, Figs. 2 and 2c, and Table 2). The output here (c
), (d), (e), (D and (g) each correspond to the numerical segment name of the 7 segments and represent the character "6" (see Figure 2).

Further, for example, for Sn2, the Q21 data signal (r2
When j) is output, the ■input becomes “Low” (a).

(b), (d), (e), and (g) are “High”
Then the character "2" will be displayed.

p12 to pts obtained by SWI enter the decoder DC2 shown in FIG. 14. p16~I)12=“LLLLLL”
The output at the time is q40, and a "Low" output is output.

The output of q40 goes to segment decoder SD5 while it goes to decoder DC4.

Other outputs are exclusively connected to SC2.

The contents of the outputs of q40 to Q62 based on the data of p12 to pte include 23 types of aperture values shown in the concept of SC2 shown in FIGS. 19 and 20. These are subjected to segment decoding in a part of SC2 (input section of q40 to q62) shown in FIG. 15, and outputs of r30 to r43 are obtained.

For data j50 to j53, decoder D in FIG.
There is C3. j50 data is decimal data,
A p1 output and a 22 output are obtained.

The data j51 to j53 represent information 0 to 6, and the outputs thereof are p3 to p9, and the output is "High" and becomes active. This output is input to the switch SW2 in FIG. 12, and the output light is switched according to the selection information MON, +/-ON. When MON is °High, +/-ON is "L"
ow”, and the outputs of p2 to p9 are inverted and q8
2 to Q89, but Q71 to q78 are all "
When -Rikishi/-ON is 'High@', MON is "Low" and the outputs of p1 to p7 are inverted and output to q71 to q77, but q82 to q8
9 are all "High"1°'''・1t''・°78°1
"1°°"'1・MON, 7+/-O
When both N are “Low”, 471 to 478°q82
The outputs of ~q89 all become ``High''.

The output of SW2 is Q71 to q78 to SC2, q82 to q
89 is output to Sn6.

q71-q78. output by SW2. q82~Q89
The contents are q71 to q78 as shown in Figures 19 and 20.
is 7 kinds of numerical values for override value and 1 kind of decimal point, 482
~Q89 corresponds to seven types of integer digit numerical values for metered manual values (including override values) and one type of decimal display.

Although the contents of Sn6 are not shown, the basic idea is the same as that of 5Dl-8D4 in FIG. 13, and FIG.

The gate configuration is such that there is a relationship between the data shown in FIG. 20 and the output display example.

Finally, r made by SDI~SD6 and DC4
l~r69 and Bl~B8. When ON, OFF signals and the clock of φI4 are input, the output control section C
TLI will be explained.

The internal configuration of the CTL is not shown in FIG.

r69-869. Except for the configuration of the S70 portion, the configuration is basically as shown in FIG. 16a. First, in FIG. 16, when a "High" signal is input to r69, the gates for S69 and 370 are opened and a clock of φ1° is used.
“High” and “Low” (again, S69 and S70 are output in opposite phases. In this way, the corresponding CA1
．． The CA2 mark lights up alternately, giving the impression that the camera mark is blurring. Regarding circuits for signals other than r69, logical expressions and truth tables showing the relationship between the output S and the input r are shown in Table 1.

As this table shows, when the σ signal becomes “Low”, the output S
is S69. All except S70 are "High" and the display contents are CA1. All lights except CA2.

Next, when the ON signal is “High”, the OFF signal is “°High”.
When it becomes "High", all the outputs S except for S69 and S70 become "Low", and all the displays except for CA1 and CA2 turn off.

“When Be (Bl-88) becomes “Low” when the OFF signal is “High” and the OFF signal is “Low”, the output S
-r, and the display is lit according to the display information given by the serial data.

The signal is “High” on δ, the OFF signal is “Lov”,
When any part of Bm (Bl to B8) becomes “High” by DC4, r in the same group is determined according to the combination of B and r under the truth table in Table 1.
The output S corresponding to .phi., 4 flashes according to the display contents at that time in accordance with the clock of .phi.,4.

For example, when the B6 signal is “High” and the other B1 to B
5.87. When the B8 signal is "L ov", the corresponding outputs S59 and 860 of r59 and r60 in the B6 signal group repeat "Htgh" and "Low".

However, if the states of r59 and r60 are "Low", S59 and S60 cannot become "High". Therefore, Ac1 and AS corresponding to S59 and S60
If I is lit, it will change to flashing.

Outputs S1 to S70 obtained by the above CTLI are input to each segment driver (Figure 6), and output as a liquid crystal drive waveform (see Figure 27) to the final output SEG terminal (SEGI-SEG35). .

The relationship between the CTLI output S and the SEG terminal is shown in Table 2.

The names of the segments shown in this table are the same as the names of all the segment diagrams shown in FIG. 2C.

1. When starting the camera: When the camera is started by turning on the main switch SM, an interrupt is generated to the CPU 10, the CPU 10 is released from the stopped state, and the camera starts operating according to the program in the internal ROM. At the same time, voltage is supplied to a photometric circuit (not shown), but it takes several tens of seconds for the photometric circuit to operate reliably and provide the necessary data to the CPU 10.
time is required.

However, the CP [JIO, which operates at high speed, is performing serial data communication with the display circuit section at least once at this point. Contents of serial data communication (see Figure 36)
The main sources of exposure information are shutter speed, aperture value, etc., but accurate values of these exposure information cannot be obtained at the time when the photometry circuit etc. are not operating normally. Therefore, it is not good to carry out serial data communication in this state because it not only has no meaning but also causes erroneous display. Therefore, at startup, until the CPU10 takes in accurate information and completes the calculation, a troublesome inaccurate value is displayed on the display by sending data for turning off the light or data for standby display. The display section of the embodiment has a structure that retains the previous display unless there is new serial data communication.Using this, serial data communication can be carried out until the calculation is completed. If not, there is no particular problem, but CPU programs are designed to create a program flow that minimizes exceptions, so it is better to communicate serial data at regular intervals because it requires less ROM capacity for the program. This is good in the sense that it does not increase the amount of data.Therefore, the above method is better.

Immediately after the battery is installed in the camera, a voltage of 10 E is applied to the CPU 10 and the display circuit section 20, and each starts operating. Each circuit has a separate crystal oscillator XL1. XL2
, and starts operating independently, but in this case, XLI
Generally speaking, XL has a higher frequency than XL2.
I starts oscillating early. After the oscillation starts, the CPU10 starts operating according to the program in the internal ROM, but since there is little work to be done immediately after the battery is installed, it stops functioning after several tens of seconds, waiting for it to be woken up again. . -'Generally, at this point, the oscillation rise of XL2 of the display circuit 9820 (generally 100m5ec~l s
ec degree) is not guaranteed. When XL2 of the display section is not oscillating, serial data communication with CPUl0 is not received and the clock φ shown in FIG. 7 is not generated, so the timing chart shown in FIG. It does not operate and no LTCH pulse is generated. Furthermore, even if XL2 is oscillating, the data in the display circuit section 20 is not rewritten unless there is serial data communication. (Since PWC, CS, 5DATA, and SCK in Figure 7 do not come, BS
7 does not occur and no LTCH pulse occurs. ), the operation of the CPU 10 as described above is not good because the display content continues to be an indefinite display of the battery installed state. Therefore, in this circuit, the IO reset, 01 set, Fig. 24, and 25 shown in Fig. 7 are performed.
One countermeasure is to prevent the initial indefinite display by turning off the power for driving the LCD using a power-on reset circuit as shown in the figure. Furthermore, if the power-on reset circuit does not work for some reason, or if it is not good for the display to remain off, continue to communicate serial data from the cPUIO until the guaranteed start-up time of the XL2 oscillation after the battery is installed. As soon as the oscillation of XL2 starts, normal operation starts and the display contents change immediately. The contents of the serial data at this time may be data for turning off the light, data for standby display, or any other arbitrary data.

Therefore, the CPU operates by performing serial data communication using display data from the time it performs necessary processing immediately after the battery is installed until the guaranteed start-up time of the XL2 oscillation, and after a predetermined period of time, if necessary. All you have to do is go into a stopped state and stop functioning. However, CPU10 must prohibit interrupt operations within the guaranteed rise time of the XL2 oscillation.

- Before CPUIO stops - Immediately before CPUIO stops its operation, CPUIO sends standby mode display data to the display. After that, until cputo is activated again, there is no data transfer, so the display remains unchanged and the standby mode display continues. Immediately before the main switch SM is turned off and the CPU10 stops operating, CPU10 sends the display data for the light-off mode to the display in the same manner as described above. After that, there is no data transfer until the main switch SM is turned on again, so the display remains unchanged and the light continues to go out.

-ALLON and ALLOFF- Serial data jlO and jl1 are the highest priority data that completely turn off the LCD power supply.

It turns off when jlo/jll=“High”.

-"5°61!ik'Fj°"(Df-91"141'
″”′ It is prepared for the 1st, and the 2nd
This is priority data. When j67="High",
The waveform in which all segments are lit, and the waveform in which all segments are turned off when j66 = “Low” are COM and SE, respectively.
Output from the G terminal. When each waveform is applied to a normally connected LCD, it will display whether all the lights are on or all the lights are off. However, if the connection with the LCD is misaligned, the L
A part of the CD may be off or on, or the brightness may be different from other segments, which clearly indicates a connection abnormality.

Also, as a method of providing signals for serial data communication, 5DA
By connecting the TA line to +E through a small resistor, i.e., pulling it up, it will be serial and some of it will be “
The priority bit j67 becomes active and becomes the all-lighting mode.On the other hand, when connected to GND, that is, pulled down, all serial data becomes “High” information.
It becomes "Low" information, and the priority bit j66 comes alive and becomes the all-lights-off mode. This is a very easy check that can be done even after the camera is assembled.

Furthermore, there is no need to provide a dedicated terminal, which is ideal.

- Off mode and standby mode - Fig. 35 shows the display on the external display section 4 in standby mode. Only the bar is lit and all other external and internal displays are turned off. As the camera body, the CPU
l0 is in a stopped state and is waiting for an input corresponding to an interrupt instruction. Further, although power is supplied to the display circuit 20, no power is supplied to any other circuits (not shown) other than the CPU 1O. However, when an interrupt input such as a photometry switch is input to the CPU10, power is supplied, other circuits start working, and the camera function starts.

On the other hand, the display in the lights-out mode turns off all displays.

The method is to turn off the LCD drive power by 0FFV LC.
Set D to “High”. At this time, the camera main body operates only in a stopped state in which the CPU 10 waits for an input interrupt from the SM terminal, and power is not supplied to any other circuits except for the display circuit (not shown).

The difference between the camera in standby mode and lights out mode is that in lights out mode, only the main switch SM is active. On the other hand, in the standby mode, other operation start switches such as a photometry switch (not shown) come into play. Further, the current consumption is lower in the off mode, which is energy saving, and the voltage applied to the liquid crystal is zero in the off mode, so the liquid crystal has a good shelf life.

- Manually configurable data indication marks - Figure 29 a, b
In the A mode, since the aperture can be set, the mark 4TA2 on the aperture value side is lit, and the black mark TAI on the shutter speed side, which cannot be set, is turned off.

Similarly, in the S mode, that is, the shutter priority mode shown in Fig. 30a and b, since the shutter speed can be set, the 4 mark TAI on the shutter speed side is lit, and the beak on the aperture side, which cannot be set, is lit. Mark TA2 goes out.

In Figure 31 a and b, in manual (M) mode, both numbers are setting cylinders, so both marks TAI and TA2 are displayed.
lights up to indicate that both can be set.

In the P mode shown in FIG. 28, since there are no numerical values that can be set, both marks are turned off to clearly indicate their meaning.

Note that these marks can be turned on or off by jr2. ;73 is used as is for control.

However, if the function for determining the presence or absence of a lens (not shown) determines that there is no re-lens, the aperture of the lens cannot be set. Therefore, in this case, the setting mark TA2 regarding calibration is specially set not to light up regardless of the mode. This is controlled by the q40 signal shown in FIG.

1-Open F value display - The aperture value display is a 7-segment numerical display as shown in FIGS. 28 to 31. The contents of the aperture value are shown in FIG. Here, the rQ40J signal indicates a state equivalent to no lens by displaying -1. rq43J~rq62J is 0.5
With aperture value rounded for each EV
There is one. On the other hand, the lens open F-number includes values such as 3, 5, and 4.5, which have been popular in the past. However, these values are not multiplied by the aperture value for every 0.5 EV, so these values are treated as special and r
Prepare as q41J, r q42J signals. In this way, the result of calculation by CPUl0 or the set aperture value is the aperture value (judgment is made by an unillustrated aperture signal), and furthermore, it is 3, 5, 4.5, etc. in this embodiment. In some cases, the normal display is 3.4 or 4.
．． A display signal is given from the CPU10 so as to display 3.5 or 4.5 etc. instead of 8 etc. Further, when the result of the calculation performed by the CPU 10 or the set aperture value is not the aperture value, the normal display such as 3.4 or 4°8 is used for display.

The above two series of display formats are provided.

As an example, FIGS. 33a and 33b show display examples of the open F value.

The open F value is determined, for example, as follows.

As shown in FIG. 40, in step St, the control CPU10
reads the open F value Avo from the lens 3 and stores it in an internal register. On the other hand, CPU10 uses the calculated F value Ay calculated in step S2 based on the camera settings and the value obtained from the photometry results, and in step S3, Avo=Av.
If Avo=AV, take out the open F value Avo (step S4); if Avo≠Ay, calculate the F value Ay
Step S5) of rounding up to every 0.5 EV,
The data (AvDSP) of j12 to j16 are determined, and the extracted outputs are displayed on the display units 4 and 6 (step S6
).

-Combined display of override amount and metered manual amount- The +6.5 in Figure 31 is the deviation amount of the metered manual, and is always lit during the manual mode, which is the only internal display of the infinder. The displayed range is +6.5
~-6.5EV (see Figure 20), and when that amount is exceeded, +6.5 and -6,5 are blinking and displayed.The data when b blinks is M'dMOVERh of j61 data.
(Set to "High".

Also, +1.5 in Figure 33 is the override amount,
It always appears depending on the setting when in AE mode other than manual mode. Similarly, only the internal display of the infinder is displayed.

The displayed range is +4.0 to -4.0 EV (see Figure 20), and settings cannot be made beyond that amount. Here, the override display is constantly flashing to distinguish it from the metered manual, and at the same time draws attention to the override setting.

On the external display, +/- symbols (OR+,
However, in metered manual mode, the +/- symbol (OR+, OR-) lights up.

0R8) is turned off and not displayed.

The data for each quantity of override and metered manual is received and received using the same register.
A separate identification signal is required.

This signal is provided by the 5IGN signal of j54 to j56 data.

Table 3 shows the relationship between the data contents of j54 to j56 and their output display states. This makes the portions j54 to j56 of FIGS. 21 to 23 easier to understand.

-6 and A mode display- The display mode is shown in FIGS. 29 and 30.

FIG. 29 shows the display in the A mode, and the A mode display section with an arrow pointing toward the display of the manually settable aperture value is lit. Figure 30 shows the display in S mode,
Light up the S mode display with an arrow pointing toward the display of the manually settable second time value. By doing this, the meaning of the mode display and the meaning of the numerical display can be understood at a glance, making the mode display very easy to use.

Figures 38a and 38b show the display contents at the time of initial loading after mounting the film. During film blank feeding, which is the initial loading period, the shutter speed is 1/4000 seconds and the aperture value is controlled at the minimum value (F22 in this case). At that time, all exposure mode displays have disappeared, but this is because the j75 bit is set to "High" to erase the mode display. 1 Figures 39a and 39b show the display contents when the lens is not attached. When the CPU10 detects that there is no lens by a mechanism not shown, all 02 to 06 for display are set to "Lo".
v''. This is done in step S18 of the flowchart of FIG.
The q40 signal shown in the figure is output and F62 of FIG. 23 is set to "Low". Therefore, Display-1 is displayed as the aperture value, and the aperture chain side mark TA2 of the settable marks disappears.

Note that FIG. 42 shows another embodiment in which camera shake is displayed on the internal display section 6. In this case, as shown in (a) in the figure, it is composed of three segments, and the type of camera is indicated by lighting two of these segments. This 2
There are two types of segment selection, (b) and (C), and camera shake is displayed by lighting these two types alternately.

FIG. 41 shows an outline of the operation of the control CPU10.

By installing the battery, the CPU 10 starts operating from a reset start (step So). At the same time, voltage is also applied to the display circuit. First, inside CP and UIO.

Initial camera settings are performed on both the outside and the outside (step 510).
Then, display data, turn-off data, standby data, ISO data, etc. are sent n times to the display circuit (step 5ll). (n is a value determined depending on the time it takes for the display circuit to guarantee normal operation) When the transmission is finished, interrupts from a switch group (not shown) are permitted (step 5I2)
. If there is nothing, the internal operation clock is stopped and the system enters a stopped state (step 613). Among the switch groups (not shown), the photometric switch Sl or the initial load switch SB has a relationship with the main switch SM as shown in FIG. 44, and the other switch groups have the same configuration as Sl and SB. When the main switch SM is OFF, the SL and SB large inputs are pulled down and the SL.

SB large input is dead. In this state, only the SM multiplication signal generates the INTset signal that generates an interrupt. When the main switch SMh is turned on and the
)to go into. This INT flip-flop is set at the rising edge, enabling interrupts (step 512).
), the NT flip-flop is reset and waiting for another interrupt.

Now, when the INT (step 514) is entered, check the switch SB that detects the initial load state (step S15). Photometry is started in step S16. After that, in step SI7
E calculation is performed to prepare display data necessary for the display circuit and send it out in step S18. Thereafter, the main switch SM is checked in step S19, and if it is OFF, data for turning off the light is sent out as display DATA in step S20, power supply is stopped, and photometry is stopped in step 521. After that, step S12. Proceed to S13. Also, if the main switch SM is ON in step S19, check switch S1 (step S26) L, OFF.
In this case, data for standby display is sent out as display data in step S16. S21. S12. Proceed to S13. If it is turned on in step S26, the release switch 82 is checked in step S22. ON
If so, perform exposure control (step 523) and proceed to step S17, but if it is OFF, do nothing and proceed to step S.
The process advances to I7 and the AE calculation is performed again.

On the other hand, if the switch SB for detecting the initial load state is ON in step S15, the second value and aperture value for initial load and MODE OFF information information 5 data = "High" are sent out in step S24. Then, an initial load is performed to control the shutter mechanism using the seconds value and aperture value (step 525). Thereafter, in step S15, the switch SB is checked again, and depending on the state of the switch SB, the photometry starts in step SI6.

To move from step S13 to S14, as shown in FIG. 44, depending on the switches SM, SL, and SB,
When F, the SL and SB switches are in the "Low" state, and are dead as switch signals.
There is. Therefore, an INT set signal is generated only when SM is turned on, and an interrupt (INT) operation is started. Also, when SM is ON, the St and SB switches are active, and the NTset signal is generated by Sl or SB, and an interrupt (INT) operation begins.

Although not shown, the SB switch is turned on when it detects the presence of film and that the back lid is closed, and turned off when a film counter (not shown) reaches 1.

FIG. 43 is a flowchart showing the operation for detecting camera shake. In step S31, the CPU 10 reads necessary information such as focal length from the lens. Then, in step S32, a TV value for gloss control is calculated by exposure calculation, and a TVL value for camera shake warning limit is calculated from lens information. Then, in step S33, TV and T
Comparing the size with VL, if TV<TVL, YES, the process proceeds to step S34, and if TV>TVL, NO, the process proceeds to step S35. In step S34, the LOWSS signal is set to "High" and the marks CAI and CA2 are vibrated to issue a camera shake warning. In step S35, the LOWSS signal is set to "Low" and the marks CA1 and CA2 are vibrated to issue a camera shake warning. Turn off CA2.

FIG. 44 shows CPU+o and switch S1. S2゜SB,S
Indicates the relationship with M.

Table 1 <Combination of r2n and B+> Bl -r51- r53. r61~r65B2 -
r54 B3 - r55 to r58. r67, r68B4-r
l -r29 B5 - r30~r4'3 B6-r59. r60 B7 -r44 to r50 B8 -r66 Table 2 Table 2 (Continued) Table 2 (Continued) Effects of the Invention As detailed above, the present invention is capable of controlling display in a display device having a plurality of display segments. Since the display device is tested by adding signals to the serial data that instructs all segments to be displayed, all segments to be turned off, and all segments to be turned off, display tests can be performed without the need for special test terminals. Omission can save space and cost.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing an example of a camera to which the present invention is applied, FIG. 2 a is a front view of the finder of the camera shown in FIG. 1, and FIG. FIG. 2C is a diagram showing an example of all the segments displayed on the internal display section of the display device of the present invention, and FIG. 3 is a block diagram showing an embodiment of the present invention. , FIG. 4 is a detailed circuit diagram of the oscillation frequency dividing section in FIG. 3, and FIG. 5 is a detailed circuit diagram of the common driver in FIG. 3.
1. FIG. 6 is a detailed circuit diagram of the segment driver in FIG. 3, FIG. 7 is a detailed circuit diagram of the data latch section in FIG. 3, and FIG. 8 is a detailed circuit diagram of the decoder section in FIG. 3. Figure 9 shows the switch circuit SWI in Figure 8.
10 is a circuit diagram showing details of symbols in the circuit, FIG. 11 is a detailed circuit diagram of the data conversion section,
Figure 2 is a detailed circuit diagram of the switch circuit SW2 in Figure 8, Figures 13, 14 and 15 are detailed circuit diagrams of the segment decoder in Figure 8, and Figure 16a is the output of Figure 8. A detailed circuit diagram of the control section, Figure 16 is a detailed circuit diagram of a part of the circuit in Figure 8, Figures 17 to 20 are diagrams showing the relationship between input signals and displays, and Figures 21 to 20 are diagrams showing the relationship between input signals and displays. Figure 23 is a detailed circuit diagram of the data conversion section in Figure 8, and Figure 24 is a detailed circuit diagram of the data conversion section in Figure 8.
Detailed circuit diagrams of the voltage generating section shown in Figures 25 to 27
The diagrams are waveform diagrams of the main parts of the circuit in Figure 3, Figure 28a,
Figures 34-a, 34-35 are diagrams showing various aspects of display, Figure 36 is a diagram showing the relationship between signals and registers, and Figures 37-a, b, c, and 35 are diagrams showing various aspects of display. Figure 38a, b, Figure 39a. 40 is a flowchart of the CPU showing the display selection operation, FIGS. 41 and 41 are flowcharts showing the operation of the CPU in FIG. 3, and FIG. FIG. 43 is a flow chart of the CPU showing the operation of displaying camera shake, and FIG.
FIG. 2 is a circuit diagram showing details of a part of the CPU shown in the figure. 4...External display unit, lO...CPLI. 22... Data latch, 22... Decoder, 24...
...Segment driver, SRI~SR7...Shift register, 5DATA...
・Noreal data.

Claims (1)

[Claims] (1) It is equipped with a display means having a plurality of display segments and a register that temporarily stores serial data that controls the display of the display means, and by sending an all display signal or an all erase signal to the register, A display device characterized by displaying or erasing segments.