JPS61141428A - Display device of camera - Google Patents

Abstract

PURPOSE:To simplify the program of a CPU by erasing the display of unnecessary data, symbol, etc. when the correct data to be displayed is not obtd. CONSTITUTION:The display data of a standby mode is fed from the CPU10 to the display immediately before the CPU10 stops operation. There is no data transfer and therefore there is no display until the CPU10 starts again thereafter. The standby is thus continued. The display data of the putting out mode is fed from the CPU10 to the display immediately before the CPU10 stops operation after a main switch SM is turned off. There is no data transfer and therefore there is no change in the display until the main switch SM is turned on again thereafter. The putting out state is thus continued.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a camera display device, and more particularly to a camera display device having a function of displaying automatic exposure data.

5 Problems to be Solved by the Invention In a camera in which the shutter speed and aperture value are calculated by a CPU using a microconopinita according to the side light results, and the calculation results are displayed on a display device, the CPU
In order for U to proceed with the program according to a fixed routine, data communication with the display circuit must also be carried out at fixed intervals. but,
When normal information cannot be obtained, such as immediately after photometry starts, there is no data to be communicated.

If the display device displays data other than the data to be displayed during this time, the notware used in the CP tJ to create the display data becomes complicated.

Purpose of the invention This invention was made to solve the above-mentioned problem, and when the data to be properly displayed cannot be obtained, the CPU program can be simplified by erasing the display of unnecessary data and symbols. The purpose is to provide display devices for cameras.

Structure of the Invention The second invention provides a camera operation control CPU that determines between sleeve state and operation state, display means that displays various operation modes and their contents, and display control circuit that controls the display of the display means. However, the display data of the display means is created by the CPU, the data is transferred to the display control circuit, and at least the first display data sent from the CPU to the display control circuit when the CPU rises from the sleep state to the operating state is turned off or in standby. It is characterized by being display data.

In this specification, the sleeve state refers to a state including a CPU stop state and a standby state.

Embodiment FIG. 1 is a diagram showing the external appearance of a camera to which this invention is applied. 1 is a camera body, 2 is a glossy lens, 3 is an interchangeable lens lever, and inside the 9-point lens 3 is the data of the lens, for example, the aperture. A device is provided that outputs data indicating the aperture value and the like to the camera main unit 1 as an electrical signal. Further, the Noyatsutabotano 2 is provided with a photometry switch S1 and a release switch S2, which operate according to the amount of button depression, using a known method.

Reference numeral 4 denotes an external display section, which displays the calculated Bv value and various other data, which will be described in detail later, according to the operation mode.

5 is a finder, and within the field of view of this finder 5 is provided an internal display section 6 (see pQ in FIG. 2) for displaying data and the like displayed on the external display section 4.

SM is the main switch.

FIG. 2 shows details of the display of the external display KI4, or PROGrtAMS for AE momo display from above. A
When E mode is program mode (hereinafter referred to as P mode), PROGRAM is displayed and S is turned off, and when in aperture priority mode (hereinafter referred to as A mode), A is displayed and PR
Turn off OCR and MS. Manual mode (hereinafter referred to as M mode) and shutter speed priority mode (hereinafter referred to as S mode)
(referred to as mode), M and S are displayed respectively. Below that is the SO mark in ISOS-mode, and immediately below it is 7.
There is a 4-digit segment SS, ISO, and CTR display, and on the right side there is a setting instruction mark TAI. Below that, there is a bar display that only turns off when the camera's main switch SM is turned off, and a 7-segment, 2-digit F, +/- display, and to the right of it is a setting display. There is an instruction mark TA2. To the left of the two digits is an aperture value discrimination mark F, and further to the left end is a +/- mark, which is a sign when setting an override.

Furthermore, FIG. 2C shows details of the display on the internal display section 6.
Starting from the left end, there are 2 adjacent images for displaying camera shake (camera shake).
Mark CAI has two camera shapes.

There is CA2, followed by 7 segment 4 digit SS.

There are ISO and CTR display sections, and then there are S, P, and A for E-mode display. The S mark consists of a 7-segment arrow pointing toward the 4-digit side to indicate glossy second priority.
Similarly, the A mark is located immediately to the right to indicate aperture priority.
The 6P mark, which consists of an arrow pointing toward the 2-digit segment side, has nothing to do with prioritizing both aperture and seconds, so there is no arrow between S and A. The two 7-segment notes on the right side for the AE momo display display the F value and -1-/in +/- mode.
-Display the value. Immediately to the right of it is the M mark for the AE momo display. This is because the metered manual display lights up at the same time, so it is displayed on the meter display to make it easier to understand. On the right side, there is a foot mark, which is the symbol for override and metered manual, followed by #! which consists of 7 segments. ! , the value range is located. This numerical value band displays +/- values during AE mode (P, A.

(Only in S mode) and also displays the metered manual value in <AE mode (Only in M mode).

Finally, ASI and ΔS2 that can be displayed in ijl+light mode
There is a mark. During average metering, only ASI lights up, and during partial metering, both ASI and AS2 light up.

Fig. 32 a, b and Fig. 33 a, b are showing the override, but the place where the override value is displayed in the InnoFinder internal display is the override (+/-
) mode and AE mode. This is an attempt to display the birch tree near the center of the display area so that it can be more clearly seen during the override mode display.

FIG. 3 shows the overall configuration of the control device related to the above-mentioned camera display. CPU+O using a central control microcomputer that controls the operation of the entire camera is 1 from battery I+! Atom E is supplied to the main switch SM, which is pulled up by a resistor R, a reference oscillator XL1 for operating the CPU10, and a group of control signals to peripheral circuits (particularly regarding the display).

C-block, FW connects the Norial data 5DATA and Norial Cloth Book SCK necessary for Norial transfer of data to the surrounding area.

An outline of the operation of CPLIIO will be described later.

On the other hand, the display circuit section 20 receives signals d1-. Do W
C, 5DATA, SCK, reference oscillator XL2, and LCD drive reference 1/21 are input, and the output is as follows.
There is a drive output group for the common and segment electrodes of the external display section 4 and the internal display section 6 using a liquid crystal display. The drive output terminal group is connected to the external display section 4 of the camera and the external display section 6 inside the finder, which are connected in parallel.

Inside the display circuit 20, there is a data latch section 22 that latches norial data. A decoder unit 23 that decodes the matched data. Segment driver unit 2 that drives the LCDs of external and internal display units 4 and 6 using decoded signals
4. Common driver section 25 that drives the common section of the LCD
．． Oscillation frequency dividing section 26 that creates operating clocks for each section. L.C.
There is a voltage generator 1127 that generates the driving voltage of D.

FIG. 4 is a detailed diagram of the oscillation section 11 section 26 in FIG.
It consists of a frequency dividing stage composed of FI). The flip-flop FFI is provided with a reset terminal R, which is initialized when a battery is installed.

Figure 5 is a detailed diagram of the common driver W825.
0. VLCD2. VDD voltage analog switch ASI-AS4 and PchFET FPl, FP2
Through φ,, φ1. C0M1.00M at the timing of
It has a birch configuration that outputs to 2. Nantes Gate NA1.2
The NOR gates NR1 and NR2 and the inverter IN3.4 are gates for creating timing, respectively.

FIG. 6 is a part of a detailed diagram of the segment driver section 24,
VLCD2. Analog switch AS5 and PchFET EP3 for switching each voltage of VDD are φ1. Of the timing of φ1°, segment data S2n, 52n-
It is configured to be driven according to the state of 1. Nantes Gate NA3 to NA7 and Impark IN6.7 are S2n
, 52n-1 constitute a clock selector, and the inverter INS and flip-flop FF2 are connected to φ1. It constitutes a clock generator for creating a clock with a phase difference of 4N from φ1°.

The entire segment driver section is of the type shown in FIG. 6 in which only the clock selector, analog switch, and PchFET portions are provided with SEG output terminals, and a clock selector is added.

FIG. 7 is a detailed diagram of the data latch unit 22, and there are seven 8-bit forward switches SRI to SR7 that receive 5 DATA of normal data from CPolo, and the parallel outputs of these forward switches are latched at the falling edge of the LTCH signal. 7 8 pits draft LTI~L T
7 is connected.

The reset R manual power is applied to the 1st LTI IO data, and the set S manual power is applied to the jll data, and the Taniyako IO data and 11 data are reset and set by the power ON reset FOR signal. Ru. Therefore, the initial state is jlO=-Lov-, j I I = ”
High”.

On the other hand, the serial clock SCK from the outside is passed through the OR gate OR+ as a φS signal.
9, and also serves as the φλ power of the counter decoder CD. When the set manual power S of the counter decoder CD is “°High”, the output BSI of the counter decoder CD
~ BS7 are all 1 High", and when the S input becomes hvLo", BSI or 98 is sequentially set every 8 pulses of φλ force.
One up to S7 becomes Lov7.

When any one of BSI to BS7 is “Low@”,
One of the corresponding NOR gates NR3 to NR9 becomes active, and the φS signal, which is the input of the NOR gate, is transferred to one of the Norial registers 5RI to SR7.
Enter the λ force. The external control signals DO and D from cPUlo are logically summed by an OR gate OR3 to become a p-cs signal, which is input to the other input of the ORI and the S input of the counter decoder. Also, it becomes one input of OR gate OR2, and the other human power BS7
An OR logic is performed with these, and this becomes the D input of the flip 70 block FF3 and one input of the Nant gate NA8. In the flip-flop FF3, the FOR signal is input to the set input S, and the η output is connected to the other input of NA8. or,
φ and the output of FIG. 4 are connected to the φλ force of the flip-flop FP3.

FIG. 8 is a detailed block diagram of the decoder section 23 shown in FIG. 3, and shows switch circuits SWI, SW2 . Data converter DCI to DC
4. Segment decoder sections SDI to SD6. It is composed of an output control section CTLI. The switch circuit SWI has the outputs j12 to j of the decoder 22 as human power.
16. j22-j27. j32-j37. j4
25 outputs j50 to j53 of the decoder 22 are input to the data conversion unit DC3, and outputs IO and jll of the decoder 22 are input to the data conversion unit DC4.

+20. +21. j54-j57. j60～j67゜J
A total of 53 pieces of 24 pieces from 70 to j77 are in the second L in Figure 7.
It is connected to the outputs of TI to LT7. In addition, the data R switching unit DC4 receives the main switch signals SM and vWτ shown in Figure 3.
There are two inputs. Output controller ll8cTL
From Fig. 4, φ, 4 is connected to I as an input,
Seventy outputs of 5l-S70 are connected to the segment driver section 24.

FIG. 9 is a detailed diagram of the switch circuit SWI in FIG. 8,
jn from data latch 22 (dos 12 to 47 (however, l
7, 20.21.30.31 are excluded)) - Pn (n
= l 2 to 47 (excluding +7.20, 30°31)) using 25 Nant gate NAs, F'OM, CTR, ISO.

It is switched by the SS signal. FON, CTR.

When the ISO and SS signals are 1L01°, the Pn signal is “
High” and the jn signal is cut off, but the FON.

When the CTR, IsO, and SS signals are “High”, Pn
= jn, and the switch is turned on.

FIG. 10 is a diagram explaining the symbols used in FIG. 1t, FIG. 13rA to FIG. 15, and FIG.

For each input of D, by placing an O mark at the intersection of the arrow with the output Q, it indicates the same function as the Nantes gate, that is, Q
=B-D.

FIG. 11 is a detailed diagram of the data conversion unit DC3 in FIG.
The logic of outputs p1 to p9 is shown for inputs 350 to j53. This output serves as an input to the switch circuit SW2 shown in FIG.

FIG. 12 is a detailed diagram of the switch circuit SW2 of FIG. 8, and represents the logic in which the input pi-99 is switched to q71 to q7g and QB2 to Q89 by the switching signal MON and the +/-ON signal. The input p signal enters the Nantes gate,
When the switching signal MON and +/-ON signal are "Low", the output q signal becomes °High and the p signal is cut off.MO
When the N,+/-ON signal is "High", the output q signal becomes equal to the input p signal, and the switch is turned on.

Figure 13 shows the segment decoder ff1sD in Figure '148.
In the detailed diagram of 1-5D4, output "
1 to 29. This figure shows the segment decoder units SDI to SD4 in the same drawing because their basic configurations are the same, but SDI to SD4 are different, so the necessary parts are extracted from this figure. This output is powered by the output control unit CTLI shown in FIG.

FIG. 14 is a detailed diagram of the data converter DC2 in FIG. 8, showing the logic of outputs q40 to q62 for human input p12 to p16. The zero output is the segment decoder SD in FIG.
5 input.

FIG. 15 is a detailed diagram of the segment decoder section SD5 of FIG. 8, in which inputs q40 to q62. For Q7 to q78゛, the zero output showing the logic of outputs r30 to r43 is the output control in Figure 8! It is input to Il+CTLI.

FIG. 16 is a part of a detailed diagram of the output control unit CTLl shown in FIG. 8, and shows the segment decoder IsD! The output of 5l-S70 is obtained by the output of ~SD6, data conversion IDc4, and clock φ,4.

In this figure, r2n and Ba are shown in arbitrary combinations, but in reality they are connected in the combinations shown in Table 1.

Table 1 shows a truth table by replacing the circuit diagram of FIG. 16a with logical expressions. Furthermore, a combination of r2n and 81 is specifically shown. (1≦1≦8).

(1≦20≦68) r69 is shown in FIG.

Figure 16 shows the logic to input ``69'' and outputs s69.s70.

FIG. 17 shows the relationship between the outputs 91 to Q39 of the data conversion unit DC1 of the decoder unit 23 and the characters displayed on the display units 4 and 6. The data conversion unit DC! Inputs p22 to p
27. p32-p37, p40-p47. When q1 to q39 are output according to the state of CTR, qt to Q3
The displayed character is @ controlled depending on the state of 9, "L ov" or 'High'.

That is, the output q! If q2 is 'High', the SDI is displayed. Therefore, the display unit 4 (and 6) at the 10@ digit is 0° If q2 is 'High', the IOo digit is 2. Tsuyabuta J1]L' For SS value, p22-p2
7. [For the 50 value, data is given in p32 to p37, and for the CTR value, data is given in p40 to p47 and the CTR signal. Also, p22-p27゜p32-p37, p
The configuration is such that when all of p40 to p47 are "High", no output is produced for that data. Therefore, for example, p22~ for the Shabuta speed SS value
When p27 data is available, other p32 to p37.
It is composed of a data converter DC4 and a switch circuit SWl so that p40 to p47 are all set to High'''. (See Figures 9 and 21) The contents that can be displayed are illustrated in Figure 18. There are 361 types of SS values, 31 types of ISO values, and 100 types of CTR values.

19 and 20 are diagrams showing the relationship between the data of data conversion II (DC2 and switch circuit SW2 and the characters displayed on display units 4 and 6), and the input of data conversion unit DC2, p12 to p16 and , SW2 pi~p9, MON
, q40 to Q62. depending on the +/-ON state. Q71～
q78. The outputs of Q82 to q89 output data as shown in this figure. p12 to pi 6 for F value, p for override ia and metered manual value
Data are given on pages 1 to 9.

FIG. 21 is a part of a detailed diagram of the data converter DC4 of FIG. 8, showing switch switching signals MON, +/-ON, FON of switch circuits SWI and SW2.

CTR, Tomiso, ss logic and CTLI section ON,
The logic of the OFF signal and the logic of the OFF V LCD signal applied to the voltage generator 27 in FIG. 3 are shown, respectively.

The input signals are the output signals jlo and jl of the data latch section.
1. 355. Ko56. j60～j
67゜j70. j71 & outside ffi (K issue,
SM, PWτ.

FIG. 22 is a part of a detailed diagram of the data conversion section DC4 in FIG. 'i48, and shows the logic of the B1-B8 signal of the CTLI section. The human input signal is the output signal j20. of the data latch section. j
55-j57. j61 to j64° | j70 = j74 and external signal FW.

FIG. 23 is a part of a detailed diagram of the data converter DC4 of FIG. 8, and shows the logic of the r51 to r69 signals of the control unit CTLI. The input signal is the output signal j of the data latch section
21. j54～】57゜】70～373. j7s~
j77 and the output signal 940 of the DD2 section. and external signal 7
It is WC. 21 to 23 include all the data conversion section DC4 of FIG. 8.

FIG. 24 is a detailed diagram of the voltage generating section 27. Diode D externally! By creating a reference voltage VLCD by inserting a resistor R1 between +E and CND, and supplying it to the booster circuit 27a (encircled by a broken line) including a capacitor CI+C1, a voltage doubled (+E -VLCD) is obtained. 10E-V L
CD1) is generated. Both VLCD and VLCD1 are led to VLCD0 and VLCD2, respectively, by an output control circuit made of an analog switch and a PchFET.

V LCD0 and V LCD2 are in the state of 0FFVLCD
The output changes accordingly. OF F V LCD? L
ow”, V LCD0 = V LCD,
V LCD2 = V LCDI, 0FFV
When the LCD is °High”17), V LCD0 =
V LCD2 = V DD.

Further, the booster circuit ff127a obtains a clock from φ in FIG. 8 to switch the connections of the converters C, , C, and performs boosting. Also, Po is a terminal for starting the booster circuit, and is started by the Po1l output shown in FIG.

FIG. 26 is a time chart of the data latch section 22 of FIG. 7. External signals pwc and cs both become “Low”, and at the falling edge of SCK, the Norial Renostar SRI~S
The data in R7 will be rewritten.

All the contents of SRI are written at the falling edge of the first 8th pulse of SCK, and from the 9th pulse onwards, they are rewritten every 8 pulses in order from shift renostas SR2 to SR7.
, BS7 becomes 01° at the rising edge of the 49th pulse immediately after SR6 is rewritten, and at the same time as SR7 rewriting begins, flip-flop FF3 reads the D input at the rising edge of φ, so the compatibility of FF3 is changed. -The output is °L
OW” and does not change until BS7 becomes “High” again.

The output and the P-C5 signal create an L T CH pulse that causes the contents of the 5rLI-5117 real register to be loaded into the latch of the LTI-LT7.

FIG. 25 is a time chart showing the overall general operation from after the battery is installed in the camera. Battery installation 11! The rear display circuit section 20 is initialized by the FOR signal. signal V
LCtll becomes ground CND level, OF F V
LCD h< @High”. Therefore, no voltage is applied to the liquid crystal. After that, CPU I 0
(7) XL1 starts oscillating, and CPU10 starts operating. After a while, the oscillator X of the display circuit section 20
L2 starts oscillating and clock φ.

~φ3. starts to start. When the clock φ starts operating, the data latch section 22 starts operating, and when the norial data comes from cPUIO, it operates as shown in FIG. 26. When the clock φ starts operating, the voltage generating section 27 shown in FIG. 24 starts operating, and after a short period of time, the potential of the signal VLCDI becomes stable. After that, if you set 0FFVLCD to °Ow° as necessary, the liquid crystal drive voltage, V LCDQ. V
LCD 2 is supplied to display sections 4 and 6.

28 to 35 and 37 to 39 show various display modes of the external display section 4 and the internal display ff16. The figure shows the display on the internal display section 6.

Figures 28a and 28b are AE displays in program mode,
The auto second time is 1/250, the auto aperture value is 5°6, and the program PROGRAM is displayed.

The mark ASI at the right end of FIG. 28 indicates the photometry mode and indicates average photometry.

Figures 129a and b are the AE display in aperture priority mode, and when the calibration setting mark is pressed, the set aperture value is 5.6 and the auto second time is 1/250, and the aperture priority A and D represent the AE mode. .

Figures 30a and 30b are AE displays in the Tsuyabuta time priority mode. Set the glossy seconds setting mark and set the glossy seconds f
It shows at/250 and auto aperture value of 5°6, and AE mode is represented by S and 9, which give priority to the time.

FIGS. 31a and 31b are AE displays in manual mode.

The glossy second time and aperture value setting mark indicates the set glossy second time value of 8'' and the set aperture value of 14, and the manual mode M and the figure represent the AE mode. The right end of the internal display is the partial metering mark for the metering mode, and the left side is the error amount of the manual setting value against the appropriate value, which is the so-called metered manual indication value, +6.5EV.
The mark on the left end is a mark indicating a camera shake (hand shake) warning, and the two marks are lit alternately.

FIGS. 32a and 32b are displays during override setting. It represents the override direction + and the absolute amount 1.5EV.

FIGS. 33a and 33b show the AE mode display after override setting. Compared to FIG. 28, ten override directions have been added. Further, the internal display also displays the absolute value of 1.5 EV of N override. However, +1.5 is blinking on the internal display.

FIGS. 34a and 34b are ISO setting display.

The IsO mark and ISO value 100 are displayed.

However, the IsO mark does not light up on the internal display.

FIGS. 37a and 37b show hand shake (camera shake) warning displays. On the internal display section 6, mark CA on the leftmost camera
1. CA2 lights up alternately to indicate movement.

FIG. 37C shows the display on the external display section 4.

FIG. 35 is a display in Stanopie mode.

Only the bar display was dimmed, and all other lights were off. Functions other than camera display are in a stopped state.

<Operation Description> - Overall Operation - The basic operation of the display circuit 320 will be explained. When a DC voltage of 10 E is supplied from the power supply 11, the momentary FOR signal generated by the power-on reset circuit 40 (right end in FIG. 4) causes the flip-flop FF l of the frequency dividing stage to be supplied.
(FIG. 4), the clock generator's flip 70 FF2 of the segment note driver 124 (FIG. 6), the data latch circuit 23's flip 70 FF3. Latch LTI (Figure 7), starting FET 27 of voltage generator 27
b (FIG. 24) are each set to an initial state. Latch L
At T1, each data terminal is jlo="Low".

Ko! 1 = “High”. flip flop FFI
.

In FF2, set the output state to Q = “Lov” and Q = “Hi”
Set the output state to Q=”High in FF3.
h”.

Set ζ=“Lov”. [In the pressure generating section 27, FET
27h is momentarily turned on, the capacitor C1 is charged with electric charge, and the level of VLCDI becomes the GND level. In this state, since the crystal oscillator XL2 of the oscillator 41 (Fig. 4) has not started oscillating, there is no circuit operation at all, and the oscillation rise of XL2 ( Waiting for the oscillation rise of =φ. On the other hand, VDD, VLD2°V LDO are given in an undefined state through COM and 5EGi to the CD display side of the external display [4 and 6].
I is VLCD2゜C0M2 is VLCDO, 5EGn is
VDD or VLC depending on the state of S2n and 52n-1
D2) O F F VLC input to the a pressure generating section 27
Dh(j IO=”Low”, jl 1=”Hi
Due to the initial setting of ``high'', the AND gate A50° is set to ``High'' via the inverter 150 and the OR gate 050.
2=VLCDO=VDD, inner and outer display [L of 4 and 6
The voltages applied to each terminal of the CD display are equal, and there is no direct current voltage application that is harmful to the liquid crystal.

Next, the crystal oscillator XL2 starts oscillating, and φ. When a clock enters the flip-flop FFI in the frequency dividing stage, each part finally starts operating.

The clock φ enters the flip-flop FF3 of the data latch section 22 and serves to generate an LTCH pulse when the free data communication from CPLIIO starts.

The clock φ enters the booster circuit of the voltage generator 27, and C1
, C2 is used to perform voltage boosting operation.

Clock φ1. φ,. is a common driver! 1ffi25
The segment driver section was installed for two days and became the clock for the LCD drive wave.

The clock φ, 4 is input to the output control unit CTLI of the decoder unit 23 and is used to control the blinking portion of the display content.

The operation after the rise of the oscillation of the crystal oscillator WXL2 is first explained by the voltage generator 27. The clock φ input to the booster circuit 27a in FIG. 24 starts boosting operation, and the initial VLCD
What happened at the ILCD display level (V DD-2V
(LCD) level to avoid stabilization. From then on,
It continues to work without interruption until the power supply voltage drops and it stops operating, or the oscillation circuit stops, causing the lifting and lowering operation to stop. On the other hand, clock φ! The data latch circuit 22, which started operating due to
Ma°.

At the moment when a signal other than 'H1gh' is input and latched, the OFFV LCD becomes ``o'' and the analog switch on the right side of Fig. 24 switches, and VT, cD2
=VLCD1. VLCDO=VLCD, which wait for the output of common driver 25. The voltage is guided by the segment driver 24 and applied to the LCD display of the inner and outer display sections 4.6 as a voltage for driving the liquid crystal, and a liquid crystal display is performed based on the latched data.

Next, the data latch unit 22 will be explained with reference to FIG. 26. This circuit starts operating when both the pwc and cs multiplied signals become °Low'. WC is, for example, a timing signal for supplying power to a photometry circuit of a camera (not shown),
The photometry circuit starts operating when PWτ=“Lov”. Further, σ is a signal that determines the other party for the communication of the real data, and one signal is output from the CPU10 to other circuits in the camera (not shown).CS
="Sov@ selects the other party for Norial data communication.

PWτ, when either of the three guns is “High”, P・C
5 signal is "High", the counter decoder CD is set, and all BSI to BS7 outputs are set to High.
”, and the output φS of the OR gate ORI is °H
NA8 output LTC
H et al. are “High”. Both PWC and C5 are “L”
ov'', the counter decoder CD enters the operating state, and the OR gate ORI and OR gate OR2 open.
The SCK and BS7 signals become detectable. At the rising edge when the first pulse of SCK is input, BSI becomes "Low" and NOR gate NR3 opens. At the falling edge of the !th pulse, the φλ force of shift register SRI rises, so the 5D at that time
Load the contents of ATA into only one shift register SRI. The data at this time is jlo.The second pulse comes at the 0th order and the same operation is repeated.At the falling edge of the 8th pulse,
8 gl of data are taken into the shift register SRI, and the 8th data is called j17. Until this time, the signal BSI is 0 and 01°.

When the next 9th pulse rises, BSI goes high, BS2 goes to LO low, NOAR gate NR3 closes, and NOAH gate NR4 opens. Since the φλ force of shift register SR2 rises at the fall of the 9th pulse, 5DATA at that time
The shift register SR2 takes in only one content. The data at this time is j20. From then on, proceed in the same way, and the 49th
At the rising edge of the first pulse, BS6 becomes “High” and the BS
7 becomes °shiOw°, Noah Gate NR8 closes, and Noah Gate NR9 opens. Furthermore, the output of OR gate 0f (2 is °Low.

The contents of shift register SR7 are taken in from j70 to j77 up to the 56th pulse, but after the first pulse and up to the 56th pulse, the TCH output is °Hi.
gh” remains, and the data is not latched from each shift register SR and taken into T. In other words, the OR gate OR2 opened at the 49th pulse
The output of 2 becomes "L ov", but the rise of the clock φ causes the flip-flop FF3 to go to +Lo of zero.
The ζ output changes to ``High.'' However, the other input of the Nant gate NA8 becomes ``L ov'' before the ζ output changes.
The CH output remains "High".

Here, the output of the OR gate OR2 becomes "High" depending on whether the 57th pulse comes or whether either pwc or cs becomes "High". At this moment, the 1 output of the flip-flop FF3, which is the other input of the Nands gate NA8, is High-, so the output of the Nands gate NA8 is L.
TCH becomes L ov'. This “High--”Lo
The falling edge of "t" is the signal for latch.The data that was stored at 1 o'clock in Rinft Renosta SRI~5rt7 is LT.
It is latched into the data memory of I to LT7. After that, flip-flop FF3 is set to D by the rise of clock φ.
The input °lligh is taken in, and the σ output is “Low”.
”, and Kaunota decoder CD is pwc, cs
is set to "High", and each returns to its initial state.

The above is the operation IEI of the data latch. If the number of clock bytes for Norial data communication is insufficient, the last latch pulse LTCH will not be output, so no data error will occur, and even if the number of clock bytes exceeds, it will be automatically cut off at the 57th pulse. Naturally, no abnormalities occur, and since the clock within the same byte is routed to the sending CPU without interruption, abnormalities in data communication are completely prevented.

On the other hand, even if the external signals PWC, CS, SCK, and 5DATA operate normally, if the internal φ is not operating, T
CH pulse stopped coming out, notrenosufu 5rtl-5
It becomes impossible to latch the data captured in l(7) to latches LTI to LT7. This is because when φ is not operating, the liquid crystal drive waveform indicates that it does not operate, and the DC voltage is applied to the liquid crystal. Therefore, at that time, jl O = “Low”, jl l =”
It is necessary to maintain the voltage at 0FFVLCD and set 0FFVLCD to "High" so that no voltage is applied to the liquid crystal.For this reason, external data is not taken in when the clock φ is not operating.

Next, the common driver section 25 and the segment driver section 2
I will explain about 4.

In Figures 5, 6, and 27, Nant Gate N
AI, NA2. Noah Gate NrL1. NR2, inverter IN3. The analog switch ASI-AS4゜Pch FET FPl,
Controls each switch of FP2. The input signals of the gate circuit are φ, φ1. , and due to this timing, C0M
2. The output of COMI changes as shown in Fig. 27. Signals C0M2 and COMI are clocks φ,. of! This is the same as the first period, and there is a shift of 1/4 period from each other.

The output value has three levels: VDD, VLCD0, and VLCD2.

In Figure 6, the inverter! Four types of clocks generated by clocks φI and φ1o processed by a clock generator consisting of N5 and flip-flop FF2 are selected by a clock selector consisting of Nant gates NA3 to NA7. The selection conditions are S2n,
52n-1, and by this condition, 5E
The output waveform of Gn is determined.

This state is shown in FIG. 27, and each state is different depending on four types of states determined by S2n and 52n-1.

The period is the same as the clock φ1°, and there is a difference of 1/4 period from each other. The output values are VDD and V
It has two LCD levels. Signal C0M1.
The potential difference between 2 and segment signal 5EGn is 2 X V
1. The LCD display lights up depending on the waveform of the portion that becomes CD2. 5EGn (LH), 5EG for COMI
The segment of the LCD display to which a voltage of n (HH) is applied lights up, and 5EGn (HL
), 5EGn (HH) voltage is applied and Cb
The display segment lights up. For 5ECn (LL), the segment will not light up even for COMI and C0M2.

In other words, the 52n-1 signal is the vI control signal that lights up the segment for COMI, and the 52n-lx'Lrow
”, it is OFF, and when 52n-1='High', it is O.
The S2n signal is a signal that controls lighting of the segment for C0M2, and is OFF when 52n="Low" and ON when 52n="High".

Data latched in Figure 7 j10~j17゜j20~
j27. j30-j37. j40～j47゜j50～j
57. j60-j67,. 70-j77 is 07. j3
0. All bits except 3 bits of j31 are input to the decoder section shown in FIG. SW I.

SW2°DCI to DC4,5DI-SC2 are simply gate circuits and have no timing relation at all.

The explanation is below.

First, the contents of the real data will be explained.

jlo and jll are signals that control the supply of liquid crystal drive voltage, J10="LO 豐", jl l ='High
The liquid crystal driving voltage stops only at h°, and the voltage applied to the liquid crystal becomes 0.

j12 to 316 are data signals regarding the aperture value of the camera (
9, 14, 15, and 22 (IKt), and there are 231jii. Also, 312 to j16 are all “H”
Nothing is displayed when the display is set to "high".

j20 is a signal related to a warning of insufficient battery voltage in the camera (see Figure 22), and j20="High"
”, all the displays displayed are φ,.

Repeats blinking at a period determined by .

j21 is a hand shake (camera shake) warning signal (see FIG. 23), which becomes ")1high" when the shutter speed becomes slower than near the limit that causes hand shake (camera shake). At this time, the camera shake mark CA1 on the internal display section 6 in the viewfinder. CA2 lights up alternately.

”22 to j27 are data signals (
(see Figures 9, 13, 17, and 18),
There are 36 types. Also, j22~J27 will continue “Ili
gh”, no display appears.

j32 to j37 are data signals related to 150 values of film sensitivity (FIGS. 9, 13, and 17).

(see Figure 18), and there are 31 types. Also, j32~j
When all 37 are 'High', no display appears.

j40 to j47 are data signals (
(see Figures 9, 13, 17, and 18),
There are 100 types from 0 to 99.

Further, when all of j40 to j47 are "High", nothing is displayed.

j50 to ko53 are data signals regarding the override value and the deviation amount of the metered manual (see Figures 11 and 12. "1419.20), and there are 9 types of override values depending on the content to be displayed. The metered manual deviation amount li!l 4p1 is switched and CP
Sent from LJ. j50 to j53 are all 'Hi'
gh", nothing is displayed. For switching the display contents, the receiver has signals j55 and j56 (described later).

354 to j56 are 5IGN signals (see Figures 21, 22, and 23) related to the override value, the sign of the metered manual deviation amount, and signal switching, and j54 is "+" and r - a signal regarding the sign of J;
j55 and j56 are signals for switching data between the override value and the metered manual deviation amount for each external display and internal display.

j57 is a signal used to display the so-called preview moment (see Figures 22 and 23), which is used to check the depth of field by narrowing down the lens aperture before taking a picture. This signal becomes °High', and the 40 calibration mark F on the external display flashes and the set number (
A-band instruction mark TAI.

Controls the lighting of the bar at TA2.

j60 has a +50 display priority signal l5OPR1t'. This means that the main switch SM is OFF and 0FFVL
Is the CD signal "High"?? Yes, the LCD drive voltage has stopped, and when this signal becomes "High", the 0FFV LCD signal is set so that the LCD drive voltage is supplied to the segment driver 24 and common driver 25. Lo
Let's try it. (See FIG. 21) This signal is not used alone, but the data of the ISO display mode and ISO value are sent from the CPU 10 at the same time as this signal. In terms of camera operation, this is the state immediately after the battery is installed.

j61 is the deviation m of the metered manual M'dMOVl
This is a flashing signal (see Figure 22), and this signal is °High.
The deviation value of the metered manual flashes with h-.

j62 is the shift signal 5HIF for blinking the program mode mark during the shift of the camera's program mode.
(see TC Figure 22), and this mark blinks when j62 is "High". Here, the shift refers to a state in which the combination of the aperture value and the shutter speed value in the program mode is changed to avoid operation. Incidentally, all AE motes can be blinked as necessary, regardless of the program mode.

Noro 3 is the control interlocked warning signal Not, C0NT (21st
(see figure), and this signal goes High when an exposure value that exceeds the aperture value and second value that the camera can control is required.
”, and the calibration value and /nu are the seconds value, and the numerical value on the calculation control value side flashes according to the AE mode, giving a warning.

j64 is a brightness change interlocking warning signal BV (see Figure 22), and this signal becomes ``°High'' when the Fi degree value exceeds the brightness value that the camera can measure, and the ASI during the photometry mode display. and AS2 flashes to warn you.

j65 is the bulb time signal BtJLB (see Figure 21), which is a signal for switching the 4-digit, 7-segment display content during bulb exposure from the glossy seconds display (buLb) to the bulb exposure seconds count display. Press - to display the valve count and display the contents of j40 to j47.

Noro 6 has all lights off signal LLOFF (see Figure 21!!Q)
The waveform of the SEG pane for driving is controlled to be OFF waveform (see No. 27 [i'05EGn (LL))]. When the power is turned off, the OFF display will appear. However, the camera mark CA1. CA2 cannot be controlled.

] 67 is the all-lighting signal AI, LON (see Fig. 21), which turns all the waveforms of the SEG terminal for driving into ON waveforms (second
7 (see Figure 5EGn (Hll))), and all are displayed as ON at "°lligh".

However, the camera mark CA1. CA2 cannot be controlled.

j70.371 is the camera operation mode signal CALL M
ODE (see Figures 19, 20, and 21), normal AE mode, 5TANDBY mode in which the main switch SM is ON and the camera is not operating, 150 mode for ISO setting and display, +/ +/ for general settings/display
- There are four modes, and the display contents are switched according to each mode. (See Figures 28 to 35) j7
2. Core 3 is the camera's AE mode signal AEMODE
(See FIGS. 22 and 23), and there are four states: program mode, aperture priority mode, glossy seconds priority mode, and manual setting mode, and the display contents are switched according to each signal.

"74 is the IsO output when prompting to set the ISO value.
This is the kidney warning signal ISOARM (see Figure 22), and when this signal goes high, the
The mark and ISO value flash.

j75 is the mode off signal MODE OFF C (see Figure 23), and when the main signal goes high, the AE mode display that is being displayed goes out.The mode display is displayed when the film is not fed when loading film into the camera. OF
Make it F.

j76, j77+i Photometry mode switching signal AVE/5PO
T (see Figure 23), and when the partial metering mode is selected between the average metering mode and the partial metering mode (either or one of j76 and 377 is
) Turn on AS2 on the internal display section 6 of the finder. ASI is always lit during B mode.

DC4 also uses 1 as data in the external signals SM and PW, and performs data code conversion ff5 (Fig. 23) and display section 4.6 for displaying positions other than the number of seconds, aperture value, etc.
Decoding KI (Fig. 22) for blinking control of each display segment of the Noshi CD display and two signal switching units SW
1. It is divided into three parts: decode wI (FIG. 21) regarding SW2.

Figure 21 is created mainly with the switching signals of SWI and SW2, and the FOM, CTR, ISO, SS signals 1tsW
L, MON,! /-ON signal controls SW2. In addition, the ON and OFF signals are instructions for controlling CTLI and displaying an ON display and an OFF display for all segments. Furthermore, the OF rr VLCD fx has the function of cutting off the liquid crystal drive power supply and the liquid crystal drive circuit when this f3 is "Illight".The purpose of this is to
Is it possible to prevent the direct voltage applied to the liquid crystal when the L2 primary oscillation is stopped, and to turn it off when the main switch SM of the camera is turned off? m force reduction. On the other hand, the CALL MODE signal j70. j
71 represents four camera operation modes, Noah 0.
37 + = AE for normal shooting when “High”
It's called a mode. j70・When Noah 1 = “High”, it is called ISO mode for ISO sensitivity setting. Core 0・j
71 = 5TAN in camera standby state when “High”
Called DBY mode, j70/j71 =-High
h” is called +/- mode for setting the override amount.

To explain the signals for SWI and SWZ according to the above four modes (see Figure 21), during AE mode, V
Wτ becomes “L ov” (the camera starts operating.

), the FON signal becomes "High", the SWI operates, and aperture value information j12 to j316 is selected and decoded and displayed. pwc becomes “High” (camera is on standby [
It goes into standby mode. ) and the FON signal is °L o
v'', and the aperture value information is erased by SWI.

On the other hand, when PWτh4"L, at-tej65 is "Low" (a always), the SS signal becomes High' and the shutter speed information j22 to J27 is selected and displayed. At this time, The other CTR signals and ISl"11i are "L ov", and the timer count information and IsO
Value information is erased by SWI.

i lever λrcbjiL ov- and j65 key High-1
In this case (during valve count), the CTR signal or "Hi"
gh” and timer count information j40 to j47 are selected and decoded and displayed. At this time, other SS signals,
The ISO signal is "Lov", and the ISO signal is
SO value information is erased by SWI.

Also, the +/-ON signal is “LO blind” or the MON signal is when PWC is “Low” and j50 or co56 data is “High”.
If it is "h", it is "High", so the value information of the metered manual deviation amount is selected and decoded and displayed by SW2, but the value information of the override is erased.

SS, CTR, FON, MON in ISOS mode.

+/-ON signals are all "Low", ISO signal is "High"), SW l h4 operates,
15Ola information] 32 to j37 are selected and decoded and displayed. At this time, other numerical bands are erased.

5 During TANDBY mode, SS, CTR, FON, r
The so, MON, and +/-ON signals are all "low", and all numerical bands are erased.

During +/- mode, SS, ISO, CTR, FON, M
All ON signals become "Low", and PWC becomes "Low".
When OW-, the +/-ON signal becomes "High".

At this time, override information items 50 to 53 are selected and decoded and displayed.

Figure 22 shows a control signal for the blinking display of each display segment. When the outputs 81 to B8 become ``High'', if the corresponding segment (see Table 1) is lit, that segment is Flashing.

The B8 signal is a signal that causes the F mark on the external display w34 to blink, and is mainly controlled by 357 data.

The B7 signal is the 7th segment of the CD on the internal display section 6.
This is a signal that flashes the numbers 8 and 8, and the col and 2 second digits between them, mainly j55. It is controlled by the data of j56 and j61.

The B6 signal is a signal for blinking ASI and AS2 on the internal display section 6, and is mainly controlled by ]64 data.

The B5 signal is a signal that blinks the external/internal display section 4.6, No. 5 and 6 of the 67th segment, col, and l, and is mainly controlled by the ]63 data.

The B4 signal is a signal that blinks the external/internal display section 4.6 and segments 1 to 4 of 67, and is $IIi mainly based on the data of 363 and j74.

The B3 signal is a signal that causes both the external and internal display sections 4.6 to flash, and is mainly controlled by 362 days.

The B2 signal is a signal that causes the 150 mark on the external display section 4 to blink and is mainly controlled by the data of j74.

The B1 signal is a signal that causes all segments other than the segments 88 to B2 to flash except for CAI and CA2, and there is no particular data signal. However, including Bl, blinking is controlled by j20 data from 82 to B8.

FIG. 23 shows a decoder for the segments excluding 1 to 8 and col, I, col, and 2 of the 7-segment note for displaying numbers in the inner/outer representation part 4.6. norial data j
54-j57. j70-j73. j75-j77, j2
1. The output is controlled by the external signal pw (-1) and the decoded DC2 output signal Q40, and the outputs range from r51 to r69, and when each output becomes "High", each corresponding segment lights up.

FIG. 9 shows SWI, which selects signals.

The input signals are the aperture values of j12 to j16, and the aperture values of j12 to j16.
These are the j270 glossy seconds value, the IsO value of j32 to j37, and the timer count value of J40 to j47, and there are a FON signal, CTR signal, ISO signal, and SS signal to select each of them. When each selection signal is “High”, it is NAND
The gate is opened and the output data becomes p=manual data J. On the other hand, when it is "Lot", the NAND gate is closed and the output data p becomes "High".

(Example) When FON is "High", outputs p12 to p16 transmit inputs N2 to j16 as they are.

When F ON = "Low", all outputs p12 to p16 become "High".

Next, is there a detailed diagram? I) I will explain CI.

DCI is serial data processed by SWI. j32-j37. j40~
p22-p27. corresponding to j47. I) 32-p3
7. This is a decoder that uses human power to operate p40 to p47 and outputs data of q1 to q39 corresponding to the 7-segment 4-digit part. Figure 17.

Figure 18 is for explaining the W1 inclusion of DCI, but the input data is 36 types of Tsuyatta second-second values (SS values) (buLb ~ l/4000) corresponding to p22 to p27 and A
LLHigh, ISOSDI corresponding to p32-p37
species (ls06-1506400) and ALLHigh,
100 types of timer count values (CTR values) (0° to 99") corresponding to p40 to p47 and A L L I
There is.

For example, data p27 corresponding to SS value rhaL bJ
~ p22 = When "Shishishishi LL" is input (at that time)
Ya's data p32-p37, p40-p47 are A L
Processed with DC4 and SWI to make it L High. ) The output data is q7 data °bゝ for segment decoder SDI, q18 data 0L'' for SO2, and Q29 data °U°, S for SO3.
Q39 data b for O4.

becomes.

Also, data p37 to p corresponding to +50 value r200J
32 = “When LHHHLL- is input, the pond data at that time p22-I)27.P40-p47 are ALLHigh
It is processed using DC4 and SWI so that it becomes h. ) Output J data is q1 data for segment decoder SDI, q8 data for SO2, q21 data for SO3, and no data is output for SO4.

Also, p22-p27, p32-p37. p40～
When ρ47 is "High", no output is output to the segment decoders SDI to SD4.

All segments for SDI to SD4 are turned off.

It is composed of a gate circuit having the above configuration.

Next, the segment decoders SDI to SD shown in the thirteenth [1]
4 will be explained. The data signals Ql to q39 obtained in the previous section are respectively 91 to q7 to SDI and q8 to q18 to SDI.
02, q19 to Q29 to SO3, and Q30 to q39 to SO4. The internals of SD1 to SD4 are basically the same, but among the 14 inputs, terminals to which no corresponding data signals are input are pulled up to the +74 source side in each block. The input of this circuit is configured so that an effective output can be obtained when it reaches °L ov".If it is fed, when the q7 data signal (b of buLb) is output to S01, the human power per mouth becomes L ov". At this time, other SDI
Inputs q1 to q6 & inputs that are pulled up are Hi
Outputs related to the line that is gh- but becomes “Low” (c), (d), (c), (r), (g)
ii becomes I-1l-1i'' and the other (a), (b
), (h) line is "Ql'. This output (c
), (d), (e), (r), (g) are S[]1
This corresponds to terminals r3 to r7, which are connected to the next stage CTL I and connected to the liquid crystal display. This "output corresponds almost one-to-one with the liquid crystal segment (Figure 16a,
(see Figure 2, c, Table 2). Output here (c), (d), (e), (D.

(g) corresponds to the numerical segment name of each of the 7 segments, and represents the letter r6J (see 1!Q in Figure 2).

Further, for example, for SC2, the q21 data signal (r
When 2 j) appears, the ■input becomes °L ov- (a)
.

(b), (d), (c), (g) are °Ilight
” Then the character “2” will be displayed.

p12 to p16 obtained by SWI enter the decoder DC2 shown in FIG. 14. p16~pI2=-L, LLLL"
The output at the time is q40, and a 'Low' output is output.

The output of Q40 goes to segment decoder SD5 while it goes to decoder DC4.

Other outputs are exclusively connected to SC5.

The contents of the outputs of q40 to q62 based on the data of p12 to p16 are the aperture v123 gods shown in the concept of SC5 shown in FIGS. 19 and 20. The SC shown in Figure 15
A segment decoder is performed using the manual power J[Kl of q40 to q62], and outputs of r30 to r43 are obtained.

For data files 50 to 53, the decoder D shown in FIG.
There is C3.ノ50 data is data below the decimal number,
A p+ ratio output of 22 is obtained.

The data j51 to j53 represent the information of O to 6, and their outputs are p3 to p9, and the output is in the active state at "High". This output is input to the switch SW2 in FIG. 12, and the selection information MON, Switch the output destination by +/-ON.When MON is °High, +/-ON is °L
ow”, and the outputs of p2 to p9 are inverted and q82
~Q89 is output, but q71-Q78 are all °
-power factor/' - When ON or High, MON is "Low" and the outputs of p1 to p7 are inverted and output to q71 to Q77, but q82 to Q
89 are all “High”, and q78 is °L
ow”.M ON.

When both +/-ON are "1. ow-, Q71-+
The outputs of +78°Q82 to q89 all become "High".

The output of SW2 is 471-47B to SC5, q82-q
89 is output to SC6.

q71 to q78. output by SW2. The contents of Q82 to Q89 are shown in Figures 19 and 20, and 971 to q7B contain seven types of numerical values for override values and decimal point IF! , q
82 to Q89 correspond to seven types of integer digit numerical values for metered manual values (including override values) and decimal display II.

Although the contents of SC6 are not shown, the basic idea is the same as that of 5DI-SO2 shown in FIG. 13, and is shown in FIG.

The gate configuration is such that there is a relationship between the data shown in FIG. 20 and the output display example.

Finally, 72 rl-r691 and B1-138. made by SDI~SD6 and DC4. ON, OFI signal,
Furthermore, when the clock of φ16 is input, the output control ff1cTL+ will be explained.

The structure of the CTLI internal meeting is already shown in FIG.

``69→S69.'' Except for the configuration of the 570 part, the configuration is basically as shown in Figure 16 a. Gate opening for S70 φ.

"High" and "Lov-" are repeated according to the clock, but S69 and 570 are output in opposite phases.This causes the corresponding CA1 and CA2 marks to light up alternately and the camera mark to shake. Gives a similar image.r6
Regarding circuits for signals other than 9, the logical formulas and truth tables showing the rA relationship between the output S and the input r are shown in Table 1.

This table shows that when the signal at σ becomes °LO, the output horn S is S69. All except S70 become "°1τhigh" and the display contents except for C, A1, and CA2 light up.

Next, when the σ signal is "It igh-" and the OFF signal becomes °High, all outputs S except S69.570 become 'Low', and all displays except CA1 and CA2 turn off. do.

ON signal is high, OFF signal is low
At time t-, when Em CU31-[3B) reaches zero, the output becomes S-r, and the display is lit in accordance with the display information given by the norial data.

Signal h< “High” on σ, OFF signal is Lo
w”, any part of Bm (Bl to B8) is DC
4, the output S corresponding to `` in the same group becomes Flashes depending on the displayed content.

For example, B6 signal Riji I(igh) means 81~ of that pond.
B5. B7. When the B8 signal is “L ov”, the corresponding outputs S59 of r59 and r6Q in the B6 signal group
and 560 repeats "High" and "Low".

However, if the states of r59 and r60 are °L ov", S59 and S60 cannot become °High". Therefore, As2 and A corresponding to S59 and S60
If S+ is lit, it will continue to blink.

Outputs 51 to 570 obtained by the above CTLI are each input to the segment note driver (Figure 76), and output as the liquid crystal drive waveform (see Figure 27) to the final output SEG terminal (SEGI-5EG35). .

The relationship between CTLI output S and SEG pancreas is shown in Table 2.

The names of the segments shown in this table are the same as the names of all segment notes shown in FIG. 2C.

-When starting the camera- When the camera is started by turning on the main switch SM, an interrupt is generated in CPU+O, the CPLIIO is released from the stopped state, and the camera starts operating according to the program in the internal ROM. At the same time, voltage is supplied to a photometric circuit (not shown), etc., but the photometric circuit etc. operate slowly and it takes several tens of seconds to provide the necessary data to the CPU 10.
time is required.

However, the CPU 10, which operates at high speed, performs the norial data communication with the display circuit section at least once at the second point in time. The content of the Norial data communication (see Figure 36) is mainly exposure information such as time and aperture value, but if the photometering circuit is not operating normally, these exposure information 'E An exact value cannot be obtained. Therefore, it is not a good idea to communicate norial data in this way, as it not only makes no sense but also results in erroneous display. Therefore, at startup, until the CPU10 takes in accurate information and completes the calculation, a troublesome inaccurate value is displayed on the display by sending data for turning off the light or data for standby display. In order to avoid this problem, the display unit of the embodiment has a structure that maintains the previous display unless new norial data is communicated. If you use this 11 and do not communicate norial data until the calculation is complete, there will be no particular problem, but the program 70- for CPU10 is created in such a way that it does not generate special cases as much as possible, so it is constant! The method of communicating the noreal data in the third stage is better as it does not increase the ROM capacity for the program. Therefore, the above method becomes better.

1: At the time of preliminary installation - Immediately after the battery is installed in the camera, a voltage of J-E is applied to the Cr'UIO and the display circuit section 20, and each starts operating. The ancient circuit has a separate water) ma.

Oscillator XL1. It has XL2 and starts operating independently, but in this case, since XLI has a higher frequency than XL2, generally XLI starts oscillating earlier. After the oscillation starts, the CPU10 starts operating according to the program in the internal ROM, but since there is little work to be done immediately after the battery is installed, it stops functioning after about -5ec, and stops functioning, and waits for it to wake up again. waiting. Generally, at this point, the oscillation of XL2 of the display circuit section 20 rises (generally 1
00-sec to Isee) is not guaranteed. When XI and 2 of the display section are not oscillated, Cr'UIO
We do not accept communication of 7 real data between the 7th
Since the clock φ shown in the figure is not generated, L TCI! does not operate according to the time chart shown in FIG. No pulse is generated. Further, even if XL2 is oscillating, the data in the display circuit section 20 is not rearranged unless there is communication of norial data. (DW in Figure 7 is 1C block, 5DA
ES7 does not occur because TA and SCK do not come, -LT
CH pulse is not generated. ), in the CI+IJIO operation as described in -1, the display content continues to be displayed indefinitely, which is not good. Therefore, in Figure 7 of this circuit]10
One countermeasure is to prevent the initial indefinite display by turning off the power for driving the LCD using a power on reset circuit as shown in FIGS. 24 and 25. Furthermore, if the power on/off reset circuit does not work for some reason, or if it is not good for the light to remain off for a long time, please continue the normal data communication from CP[10 until the guaranteed start-up time of XL2 oscillation after the battery is installed. By doing this, the normal operation will start as soon as the oscillation of XL2 starts, and the display contents will change immediately. The contents of the norial data at this time may be data for turning off the light, data for standby display, or any other arbitrary data.

Therefore, the CPU operates by performing normal data communication using display data from the time it performs necessary processing immediately after the tiI4112 is installed until the guaranteed rise time of the XL2 oscillation. If it does, it will be in a stopped state and the function will be stopped. +) - The deviation is good. However, XL2
Issuing &I'L is held within 1 hour (CI)) UIO must inhibit interrupt operations 7jif.

-CPU l O or stop -4ru i;1-CPtJ I
Immediately before O stops operation, CPU10 sends standby mode display data to the display. After that, until the CPU10 is activated again, the display remains unchanged because there is no data transfer, and the standby mode display continues. Immediately before the main switch SM is turned off and the CPU+O stops operating, the CPU10 sends display data for the light-off mode to the display in the same way as above. After that, the main switch SM again
Since there is no data transfer until , the display will not change.
The lights remain off.

-ALLON and ALLOFF- Norial data jlO and jll are the highest priority data that will completely cut off the CD1K source.

It turns off when jlO.jll=“HIgh”.

On the other hand, the data for roller 6 and groove 7 are prepared for checking the connection, and can be determined using the data for the 2ith point. J6
When 7="High", a waveform in which all segments are lit, and when 7="Low", a waveform in which all segments are turned off are output from the COM and SEG terminals, respectively. When each wave is connected correctly and applied to CD, it will display whether all lights are on or all lights are off. However, if the connection with the LCD is misaligned, a part of the LCD may turn off, turn on, or have a different brightness than other segments, making it obvious that the connection is abnormal. Become.

Also, as a way of giving signals for Norial data communication, 5DA
By connecting the TA line to +E through a small resistor, that is, pulling it up, all 7 real data will be “
High" information, and the priority bit j67 comes alive and becomes full lighting mode. On the other hand, when connected to GND, that is, pulled down, all 7 real data are turned on.
The LO mode information becomes 366, which is the priority bit, and the all-lights-off mode is activated. This is a check that can be done after assembling the camera, and is a very easy check method.

Furthermore, there is no need to provide a dedicated terminal, which is ideal.

- Off mode and standby mode - Fig. 35 shows the display on the external display section 4 in standby mode. Only the bar is lit and all other external and internal displays are turned off. As for the camera body, CPL
JIO is in a halted state, waiting for input corresponding to an interrupt instruction. Further, although power is supplied to the display circuit 20, no power is supplied to any other circuits (not shown) other than the CPU10. However, when CPLJIO receives an input from a photometry switch, etc., power is supplied, and the circuit starts working, starting to function as a camera.

On the other hand, the display in the lights-out mode turns off all displays.

The method is to turn off the 0FFV L to turn off the liquid crystal drive 74 source.
Set the CD to "High".At this time, the camera body operates only in a stopped state where CPU10 is waiting for input interrupts from the 8M terminal, and power is supplied to all other circuits except for the display circuit (not shown). Not done.

The difference between the camera in standby mode and off mode is that in off mode: i Main Switch SM 1+ is alive. On the other hand, in the standby mode, other operation start switches such as a photometry switch (not shown) come into play.

In addition, the current consumption is lower in the off mode, which saves energy.
Since the voltage applied to the liquid crystal is zero when the lights are off, the liquid crystal has a good shelf life.

- Manually configurable data indication marks - Figure 29 a, b
In the A mode, the aperture can be set, so the mark 4TA2 on the aperture value side is lit, and the gloss mark TAI on the glossy seconds side, which cannot be set, is turned off.

Similarly, in the S mode, that is, the shutter priority mode shown in Figures 30a and 30b, since the glossy seconds can be set, the tint mark TAI on the glossy seconds side is lit, and the tint mark TAI on the aperture side, which cannot be set, is lit. Mark TA2 goes out.

In FIGS. 31a and 31b, in the manual (M) mode, since both values can be set, both the black mark 'r' is set to 1. TΔ
2 lights up to indicate that both can be set.

When in P mode as shown in Fig. 28, there is no ViN^ that can be set, so both lights are turned off to clearly show the taste.

Please note that these marks can be turned on or off using j72. Control is performed using the AE mode information provided by j73 as is.

However, if the absence of a lens is determined by a function (not shown) that distinguishes whether a lens is present or not, the aperture of the lens cannot be set. Therefore, in this case, the setting mark TA2 regarding the aperture is specially set not to light up regardless of the mode. This is controlled by the q40 signal shown in FIG.

1-Open F-number display - The aperture value is displayed in a 7-segment numerical value as shown in FIGS. 28 to 31. The contents of the aperture value are shown in Fig. 20, where the rq40J signal:! , - indicates a state equivalent to no lens. rq43l~rq62J is 0.
This is the aperture value rounded to increments of 5EV. On the other hand, the lens open F-number includes values such as 35 and 45, which have been popular in the past. However, these values are not multiplied by the aperture value for each 0.5 EV, so these values are treated as special and prepared as r q4 N and r q42 J signals. In this way, the result of calculation by CPUl0 or the set aperture value is the aperture value (judgment is made by an unillustrated aperture signal), and furthermore, it is 3.5 or 4.5 in this embodiment. In some cases, instead of the normal display of 34 or 4.8, it is displayed as 35 or 45.
A display signal is given from CP tJ l O so as to display the following. Further, when the result of the calculation performed by the CPU 10 or the set aperture value is not the aperture value, the normal display such as 34 or 4°8 is used for display.

The display formats of the above two series were made to be displayed at night.

For example, Figure 33.3. An example of displaying the open F value is shown in b.

The open F value is determined, for example, as follows.

As shown in FIG. 40, in step S1, the control cPUIO
reads the open F value Avo from the lens 3 and stores it in the internal reno star. On the other hand, the CPU 10 uses the calculated F value Ay calculated in step S2 based on the camera settings and the value obtained from the photometry result, and in step S3 Avo=A.
Determine v, and if Avo=AV, take out the open Fi & Avo Step S4), If Avo≠Av, take out the actual WF value Av4: rounded to every 0.5EV Step S5), 312 to month 6 The data (AvDSP) is determined, and the extracted f2 output is displayed on the display units 4 and 6 (step S6).

- Override insect and metered manual 7 display - Figure 31 +6.5 is the deviation m of metered manual
This is the only internal display in the viewfinder, which is always lit when in manual mode. The displayed range is +5. s
~-6.5EV (see Fig. 20), and when it exceeds that, +6.5 and -6.5 are displayed blinking. , as the data when decreasing to r! M'dMOVE of 1j61 data
+1 is set to "II igh".

Also, +1.5 in Figure 33 is the override amount,
It always appears depending on the setting when in AE mode other than manual mode. Similarly, the internal display of the Infi Knob is moss. The range to be displayed is +40 to -4.0BV (see Figure 20), and settings cannot be made beyond that amount. Here, the override display is constantly flashing to distinguish it from the metered manual, and at the same time draws attention to the override setting.

In the external display, when overriding, +/- Era (OR+,
OR-, 0RS) lights up, but when in metered manual mode, the +/- era (OR+, OR-) lights up.

0R5) is turned off and not displayed.

The data for each quantity of override and metered manual is received and received using the same register.
A separate identification signal is required.

This signal is provided by the 5IGN signal of j54-356 data.

Table 3 shows the relationship between the data contents of j54 to j56 and their output display states. This makes it easier to understand the sections 54 to 56 on the back of FIGS. 21 to 23.

-5 and A mode display- The display mode is shown in FIGS. 29 and 30.

Figure 29 shows the display when in A mode, with an arrow pointing toward the display of the aperture value that can be manually set, and the mode display unit lighting up. Figure 30 shows the display in S mode,
Manual setting 6 ■ Turn on the S mode display section with an arrow pointing toward the display of the glossy seconds value. By doing this, the meaning of the mode display and the meaning of the numerical display can be understood at a glance, making the mode display extremely useful.

$38fiU a and b show the display contents at the time of initial loading after the film is attached. During the initial loading period, when the film is not fed, it should be controlled at a glossy speed of I/4000 seconds and the minimum aperture value (here, 22).

At that time, all exposure mode displays have disappeared, but
This sets 375 bits to High and turns off the mode display.

FIGS. 39a and 39b show the display contents when the lens is not attached, and is cputed by a mechanism not shown.

If it detects that there is no lens, the display j12~
06 are set to "Low@". This is done in step 518 of the flowchart of FIG. 41, and the display decoder that receives this outputs the 940 signal of FIG. Therefore, display-1 is displayed as the aperture value, and the aperture value open mark TA2, which is a settable mark, disappears.

Note that FIG. 42 shows another embodiment for displaying camera shake of the internal display ff16. In this case, it is composed of three segments as shown in (1) in the figure, and two of these segments are There are two segments (b) and (C) for selecting these two segments, which indicate the type of camera when lit, and by turning on these two segments alternately, camera shake is indicated.

Control [The outline of the operation of PUIO is shown in FIG.

When the battery is installed, the CPU IO starts operating from a reset start (step SO). At the same time, electric power is applied to the display circuit. First, inside CPLIIO.

The camera is then set to turn off (step 510).
Then, display data, turn-off data, standby data, ISO data, etc. are sent n times to the display circuit (step 511). (n is a value determined depending on the time it takes for the display circuit to guarantee normal operation) When the transmission is completed, interrupts from a switch group (not shown) are permitted (Step 1 512)
. If there is nothing, the internal operation clock is stopped and a stop request is issued (step S+3). Among the switch groups not shown, the photometric switch 51 or the initial load switch SB has a relationship with the main switch SM as shown in FIG. 44, and the pond switch group also has the same configuration as SL and SB. . When the main switch SM is OFF, it is Sl, and when the 513 manual power is pulled down, it is Sl.

SB large input is dead. In this state, it is the SM times signal that generates the INTset signal that generates the interrupt. When the main switch SM is turned ON and an INTse+ signal is generated, an INT flip-flop (not shown) is set, and CPIJIO performs an interrupt operation IN (step 514).
)to go into. Does this IN'r fribbufu σtsubu seem to be set at the rising edge? interrupts are enabled (step 5).
12), the INT flip-flop is reset and waits for another interrupt to occur.

Now, when entering INT (step 514), check the switch SB that detects the initial load state (step 515). If it is 0FF (not the initial state), power is supplied to the photometry circuit (not shown), etc., and step SI6 Start metering. After that, in step S17, the AE
The calculation is performed, display data necessary for the display circuit is prepared, and sent out in step S18.Then, the main switch SM is checked in step 519, and if it is OFF, data for turning off the light is sent out as display data in step S20, and the power is turned off. The supply is stopped and photometry is stopped in step S21. Thereafter, step 512. The process proceeds to step S13, and if the main switch SM is ON in step S19, the switch Sl is checked (step S26) L; if it is OFF, data for standby display is sent out as display DATA, and step 516.521. S12. The process advances to S+3, and if it is turned on in step S26, the release switch S2 is checked in step S22. If it is ON, perform exposure control (step 523) and proceed to step SI7, but if it is OFF, do nothing and proceed to step SI7.
Proceed to step 7 and perform the AE calculation again.

On the other hand, if the switch SBh+ON detects the initial load state in step SI5, the seconds value, aperture value, and MODE OFF information data 9 = "High" for the initial load are sent out in step s24.

Then, an initial load is performed to control the shutter mechanism using the seconds value and aperture value (step 525). After that, in step 515, the switch SB is checked again, and depending on the state of the switch SB, the step SI is
Step 6 begins photometry.

To move from step S13 to 514, as shown in FIG. 44, SM, 51. SB switch j is difficult, but SM is O
When it's FF, it's 51. The SBX switch is in a 'Lo' state and is dead as a switch signal. Therefore, S
An INT Set signal is generated only when M is turned on, and an interrupt (rNT) operation is entered. Also, when SM is ON, 5
1. SB switch comes alive and r by SL or SH
The NTset signal is generated and interrupt (INT) operation begins.

Although not shown, the SB switch is turned on when it detects the presence of film and that the back lid is closed, and turned off when a film counter (not shown) reaches 1.

FIG. 43 is a flowchart showing the operation for detecting camera shake. In step S31, the CPU 10 reads necessary information such as focal length from the lens. Then, in step S32, the TV value for the camera shake control is calculated by exposure calculation, and the TVL value of the camera shake warning limit is calculated from the lens information. Then, in step S33, the magnitudes of TV and TVL are compared, and if TV<TVL, then Y
Proceed to step S34 with ES, and if TV>TVL, N
Oi? X Proceed to step S35. In step S34, the LOWSS signal is set to "High" and the mark CA1.
CA2 is vibrated to issue a camera shake warning, and in step 535, the LOWSS signal is set to "°Low" and marked CA1.
Turn off CA2.

Figure 44 shows CPU10 and switches 51.52°SB, S.
Indicates the relationship with M.

Table 1 <Combination of r2r and B+1> 131 -r51 to r53. r61~r65F]2-r
54 B3-r55-r58. r67, r68B4-r
l ~ "29 135 -r30~r43 B6 - r59.r60 B7 - r44~r50 8-r66 Table 2 Table 2 (Continued) Kaya Table 2 (Continued) Effects of the Invention As detailed above, this invention has the following effects: When the CPU has no display data, the display device is set to 111 lights, so the control CPtJ software for creating display data during that time is simplified, and the noMel area for software given to other specifications is simplified. In addition, since unnecessary displays are not displayed, it is possible to prevent the display from becoming confusing.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing an example of a camera to which the present invention is applied, FIG. 2a is a front view of the finder of the camera of FIG. 1, and FIG. FIG. 2C is a diagram showing an example of all segments displayed on the internal display section of the display device of the present invention; FIG. 3 is a block diagram showing an embodiment of the present invention; 4 is a detailed circuit diagram of the oscillation frequency dividing section of FIG. 3, FIG. 5 is a detailed circuit diagram of the common driver of FIG. 3, and FIG. 6 is a detailed circuit diagram of the segment driver of FIG. 3. 7 is a detailed circuit diagram of the data latch section of FIG. 3, FIG. 8 is a detailed circuit diagram of the decoder section of FIG. 3, FIG. 9 is a detailed circuit diagram of the switch circuit SWI of FIG. 8, Figure 1O is a circuit diagram showing details of symbols in the circuit, Figure 11 is a detailed circuit diagram of data conversion aW5, and Figure 12 is the switch circuit SW2 of Figure 8.
The detailed circuit diagrams of Figures 13, 14 and 15 are shown in Figure 8.
16a is a detailed circuit diagram of the output control section of FIG. 8; FIG. 16 is a detailed circuit diagram of a part of the circuit of FIG. 8; East Figures 17 to 20 are diagrams showing the relationship between input signals and displays, and Figure 21
Figures 23 to 23 are detailed circuit diagrams of the data converter in Figure 8, Figure 24 is a detailed circuit diagram of the voltage generator in Figure 3, and Figures 25 to 27 are detailed circuit diagrams of the voltage generator in Figure 3. Waveform diagram of main parts,
Figure 28a, Figures 28 to 34a, Figures 34 and 35 are diagrams showing eight different types of display, Figure i36 is a diagram showing the relationship between signals and registers, Figure 37IAa, b, c
, FIG. 38 1. 39b, FIG. 39 is a diagram showing various aspects of display, FIG. 40 is a flowchart of the CPU showing the display selection operation, FIG. 41 is a flowchart showing the operation of the CPU of FIG. 3, and FIG. 43 is a flowchart of the CPU showing the operation of the camera shake display, and FIG. 44 is a circuit diagram showing details of a part of the CPU of FIG. 3. 4...External display section, 6...Internal display section, lO...C
PU, 22...Data latch, 23/Decoder, 24
...Segment driver. Patent Applicant: Minolta Camera Co., Ltd. Agent Patent Attorney: n Yamane and two others Figure 2 O Figure 2 Figure 2 C 3 A δ 8 Kukoko '5 Ko Ko Ko ~ -A U Φ Figure 16 0 Figure 16 Figure 18 SD GoSOSO80so 90 gDfKI SQ
Phantom B432 * 432 + 432
sllbe 3 @ food 20th figure sos so5 5lll Q4 or 124 SO6 0.5 irises 1.5 a, 5 yo 3.5 5.5 no two cavity 7 = engineering flui direct U14 Road IJ19 Figure 28 (0) P Mo)'1/250 F5.6 AVE, 3°5
::: CS, :E, mouth Fig. 29 (0) A mode (/250 F5.6 AVE, :・ζ・'
r;s5. ::, Ro-11J Fig. 30 (a) S-E-1'1/250 F5.6 AVE, Yo°5
1rG55.130 Fig. 31(a) M”!-1-' 8” Fl, 4 5POT noter 16.5Ev Cζ..., 1. t-: hard +8. S ro Figure 32 (a) Figure 32 (b) IC+ 8, -I Figure 33 (a) , F, r:::::-: l, m, (, +:, @, Mouth 34 Figure (0) Figure 34 (b) Figure 35 Figure 37 C Figure 37 O CA'e EC(PJ , :l, (, +B Figure 37b Yo;-,t [EJ , El, 8 Mouth A2 Fig. 38 Q ′#υsu , ) 8 Mouth Fig. 39 O ; EJ5 , - Uchiguchi Fig. 40 Fig. 41 Fig. 42 (a) (b) (C) Fig. 43 Fig. 44

Claims (1)

[Claims] (1) It has a camera operation control CPU that has a sleeve state and an operating state, a display means that displays various operation modes and their contents, and a display control circuit that controls the display of the display means. Display data is created by the CPU and transferred to the display control circuit, and at least the first display data sent from the CPU to the display control circuit when the CPU wakes up from the sleep state to the operating state is display data for lights out or standby. Features camera display device.