JPS61141422A - Display device of camera - Google Patents

Abstract

PURPOSE:To prevent the difference in the normal full-aperture value and displayed value of, for example, an interchangeable lens or the lilke when such lens is used by displaying the nominal full-aperture value when the aperture value to be used is not 0.5EV unit in a display device of a camera. CONSTITUTION:The display of the aperture value is indicated by digital display of 7-segments. Here, a q40 signal is a -- display which indicates the state equiv. to the absence of the lens and q43-q62 are the aperture values of each 0.5EV. A CPU10 displays 3.4 or 4.8, etc. by changing the value to 3.4 or 4.8, etc. of the ordinary display when the calculated result thereof or the set aperture value is a full-aperture value and is further 3.5 or 4.5, etc. The CPU10 displays by using 3.4 or 4.8, etc. of the ordinary display when the calculated result thereof or the set aperture value is not the full-aperture value. Two systems of display froms are thus provided to the display device.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to a display device for a camera, and more particularly to a display device for displaying the aperture value of a camera.

Conventional technology In cameras that calculate and display the aperture value, conventionally the aperture value is 0.
．． The aperture value for every 5EV could only display data for one of the nominal F-numbers, that is, the aperture value displayed on the aperture ring of the lens. For example 0.5E
For cameras that display aperture values in units of V, the display series is...2, 8, 3.4, 4, 4
．． 8, 5.6..., so the open F value is, for example, 4.
5 lens, the F value is only displayed as 4.8, and there is a discrepancy between the data of the lens actually used and the displayed data, which gives the user a sense of discomfort. was there.

Purpose of the Invention The present invention has been made in order to eliminate the above-mentioned drawbacks, and provides a display device that displays aperture values in o, 5EVP, and columns. equal to the maximum aperture value of the lens in use, and 0.
The object of the present invention is to provide a display device that can display the nominal open F value of the lens when it is not in the 5EV series.

Bridge of invention, display of this invention! ! The first display control means displays the aperture value in increments of 0.5 EV with the force/intensity for displaying the aperture value; Detection means for detecting that a lens with an open aperture value that deviates from the aperture value for each SEV is attached, a calculated or set aperture value equal to lens xf>open aperture value, and an aperture value for every 0.5EV The present invention is characterized by comprising a second display control means that displays the nominal open aperture value when the aperture value deviates from the nominal aperture value.

Embodiment FIG. 1 is a diagram showing the external appearance of a camera to which the present invention is applied. 1 is the camera body, 2 is a shutter button, 3 is an interchangeable lens, and the interchangeable lens 3 contains data about the lens, such as the maximum aperture value. A device is provided that outputs data indicating such information as an electrical signal to the camera body. Further, the shutter button 2 is provided with a photometry switch S1 and a release switch S2, which operate in accordance with the amount by which the button is pressed, using a known method.

Reference numeral 4 denotes an external display section, which displays the calculated EV value and operation mode, as well as various other data that will be described in detail later.

Reference numeral 5 denotes a pointing, and within the field of view of the pointing 5 is provided an internal display section 6 (see FIG. 2) for displaying data and the like displayed on the external display g4.

SM is the main switch.

Figure #2 shows the details of the display on the external display 1114, and from the top there are PROGRAMS for AE momo display. A
When E mode is program mode (hereinafter referred to as P mode), PROGRAM is displayed and S is turned off, and when in aperture priority mode (hereinafter referred to as A mode), A is displayed and PR
0 manual mode (hereinafter referred to as M mode) in which OCR and MS are turned off and shutter speed priority mode (hereinafter referred to as S mode)
(referred to as mode), M and S are displayed respectively. Below that is the SO mark in ISOS-mode, and immediately below it is 7.
There is a 4-digit segment SS, ISO, and CTR display, and on the right side there is a setting instruction mark TAI. Below that is the camera's main switch SM#'tl>i/;
=IIl:□t! LJ tt. bar(r)! 1
zTCI! There is a 7-segment, 2-digit F, +/- display on both sides, and a setting instruction mark TA2 is on the right side of it. There is an aperture value discrimination mark F to the left of the 2nd sector, and a +/- mark which is an override Vwk fixed time sign at the left end.

Further, Figure #12 C shows the details of the display on the internal display section 6. Starting from the left end, there are two camera-shaped marks CAL in close proximity to each other on the camera shake (canora shake) display layer.

There is CA2, followed by 7 segment 4 digit SS.

There are ISO and CTR display sections, and then there are S, P, and A for AE momo display. The S mark consists of a 7-segment arrow pointing toward the 4-digit side to indicate shutter speed priority.
Similarly, the A mark is located immediately to the right to indicate aperture priority.
The segment consists of an arrow pointing towards the 2-digit scale. The P mark has nothing to do with prioritizing both aperture and seconds, so there is no arrow between S and A.The 7 segment 2 digits on the right side for the AE momo display indicate the F value and +/- mode. Displays the +/- value inside. Immediately to the right is M for AE momo display.
There is a mark. This is because the meter manual display lights up at the same time, so it is displayed near the meter display to make it easier to understand. To the right are the override and metered manifold signs, tens and -, followed by a numerical band consisting of seven segments. This numerical value band displays +/- values during AE mode (P, A.

(Only in S mode), the meter manifold in AE mode, and full value display (only in M mode and V).

Finally, there are the ASl and AS2 marks that indicate the metering mode. During average metering, only ASl lights up, and during partial metering,
Both ASI and AS2 are lit.

Fig. 32 a, b% Fig. 33 a, b shows the override being displayed, but in the infining-internal display, the place where the override value is displayed is the override (+/-
) mode and AE mode. This is an attempt to display information near the center of the display section during override mode display to make it easier to understand.

The third section shows the overall configuration of the control device related to the above-mentioned camera display. cpui o using a micro pump for central control to control the operation of the entire camera
is supplied with power +E from the battery 11, the main switch SM is pulled up with a resistor R, and the reference oscillator XL for operating CP010.

1. Group of control signals to peripheral circuits (especially for display).

C8, PWC, serial data 5DATA necessary for serial data transfer, and serial clock SCK are connected to the peripherals.

An outline of the operation of the CPU 10 will be described later.

On the other hand, the display circuit section 20 receives the power supply element E from the battery 11, the main switch SM, the signals C3 and PWC from the CPU 10,
5DATA, SCK, reference oscillator XL2. A reference power supply 21 for driving the liquid crystal is inputted, and outputs include an external display [4 using a liquid crystal display] and a movement output group for the common and segment electrodes of the internal display section 6. The drive output terminal group is connected to the external display section 4 of the camera connected in parallel and the external display section 6 in the seven cameras, respectively.

Inside the display circuit 20, there is a data latch section 22 that latches serial data. Decoder section 23 that decodes the latched data. Segment driver unit 2 that drives the LCDs of external and internal display units 4 and 6 using decoded signals
4. Common driver g25 that drives the common part of LCD
．． Oscillation frequency division 1!1i26 to create operating clocks for each part
．． There is also a voltage generating section 27 that generates a driving voltage for the LCD.

FIG. 4 is a detailed diagram of the oscillation division section 26 shown in FIG.
I). The 7-rip 7a-tube FFI is provided with a reset terminal R so that initial settings can be made by installing a battery.

Figure 5 is a detailed diagram of the common driver section 25.■LCD0
．． VLCD2. VDD+7) each IKIIe 7 f
of X 4-/ +As 1-AS 4 and Pe
hFET FPI, φ1 through FP2. φ,. At the timing of C0M1. It is configured to output to C0M2. Nando date jNAl
, 2. Noah Day) NRI, 2 and inverter IN3.4
is the day for creating the timing).

FIG. 6 is a part of a detailed diagram of the segment driver section 24,
VLCD2. Analog switch AS5 and PchFET EP3 for switching each voltage of VDD are made of φ1. Among the timings of φ1°, segment data S2n, 52n
-1 is configured to be driven according to the state. Nando Day) NA3 to NA7 and inverter IN6.7 are S2
n, constitutes a clock selector by 52n-1,
Inverter IN5.7 lip 71ff knob FF2 is φ1
．． It constitutes a clock generator for creating clocks with four types of phase differences from φ10.

The entire segment driver section is of the type shown in FIG. 6, in which the clock selector, analog switch, and PchFET parts are prepared in the same number as the SEG output terminals, and a rear clock generator is added.

FIG. 7 is a detailed diagram of the data latch unit 22. There are seven 8-bit shift registers SR1 to SR7 that receive serial data 5DATA from CPU10, and the parallel outputs of these shift registers are latched at the falling edge of the LTCH signal. Seven 8-bit latches LTI to LT7
is connected to.

The R input is applied to the jlO data of latch LT1, the S input is applied to the j11 data, and the jlO data and j11 data are powered on, respectively.
It is reset and set by the OR signal, so the initial state is j10 = “Low” * jl 1 = “Hi
It is gh@.

On the other hand, the external serial clock SCK is off day)
NOAD) NR3 to NR as φS signal passed through ORI
9, and is also adjacent to the φ input of the counter decoder CD. When the set human power S of the counter decoder CD is “High”, the output BSI of the counter decoder CD~
All BS7 are "High", and when the S input becomes Low, the signal changes from BSI to BS7 in sequence every 8 pulses of the φ input.
One of them becomes “Low”.

When any one of BSI to BS7 is “Low”,
One of the corresponding NOR dates) NR3 to NR9 becomes active, and the φS signal, which is the input of the NOR date, is sent to one of the serial renostars SRI to SR7.
Enter into the input. External control signal pwc from CPU10
, cs are logically summed by OR3 to become a p-cs signal, which is input to the other input of ORI and the S input of the counter decoder. Also, it becomes one input of OR2, and the other input BS7
An OR logic is performed on the 7-lip 70-tube FF3 and one input of the NAND (NAND) Na3. In the 7-rip, 70-tube FF3, the POR I word is input to the set input S, and the Q output is connected to the other input of Na3. In addition, the φ2 input of the 7-rip 70-tube FF3 in Fig. 4 is used.
Output is connected.

FIG. 8 is a detailed diagram of the decoder section 23 shown in FIG.

In the diagram, switch circuits SWI, SW2. Data converter DC
I to DC4, segment decoder sections SDI to SD6. The output j of the decoder 22 is input to the 6-switch circuit SWI constituted by the output controller CTL1.
12~jl 6. j22-j27. j32~j
37. 25 wires from j40 to j47, data conversion unit DC
3 has the four outputs j50 to j53 of the decoder 22 as inputs, and the data converter DC4 has the output JI of the decoder 22.
OI JllllJ201 j2L J54~j57
．． j60～j67゜"70～"77, total of 24 pieces 53
The book is connected to the outputs of the seventh circuit LTI to LT7 in FIG. Further, two signals SM and PWC from the main switch shown in FIG. 3 are input to the data converter DC4. As shown in FIG. 4, φ14 is connected as an input to the output controller section CTL1, and 70 outputs 81 to 870 are connected to the segment driver section 24.

FIG. 9 is a detailed diagram of the switch circuit SW1 in FIG. 8,
jn from data latch 22 (n=12
) to 47 (however, 17.20.21.
30.31)) - *Pn (n = 12-47 (however, 17, 20.30°31 is excluded)) using 25 NAND date NAs, FOM, CTR
, ISO.

It is switched by the SS signal. FON, CTR.

When the ISO and SS signals are 'Low', the Pn signal is 'Low'.
The jn signal is turned off, but the FON remains high.

When CTR, ISO, SS signals are “High”, Pn
= jn, and the switch is turned on.

FIG. 10 is a diagram explaining the symbols used in FIG. 11, FIGS. 13 to 15, and FIG. 23, including A, B, and C.

For each input of D, by marking the intersection of the arrow with the output Q, it indicates the same function as the Nantes gate, that is, Q
=B-D.

FIG. 11 is a detailed diagram of the data conversion unit DC3 in FIG.
The logic of outputs p1 to p9 is shown for inputs 350 to 53. This output becomes the input of the Sui-Nor circuit SW2 shown in FIG.

FIG. 12 is a detailed diagram of the switch circuit SW2 of FIG. 18, in which inputs p1 to p9 are connected to Q71 to q78 . by switching signals MON and +/-ON signals. The input p signal representing the logic switched to q82 to Q89 is input to the NAND date, and when the switching signal MON and the +/-ON signal are "Low", the output q signal is "High". It can be cut. When the MON and +/-ON signals are "High", the output q signal becomes equal to the input p signal, and the switch is turned on.

Figure 13 shows segment decoder sections SDI to SD in Figure 8.
In the detailed diagram of 4, outputs r1 to r2 for inputs q1 to q39.
The diagram showing the logic of 9 is the segment decoder section S.
Since the basic configurations of DI to SD4 are the same, they are shown in the same drawing, but the necessary parts of each of SDI to SD4 are extracted from this figure.One output is the input of the output control unit CTLI in figure #8. It has become.

FIG. 14 is a detailed diagram of the data converter DC2 in FIG. 8, showing the logic of outputs q40 to q62 for inputs p12 to p16.
It is input to D5.

FIG. 15 is a detailed diagram of the segment decoder section SD5 in FIG. 8, showing the logic of outputs r30 to r43 for inputs Q40 to Q621 Q71 to q78. The zero output is the output control section CTLI in FIG. is the input.

FIG. 16a is a part of a detailed diagram of the output control unit CTL1 of FIG. 8, in which outputs of 51 to 370 are obtained by the outputs of the segment decoders SD1 to SD6 and the data conversion unit DC4 and the clock φ14.

In this figure, r2n and 8- are shown in any combination, but in reality they are connected in the combinations shown in Table 1.

Table 1 shows a truth table by replacing the circuit diagram of FIG. 16a with logical expressions. Furthermore, a combination of r2n and B+m is specifically shown. (1≦so≦8).

(1≦2n≦68) R69 is shown in FIG.

FIG. 16 shows input r69 and output s69. It shows the logic to s70.

FIG. 17 shows the relationship between the outputs q1 to Q39 of the data conversion unit DC1 of the decoder unit 23 and the characters displayed on the displays W54 and 6, and the inputs p22 to Q39 to the data conversion unit DC1.
p27. p32-p37+p40-p47. When q1 to q39 are output according to the state of CTR, ql-q39
The displayed characters are controlled depending on the state of ``Low'' or ``High''.

That is, if the output q1 is "High", it is SDI, so the display unit 4 (upper and 6) displays 10 degrees as 0 degrees, and if q2 is "High", the 10 degrees display as 2. For the shutter speed SS value, p22~, 27, I
Data is given as p32 to p37 for the SO value, and p40 to p47 and the CTR signal as for the CTR value. Also, p22~p27゜I+32~ρ37, p40~
When p47 is all "High", the configuration is such that no output is produced for that data. Therefore, for example, p22 to p27 for the shafter speed SS value
When data is available, other p32~p37+ p
The data converter DC4 and the switch circuit SW1 are configured so that all 40-p47 are set to "Hi [Ih"] (see Figures 9 and 21).The content that can be displayed is shown in Figure 18 as an example. There are 36 types of SS values, 31 types of ISO values, and 100 types of CTR values.

FIG. 19 and ttS20 are diagrams showing the relationship between the data of the data conversion unit DC2 and the switch circuit SW2 and the characters displayed on the display units 4 and 6. O1~p9, MON
, Q40 to Q62+ q71 depending on the +/-ON state
-q78+ The outputs of q82 to a89 output data as shown in this figure. For F value, see p12~. 16. For override values and metered manual values, see p.
Data are given on pages 1 to 9.

Figure tjS2i is a part of a detailed diagram of the data converter DC4 in Figure 8, and shows switch switching signals MON, +/-ON, FON of switch circuits SW1 and SW2.

CTR, ISO, SS logic and CTLlH ON,
The logic of the OFF signal and the logic of the OFF Vl and CD signals applied to the voltage generator 27 in FIG. 3 are shown, respectively.

The input signal is the output signal jlo+jl of the data latch section
l+ j55+ j56t j60~ j67
゜j70+J'', external signals, SM, and PWC.

FIG. 22 is a part of a detailed diagram of the data conversion gDC4 in FIG. 8, and shows the logic of the B1 to B8 signals of the CTL1 section.

The input signal is the output signal J201 J of the data latch section
55-j5L j61-j64° j70-j74 and external signal pwc.

FIG. 23 is a part of a detailed diagram of the data conversion section DC4 of FIG. 8, and shows the logic of the r51 to r69 signals of the control section CTLI. The input signal is the output signal j of the data latch section
211 j54~J57゜''70~j731 J7
5 to j77 and the output signal q40 of the DC2 section. and an external signal PWC. 21 to 23 include all the data conversion section DC4 of FIG. 8.

FIG. 24 is a detailed diagram of the voltage generating section 27. Create a reference voltage VLCD by externally connecting a diode D1 and a resistor R1 between +E and GND, and connect the capacitor CI.

By supplying the voltage to the booster circuit 27a (the part surrounded by the broken line) including C7, (10E-vt, co>cn times trf(
+E-VLCDI) IQ rawt! , VLCD
D1 is set to V LCD0 and V LCD2 respectively by analog switch and pehFETt' output control circuit.
be guided by.

V LCD0 V LCD211.0FFVLCD
The output changes with the LS depending on the state. 0FFVLCD is “
When “Low”, VLCt+0=VLCD, VL
CD2=VLCD1tonaI), 0FFVLCD #”H
When “high” en, V LCD0 = V LCD2
= V [10.

Further, the booster circuit WS27m obtains a clock from φ in FIG. 8 to switch the connection of the capacitors C+-C2 to boost the voltage. Further, POR is a terminal for starting the booster circuit, and the booster circuit is started by the FOR output shown in FIG.

FIG. 26 is a time chart of the data latch section 22 of FIG. 7. Both external signals pwc and cs become “Low”, and shift registers SRI to SR are activated at the falling edge of SCK.
7 data will be rewritten.

The contents of SR1 are all rewritten at the falling edge of the 8th pulse at the beginning of SCK, and from the 9th pulse onwards, the contents of shift registers SR2 to SR7 are rewritten every 8 pulses.
, BS7 becomes ``Los'' at the rising edge of the 49th pulse immediately after SR6 is rewritten, and at the same time SR7 starts rewriting, -2
In order to read the D input at the rising edge of
BS7 becomes "Low" and does not change until BS7 becomes "High" again.

The LTCH pulse is created by the Q output and the p-cs multiplied signal, and the SRI~SR? LTI the contents of serial renosta
~It will be taken into the latch of LT7.

FIG. 25 is a time chart showing the overall general operation from after the battery is installed in the camera. Immediately after the battery is installed, the display circuit section 20 is initialized by the FOR signal. signal vtc
oi becomes earth GND level, OF F VLCD
h”High” Nina A, L rQ Ka91: No voltage is applied to the liquid crystal, then CPolo's
LI starts oscillating and CPU10 starts operating "f!111&6
1-&'''nfiIIf!lle#v゛?Jlffi
li1Mg2.

0 oscillation nXL2 starts oscillating, and the clock φ.

~φ3. starts to start. When the clock φ starts operating, the data latch section 22 starts operating, and when serial data comes from CPU10, it operates as shown in FIG. 26. When the clock φ starts operating, the voltage 8! shown in FIG. 24 is generated. I2
7 is activated, and the potential of the signal VLCDI becomes stable after a short period of time. After that, OF F V as necessary.
If you set the LCD to 'Low', the LCD drive voltage, V
The two LCDO and VLCD are supplied to display sections 4 and 6.

28 to 35 and 37 to 39 show various display modes of the external display n4 and the internal display section 6. The figure shows the display on the internal display section 6.

Figures 28a and 28b are AE displays in program mode,
Auto second time 1/250 and auto aperture value 5 degrees.

The mark ASI at the right end of FIG. 28 indicates the photometry mode and indicates average photometry.

Figures 29a and 29b are AE displays in aperture priority mode;
When you see the aperture setting mark, the set aperture value is 5.6 and the auto second time is 1.
/250, and the aperture priority A and prisoner represent the AE mode.

FIGS. 30a and 30b are AE displays in the shutter speed priority mode. When the shutter speed setting mark is pressed, the set shutter speed value is 1/250 and the auto aperture value is 5°6, and when the shutter speed priority is given to S83, the AE mode is indicated.

31st W Otori,) I is A E in manly mode! i
This is an indication. The setting mark for the shutter speed and aperture value indicates the shutter speed value of 8'' and the set aperture value of 1.4, and the manifold mode M and the figure represent the AE mode.The right end of the internal display indicates the metering mode. It is a partial metering mark, and the left side is the error amount of the metered manifold setting value with respect to the appropriate value, which is the so-called metered manifold indicated value.
The mark on the left end that indicates that there is a difference in indication of +6.5 EV is a mark that indicates a camera shake (hand shake) warning, and the two marks are lit alternately.

FIGS. 32a and 32b are displays during override setting. Override direction and absolute f! L1. Represents sEV.

FIGS. 33a and 33b show the AE mode display after override setting. Compared to FIG. 28, a director for override r has been added. The internal display also displays the absolute override amount of 1.5 EV. +1.5 is flashing on the internal display.

34th t! la and b are displays during ISO setting.

The ISO mark and ISO value 100 are displayed.

However, the ISO mark does not light up on the internal display.

FIGS. 37a and 37b show hand shake (camera shake) warning displays. On the internal display section 6, mark CA on the leftmost camera
1. CA2 lights up alternately to indicate movement.

FIG. 37C shows the display of external display g4.

FIG. 35 is a display in standby mode.

Only the bar display was blank, and all other lights were off. II other than camera display! function is at a standstill.

<Operation Description> - Overall Operation - The basic operation of the display circuit section 20 will be explained. When the DC voltage +E is supplied from the power supply 11, the momentary F generated by the puff-on-recession circuit 40 (the right end of FIG. 4)
The OR signal causes the frequency division stage's 7-lip 7eI9-p FF1 (
4), segment) 7-lip flop FF2 of the clock generator of the V driver section 24 < Fig. 6), 7-lip flop FF 3 of the data latch circuit 1IS) 23. Latch LTI (Figure 7), starting FET of voltage generator 27
27b (Fig. J$24) are each set to an initial state. In latch LT1, each data terminal is set to j10="Lo
w”.

jl 1 = 'High'. 7 lip 70 lip F
FI.

In FF2, set the output state to Q='"Low" and Q="High"
h''.In FF3, set Q=“High” in the output state.
”.

Set Q='″Low’. In the voltage generating section 27, F
When ET27b is turned on for a moment, the capacitor C2 is charged with electric charge, and the level of VLCDI becomes the level of GND. In this state, since the crystal oscillator XL2 of the oscillator 41 (Fig. 4) has not started oscillation, there is no circuit operation at all, and the oscillation of XL2 rises while the initial setting value and internal state from the cine steady state are maintained. (=oscillation rise of φ.)
Waiting for. LCD display for one direction, external gjl and g4 and 6? f11ml: connects the TE V through the COM and (/SEG terminals)
DD, VLD2. Although the VLDO power is given in an undefined state, (COMI is VLCD2゜C0M2 is VL
CDO, 5EGn is VDD or VLCD depending on the state of S2n, 52n-1;
Due to the initial setting of 'high', the switch circuit 1:A' in Fig. 24 is set to 'High' via the A50° inverter ■50.orday)050.
VLCD2=VLCDO=VDD, inner and outer surface bearing parts 4
, 6 are equal in voltage to each terminal of the LCD display, and there is no DC voltage application that is harmful to the liquid crystal.

Next, the crystal oscillation HXL2 starts oscillating and φ. When a clock enters the 7-rip, 70-tube FF1 in the frequency dividing stage, each part starts operating at the same time.

The clock φ2 enters the 7-lip 70-tube FF3 of the data latch unit 22, and when serial data communication from the CPU 10 starts, it is used to generate an LTCH pulse.

The clock φ6 enters the booster circuit of the voltage generator 27, and C,
By switching the capacitors , C, external pressure operation is performed.

Clock φ1. φ1° enters the common driver section 25 and segment driver section 24 and becomes the CY rack where the liquid crystal drive waveform is applied.

The input signal φ14 is input to the output control section CTLI of the decoder g23 and is used to control the blinking state of the display contents.

The operation after the oscillation rise of the crystal oscillator XL2 is explained by the external pressure circuit 27 in the diagram tlS24.
The clock φ, which has entered m, starts the boost operation and the initial V
LCt11 terminal was at GNI) level e(VD
D-2VLCD) and stabilized.

Thereafter, it continues to work without interruption until the power supply voltage drops and it stops operating, or the oscillation circuit stops, causing the lifting and lowering operation to stop. On the other hand, the data latch circuit 22 which started operating in response to the clock φ2
"Low" on l.

At the moment when a signal other than "High" is input and ticked, 0FFVLCD becomes "Low" and the analog switch on the right side of Fig. 24 switches, and VLCD2 = VLC.
D1. VLCDO = VLCD output e wait, =h
mules, each with a common driver 25. It is guided to the segment driver 24 and used as a voltage for driving the liquid crystal in the inner and outer display portions 4.
A liquid crystal display is performed based on the latched data.

Next, the data line 22 will be explained with reference to FIG. 26. This circuit starts operating when both the pwc and as multiplied signals become "Low". pwc is, for example, a timing signal for supplying power to a photometry circuit of a camera (not shown),
The photometry circuit starts operating when pwc="Low". Further, 1 is a signal for determining the other party for serial data communication, and one signal is output from the CPU 10 to each of the other circuits in the camera (not shown). C
When "S=Low", the other party for serial data communication is selected.

When either pwc or cs is “High”, P・C
8 signal is “High”, the counter decoder CD is set, and all BSI to BS7 outputs are “High”.
”. Also, the output φS of ORI is “H”.
"High", and the output LTCH of Nanddate NA8 is also "High", both do and cs are Lo11"
At this time, the counter decoder CD enters the operating state, and ORD (ORI) and ORDATE (OR2) are opened, and the SCK and BS7 signals become detectable. At the rising edge when the first pulse of SCK is input, BSI changes to "LoIl" and 9NOR date NR3 opens. At the falling edge of the first pulse, the φ input of shift register SRI rises, so the contents of 5DATA at that time are transferred to the shift register. SR1 takes in only one data, the data at this time is jlo.The second pulse comes to the primary and the same operation is repeated.At the falling edge of the 8th pulse, 8 pieces of data are taken into the shift register SRI. The 8th data is called "17." Until this time, the signal BSI is "
Low”.

When the next 9th pulse rises, BSI becomes High'' and B
When S2 becomes ``Low'', NR3 closes and NR4 opens, the φ input of shift register SR2 rises at the falling edge of the 19th pulse, so 5DATA at that time.
Only one shift register SR2 stores the contents of , and the data at this time is j20. From then on, proceed in the same way, and the 49th
At the rising edge of the second pulse, BS6 goes high, BS7 goes low, NOD NR8 closes, NOD NR9 opens, and the output of OR2 goes to "Loll". Shift register SR7 From then on, up to the 56th pulse, data from J7o~''77 is taken in, but from the 1st pulse onward to the f&56th pulse, the LTCH output is High'' *, and data is taken in from each shift register SR to the latch LT. is not carried out, or day which opened exactly at the 49th pulse) OR2
Due to off-day), the output of OR2 becomes Low'', but due to the rise of clock φ, 7rip 70 and knob FF3
takes in the “Loll” of the D input, and the output is “Hi”.
However, the other input of Na3 is set to "Lo-", so the LTCH output remains at "High".

At this point, depending on whether the 57th pulse comes or whether PWC or C3 becomes "High", the output of OFF5/~TOOR2 becomes "High", at this moment Na3
Since the other input, the 7-lip 707p FF3 output, is also 'High', the output LTCH of Nando Na3 becomes 'Low'.This 'High'→'L
The falling edge of "ow" is a latch signal, and the data stored in shift registers SRI to SR7 at 1 o'clock is latched to LT.
It is latched into the data memory of I to LT7. After that, with the rise of the clock φ, the 7-lip 70-tube FF3 is set to D.
The input "old gh" is taken in, the output thereof becomes Low, and the counter decoder CD is sent to either pwc or cs at "High", and each returns to the initial state.

The above is an overview of the operation of the blade C data latch. If the number of clock bytes for serial data communication is insufficient, the output of the last latch pulse LTCH will not be output, so no data error will occur, and the number of clock bytes will exceed. Mo5
Automatic fishing is turned off at the 7th pulse, and of course no abnormality occurs.
Furthermore, since the clock within the same byte is processed so as not to be interrupted on the sending CPU side, abnormalities in data communication are completely prevented.

On the other hand, even if the external signals PWC, C8, SCK, and 5DATA operate normally, if the internal φ is not operating, the LT
CH pulse no longer appears and shift registers SRI to SR
There is no need to latch the data captured in 7 to latches LTI to LT7. This is because when it is considered that the liquid crystal drive waveform does not operate when φ2 is not operating, a DC voltage is applied to the liquid crystal. Therefore, at that time "io = 'Low" + jl 1 = "Hi8
It is necessary to maintain OFF VLCD=“High” so that no voltage is applied to the liquid crystal. For this reason, external data is not taken in when the clock φ is not operating.

Next, the common driver section 25 and the segment driver section 2
I will explain about 4.

In FIG. 5, ff161F, and FIG. 27, NA1. NA2. Noah Date NR1, NR2
, inverter IN3. Analog switch ASI~AS4゜Pch FET by the date circuit composed of IN4
Controls each switch of FPl and FP2. The input signal of the date circuit is φ1. φ5. Wow, due to this timing, C0M2. The outputs of C0M1 each change as shown in FIG. The signals C0M2 and C0M1 have the same period as the clock φ1°, and are shifted from each other by 1/4 period.

Output value toshiteha ■DD to vLCDO and V LCD2 to 3
It has a value level.

In Figure 6, four types of clocks generated by the clock φ processed by the clock generator composed of the inverter INS, the primp 70 tube FF2, and the clock φ10 are NAND dates NA3 to NA7t'49.
t7 y 9ya & 99-1yu (selection)
Select 1 6 Conditions for selection are S2n, 52
n-1 two signals, and by this condition, 5EGn
The output waveform of is determined.

This situation is shown in FIG. 27, and there are four different states determined by S2n and 52n-1.
The period is the same as that of the clock φ16, and there is a difference of 1/4 period from each other. The output values are VDD and V
It has two LCD levels. signal COMI,
The potential difference between 2 and segment signal 5EGn is 2XVLC.
The LCD display lights up depending on the waveform of the portion that becomes D2.

5EGn (LH), 5EGn (H
The segment of the LCD display to which voltage H) is applied lights up, and 5EGn (HL), 5E for C0M2
The segment of the LCD display to which a voltage of Gn (HH) is applied lights up. 5EGn (LL) is C0M
1. The segment will no longer light up for C0M2 as well.

In other words, the 52n-1 signal is a signal that controls lighting of the segment for C0M1, and 52n-1="Lo11"
When , it is OFF, when 52n-1 = "High", it is ON
become. The S2n signal is a signal that controls the lighting of the segment for C0M2, and is OFF when 52n="Lo-"
, 52n=“Hil?h”, it is turned ON.

Data latched in Figure 7 Jl 0- Jl 7+j
20-j27. j30~J371 J40- J4
71jso~j571 j60- j67+, 70
- j77 is JI L J301 J31 3 via F
All signals except 1 are input to the decoder section shown in FIG. S
W.I.

SW2. DCI-DC4, 5D1-3D611 are simply gate circuits and have no timing relationship at all.

The explanation is below.

First, the contents of the serial data will be explained.

JIOIJII is a signal that controls the supply of liquid crystal drive voltage, and ``10 = ``Low'' + j 11 = ``Hi
gh”, the liquid crystal driving voltage stops and the voltage applied to the liquid crystal becomes 0.

j12 to j16 are data signals (
tjS9, Figure 14, @15, and Figure 20), and there are 23 types. Also, "12 to j16 are all "High
h'', nothing is displayed.

j20 is a signal related to a warning of insufficient battery voltage in the camera (see Figure 22), and j20="High"
When , all the displays are φ.

Repeats blinking at a period determined by .

"21 is a hand shake (camera shake) warning signal (see Figure 23), which becomes "High" when the shutter speed becomes slower than the limit that causes hand shake (camera shake).
At this time, the camera shake mark CA1 on the internal display section 6 in the viewfinder. CA2 lights up alternately.

j22 to j27 are data signals (
(see Figures 9, 13, 17, and 18),
There are 36 types. Also, j22 to j27 are all “High”
h”, nothing is displayed.

332 to 137 are data signals regarding the ISO value of film sensitivity (FIGS. 9, 13, and 17).

(see Figure 18), and there are 31 types. Also, j32~”
When all 37 are High'', nothing is displayed.j40~
j47 is a data signal regarding the timer seconds value (Fig. 9,
(see Figures 13, 17, and 18), and θ~99
*There are 100 types.

Also, when all of j40 to j47 are High'', nothing is displayed.

” 50 to 353 are data signals regarding override values and metered manual deviation amounts (see Figures 11, 12, and 19.20), and there are 9 types of override values depending on the content to be displayed. The metered manual's 14 deviation values are switched and sent from CPtJ. When all of j50 to j353 are ``High'', nothing is displayed.Signals J551 and J56 (described later) are responsible for switching the 0 display contents.

j54 to j56 are 5IGN signals (see Figures 21, 22, and 23) related to the override value, the sign of the metered manual deviation amount, and signal switching, and j54 is "+" and " −” Signal related to the symbol, j
55 and j56 are over'4)"1・/-9-)'v"
This signal is designed to switch the data of z7'by>@difference 81 for each external display and internal display.

j57 is a signal used to display the so-called Brevini temporary display (see Figures 22 and 23), which is used to check the depth of field by narrowing down the lens aperture before shooting. Sometimes this signal becomes 'High', causing the aperture mark F on the external display section 4 to blink and the set value band indication mark TAI.

Controls the lighting of the bar at Ta2.

j60 is an ISO display priority signal l5OPRI. This means that main switch SM is OFF and 0FFVLC
Even if the D signal is "High" and the liquid crystal drive voltage is stopped, when this signal becomes "High", the liquid crystal drive voltage is increased by the segment driver 24. The 0FFVLCD signal is set to "Low" so that it is supplied to the common driver 25. (See Figure 21) This signal is not used alone; the ISO display mode and ISO value data are sent simultaneously with this signal.
Sent from PU10. In terms of camera operation, this is the state immediately after the battery is installed.

"61 is a blinking signal of the deviation amount of the metered manual M'dMOVER (see Figure 22), and this signal is "Hi".
gh”, the deviation amount value on the meter V manual flashes.

j62 is a shift signal SHI for blinking the program mode mark during the shift of the camera's program mode.
FT (see FIG. 22), and this mark blinks when j62 is "High". Here, "shift" refers to the state in which the combination of the aperture value and shutter speed value is changed in the program mode.
Incidentally, all AE modes can be blinked as needed, regardless of the program mode.

j63 is the control interlocked warning signal Not, C0NT (JF
(See Figure I22), and this signal is used when an exposure value that exceeds the aperture value and second value that the camera can control is required.
The aperture value and/or second value becomes "High", and the numerical value on the calculation control value side flashes depending on the AE mode to issue a warning.

j64 is a brightness-linked warning signal BV (see Fig. 22), and this signal becomes "High" when the brightness value exceeds the brightness value that the camera can measure, and the ASI and AS2 during the metering mode display. flashes to warn you.

A65 is the bulb time signal BULB (see Fig. 21), which is a signal for switching the display contents of 4 digits and 7 segments during bulb exposure from the shutter time display (buLb) to the bulb exposure time count display. The valve count will be displayed and the contents of J40 to j47 will be displayed.

A66 is an all-lights-off signal ALLOFF (see Figure 21), which controls the waveform of the drive SEG terminal so that it becomes an OFF waveform (see Figure 27, 5EGn (LL)). The OFF display will appear. f day, the camera mark CA1. C- and A2 cannot be controlled.

767 is an all-lighting signal ALLON (see Figure 21!It), which controls the waveform of the drive SEG terminal so that it becomes an ON waveform (see Figure 27, 5EGn (HH)). All will be displayed as ON.

However, the camera mark CA1. CA2 cannot be controlled.

j70+J” is the camera operation mode signal CALL
MODE (see Figures 19, 20, and 21), normal AE mode, 5TANDBY mode in which the camera is not operating even if the main switch SM is ON, 180
ISO mode for settings/display, +/+ for general settings/display
There are four states: /-mode, and the display contents are switched according to each mode. (See Figures 28 to 35)
72+ A73 is the camera's AE mode signal AEMOD
E (see FIGS. 22 and 23), and has four states: program mode, aperture priority mode, shutter speed priority mode, and manual setting mode, and the display contents are switched according to each signal.

A74 is the rso output when prompting to set the ISO value.
This is the warning signal ISOARM (see FIG. 22), and when this signal goes high, the ISO mark and ISO value in the interior and exterior display sections 4 and 6 flash.

A75 is a mode off signal MODE OFF (see FIG. 23), and when this signal becomes "HilBh", the AE mode display being displayed is turned off. Turn off the mode display when loading film into the camera.
Make it F.

476+ A77 is photometry mode switching signal AVE/5P
OT (see Figure 23), and when the partial metering mode is selected among the two metering modes, the average metering mode and the partial metering mode (either or one of A76 and A77 is "L").
os'') lights up AS2 on the internal display section 6 of the finder.AS1 remains lit during the AE mode.

The DC4 also uses the external signals SM and PWC as data, and uses the data hood conversion section (Fig. 23) and the L of the display section 4.6 regarding displays other than the numerical range such as the shutter time value and aperture value.
A decoding section (Fig. 22) for controlling blinking of each display segment of the CD display, and two signal switching sections SWI, S.
It is divided into three parts: a decoder p section (FIG. 21) related to W2.

Figure 21 is created mainly with SWI and SW2 switching signals, and FOM, CTR, ISO, and SS signals are SWI and SW2 switching signals.
, MON, +/-ON signal controls SW2. In addition, the σN and OFF signals are commands to control the CTLI and display an ON display and a VOFF display for all segments. Sarani, 0FFVLC [l signal is main signal power''
It functions to cut off the liquid crystal drive power supply and the liquid crystal drive circuit when the main switch SM is turned off. On the other hand, "7 (Lj71) of the CALL MODE signal represents four camera operation modes, but A70・j71 = "Hi"
gh”, set to AE mode de n for normal shooting j7
0 ・j71 = “High”) When 1i 1 SO sensitivity setting is called 180 mode, A70 10,000] = “Hi
When A70/j71 = "Higb", it is called the 5TANDBY mode for camera standby mode, and when it is "Higb", it is called +/- mode for setting the override amount.

To explain the signals for SWI and SW2 according to the above four modes (see Figure 21), during AE mode, P
WC becomes “Low” (the camera starts operating.
), the FON signal becomes High'', SWI works,
Aperture value information j12~16 is selected and decoded and displayed. When rW becomes “High” (the camera enters the standby state), the FON signal becomes “Low”.
”, and the aperture value information is erased by SWI.

On the other hand, when pwc is "Low" and j65 is "Low" (
During normal operation), the SS signal becomes "High" and the shutter speed information "22 to j27" are selected and decoded and displayed. At this time, the other CTR signal and ISO signal are "Low" and are erased by the timer count information and ISO value type information Wl.

When pwc is “Low” and j65 is “High” (
During pulp counting), the CTR signal becomes ``High'', and timer count information j40 to j47 are selected and decoded and displayed. At this time, the other SS signals and the So signal are 'Low' and are turned off by the shutter speed information and the ISO value information WI.

Also, the +/-ON signal is 'Low', but the MON signal is PWC is 'Low' and the j50 or '56 data is 'High'.
h'', it is "High", so the value information of the metered manual deviation amount is selected and decoded and displayed by SW2, but the value information of the override is erased.

SS, CTR, FON, MON in ISOS mode.

The +/-ON signals are all "Low", only the ISO signal is "High", the SWI operates, and the ISO value information 332 to j37 are selected and decoded and displayed. At this time, other numerical bands should be erased.

5 During TANDBY mode, SS, CTR, FON, I
The SO, MON, and +/-ON signals are all "Lo@", and all numerical bands are erased.

During +/- mode, SS, ISO, CTR, FON, M
All ON signals become “Low”, and in vW it becomes “Low”
At this time, the +/-ON signal becomes High''.

At this time, override information j50~''53 is selected and displayed in defm.

Figure 22 1id table ``''''r/>)'' blinking table control
1.Creating a signal and outputting 8
If the corresponding segment) (see Table 11) is lit when 1 to B8 become "High", that segment will blink.

The B8 signal is a signal that causes the F mark on the external display section 4 to blink, and is mainly controlled by the j57 data.

The B7 signal is the 7th segment of the LCD of the internal display section 6.
This is a signal that blinks numbers 8, 8, col, and 2tIS 2 digits between them, and is mainly controlled by the data of j55+j56t j61.

The B6 signal is a signal that blinks ASI and AS2 on the internal display section 6, and is mainly controlled by j64 data.

The B5 signal is a signal that causes numbers 5 and 6 of the 7 segments, eol, and 1 to blink on both the external and internal display sections 4 and 6, and is mainly controlled by the j63 data.

The B4 signal is a signal that causes 7 segments 1 to 4 to blink on both the external and internal display sections 4 and 6, and is mainly used for J 63 and J
74 data.

The B3 signal is a signal that causes the AE mode display section of both the external and internal display sections 4.6 to blink, and is mainly controlled by the j62 data.

The B2 signal is a signal that causes the ISO mark on the external display section 4 to blink and is mainly controlled by 374 data.

The B1 signal is a signal that blinks all segments except for CAI and CA2, except for the segments output from 88 to B2. There is no particular data signal. However, including B1, from 82 to B8 Blinking control is performed by j20 data.

FIG. 23 is a code for the seven segments 1 to 8 and excluding cal, 1, eol, and 2 for displaying numbers on the inner and outer display parts 4 and 6. serial number
Evening J54-J57+470-J7L J75-J77
1 j21+ and external signal FW-1 plus dehood D
The output is controlled by each signal of q40 which is the C2 output signal, and the outputs are from r51 to r69, and each output is “Hi”.
gh'', each segment corresponding to it lights up.

FIG. 19 shows SW1, which selects signals.

The input signals are the aperture values of j12 to j16, and the aperture values of j22 to j16.
These are the shutter time value of j27, the ISO value of j32 to j37, and the timer count value of j40 to j47. One selection signal for each selection is the FON signal, CTR signal, ISO signal, and SS signal, each of which is "High". Sometimes NAND
When the date is open, the output data p=input data j. On the other hand, when it is "Low", the NAND gate is closed and the output data p becomes "High".

(Example) When FON='''High'', the outputs 012 to p16 transmit the inputs j12 to j16.

When FON="Lo-", output pi2-plG are all'
becomes “High”.

Next, although there are no detailed diagrams, DCI will be explained.

DCl is serial data j2 processed by SWI
2-j27. j32-j37. j40~”47
p22~p27+ p32~ρ37, p
FIG. 17 is a data converter (decoder) which inputs data from 40 to p47 and outputs data from q.1 to Q39 corresponding to a 7-segment 4-digit part.

Figure 18 is for explaining the concept of DCI,
The input data is 36 kinds of shutter speed values (SS values) corresponding to p22 to 27 (buLb-1/4000) and A
ISOS corresponding to LLHigh+ p32-p37
S value type (IS06~l5O6400) and ALLHigh
+Timer count value (CTR) corresponding to p40 to p47
There are 100 types (o'' to 99'') and ALL High.

For example, data p27~corresponding to SS value rbuLbJ
When p22="LLLLLL" is input (other data p32 to ρ37..4O-p47 at that time are set to ALLHigh)
It is processed with DC4 and SWl so that it becomes h. ) Output data is q7 data “b9” for segment decoder SDI, 018 data “L” for SC2, S
For C3, Q29 data is "U", and for SC2, q39 data is "b".

Also, data p37 to p corresponding to ISO value j200J
When 32="LHHHLL" is input, other data D22 to p2 L p40 to p47 at that time are ALLH
Processed with DC4 and SWI to make it bright. )
The output data is q1 for segment decoder SDI.
The data is q8 data for SC2, q21 data for SC3, and no data is output for SC2.

Also, ρ22~p27+ p32~ρ37. p40～
When p47 are all 'High', no output is output to the segment decoders SD1 to SD4.

All segments for SDI to SD4 are turned off.

It consists of a date circuit configured as described above.

Next, segment decoders SDI to SD4 shown in FIG.
I will explain about it. The data signals q1 to Q39 obtained in the previous section are respectively q1 to q7 to SDl and q8 to qlB to SC.
2, Q19 to Q29 to SC3, and q30 to Q39 to S
Input to C2. The internals of SD1 to SD4 are basically the same, but among the 14 inputs, the terminals to which the corresponding data signals are not input are pulled up to the power supply side in each block. For example, SD
When the q7 data signal (b of bu L b) is output to I, the rbJ input becomes “Low”. At this time, other SD
The inputs q1 to q6 of I and the inputs that are bullarp are "
However, the outputs (c), (d)-(e), and (f)-(g) related to the line that became ``LO-'' all become ``High'', and the other (a) + ( b), (h) line is “Low”, this output (c), (d),
(e), (1, (II) is r3 in terms of SDI terminal
~r7, which is input to the next stage CTLl,
This leads to the LCD display. This r output corresponds almost one-to-one with the liquid crystal segment (Fig. 16a, Fig. 2 bl cl 2
(see table). The output here (c), (d),
(e), (f).

(g) corresponds to the numerical segment name of each of the seven segments, and represents the character "6" (see Figure 2).

Further, for example, for S03, the q21 data signal (r2
When J) is output, the Lolo input becomes "Lo-" (a).

When (b), (d), (e), and (g) become "High", the character "2" is displayed.

p12 to p16 obtained by SWI enter the decoder DC2 shown in diagram #114. p16~p12="LLLLLL"
The output at the time is q40, and a "Low" output is output.

The output of q40 goes to segment decoder SD5 while it goes to decoder DC4.

Other outputs are connected exclusively to SDS.

The contents of the outputs of q40 to a62 based on the data of p12 to p16 include 23 types of aperture values shown in the concept of SDS shown in FIGS. 19 and 20. These are subjected to segment decoding in a part of the SDS shown in FIG. 15 (input parts of q40 to q62), and outputs of r30 to r43 are obtained.

For data "50 to" 53, decoder D in Fig. 11 is used.
There is C3. j50 data is decimal data,
A pt output and a p2 output are obtained.

The data j51 to j53 represent information 0 to 6, and the outputs thereof are p3 to p9, and the output is "High" and becomes active. This output is input to the switch SW2 in FIG. 12, and the output light is switched according to the selection information MON, +/-ON. When MON is “High”, +/-ON is “Low”
”, and the outputs of p2-p9 are inverted and are 082 to 0.
89, but q71 to q78 are all “High”
h”, -Rikishi/-When ON is “High”, MO
N is "Low", and the outputs of p1 to p7 are inverted and output to q71 to q77, but q82 to q89 are all High, and 078 is "Low".
MON.

When both +/-ON are low, q71-478+q
The outputs of 82 to q89 all become "High".

The output of SW2 is Q71 to q78 to SDS, q82 to q
89 is output to SC2.

Q71~q78+ q82~Q8 output by SW2
The contents of 9 are 071 to q7 as shown in Figures 19 and 120.
8 is 7 kinds of numerical values for override value and 1 kind of decimal point, q8
2 to Q89 correspond to 7 types of integer digit values for metered manual values (including override values) and 1 type of decimal display.

The contents of 11SD6 are not shown, but the basic idea is
This is the same as SDI to SD4 in FIG. 3, and FIG.

The date structure is such that there is a relationship between the data shown in FIG. 20 and the output display example.

Finally, r made by SDI~SD6 and DC4
l-r69 and Bl-B8. ON, OFF signals, and φ1. When the clock is input, the output control section CT
LI will be explained.

The internal configuration of CTLI is already shown in FIG.

r69-369+ Except for the configuration of the S70 part, the configuration is basically as shown in Figure 16a. *In Figure 16, when a "High" signal is input to r69,
The date for S70 opens and repeats “High” + “Low” with the clock of φ1°, but S69 and 8
70 outputs in reverse phase. In this way, the corresponding CA1.
The CA2 mark lights up alternately, giving the impression that the camera mark is blurring. Regarding circuits for signals other than r69, logical expressions and truth tables showing the relationship between the output S and the input r are shown in Table 1.

As shown in this table, when the ON signal becomes "Low", all the outputs S except 869.S70 become "Hillb" and all the display contents except CAL and CA2 light up.

Next, when the n signal is “High”, the OFF signal is “High”.
gh'', all the outputs S except S69 and S70 become Low'', and all the displays except CAI and CA2 turn off.

When the ON signal is "High" and the OFF signal is "Lo@", when Bm (Bl-88) becomes Low, the output S=
r, and lights up and displays the display contents according to the display information given in the serial data.

ON signal is 'High'', OFF signal is Low''+8m
Any part of (Bl to B8) is set by DC4 as "
When it becomes High, the output S corresponding to r in the same group will be displayed according to the current display content according to the clock of φ1. Flashes.

For example, the B6 signal is 'High' and the other 8l-B
S, B7. When the B8 signal is Low, the corresponding outputs S59 and 86 of 59 and r60 in the 86 signal group
0 repeats “High” and “Low”.

However, if the status of ``59 and 60 is ``Low,'' 859 and 860 cannot become ``High.'' Therefore, As2 and AS corresponding to S59 and 360
If I is lit, it will change to flashing.

The outputs 81 to 870 obtained by the above CTL1 are input to the segment drivers (Fig. 6), and output as the liquid crystal drive waveform (see Fig. 27) to the final output SEG terminals (SEGI to 5EG35). .

The relationship between CTL1 output S and SEG terminal is shown in Table 2.
The names of the segments shown in this table are the same as the names of all the segment diagrams shown in FIG. 2C.

1. When the camera is started - When the camera is started by turning on the main switch SM, the cPUlo is interrupted and the CPUIO is released from the stopped state, and the camera starts operating according to the program in the internal ROM. At the same time, voltage is supplied to a photometric circuit (not shown), but it takes several tens of +5 seconds for the photometric circuit to operate reliably and provide the necessary data to the CPU 10.
c time is required.

However, the CPU 10, which operates at high speed, has communicated serial data with the display circuit section one or more times at this point. The contents of the serial data communication (see Figure 36) mainly include exposure information such as shutter speed and aperture value, but the accuracy of these exposure information may vary when the photometering circuit etc. is not operating normally. Therefore, communicating serial data in this state is not only meaningless, but also erroneously displayed, so it is not a good idea to do so. In the darkness until the calculation is completed, by sending data to turn off the lights or data for standby display, it is possible to avoid displaying troublesome and inaccurate values on the display. As long as there is no serial data communication, the previous display is retained.Using this, up to the calculation light, there is no particular problem as long as there is no serial data communication, but the CPU
Since the program 70- for l0 is created in such a way as to avoid exceptions as much as possible, it is better to communicate serial data at regular intervals in the sense that it does not increase the capacity of the ROM for the program.Therefore, the method described above is better. The method is better.

Immediately after a battery is installed in a camera, +E voltage is applied to the CPU 10 and the display circuit section 20, and each starts operating. Each circuit has separate crystal oscillators XLI and XL.
2 and starts operating independently, but in this case XL
Since I has a higher frequency than XL2, it is generally
LI starts oscillating early. After the 0 oscillation starts, CPU10 starts operating according to the internal wSROM program, but since there is little work to be done immediately after the battery is installed, it takes several tens of five e.
It goes into a stopped state at about c and stops functioning, waiting for it to be woken up again. Generally, at this point, the oscillation of XL2 of the display circuit section 20 rises (generally 100s+See~1
3) When the XL2 oscillation of the display section is not performed, serial data communication with the CPU 10 is not accepted. In Figure y17, a-2 does not occur, so it does not operate as shown in the time chart shown in Figure 26, and no LTCH pulse is generated.
Even if oscillating, the data in the display circuit section 20 is not rewritten unless there is serial data communication. Since the N4 configuration is such that the pulse does not occur, the CPU as shown above
(In IE, the display content continues to be displayed indefinitely depending on the battery installation status, which is not good. Therefore, the j10 reset, jll set, and
One countermeasure is to prevent the initial indefinite display by turning off the power for driving the LCD using a power-on reset circuit as shown in FIGS. 24 and 25. Furthermore, if the power-on reset circuit is not working properly for some reason, or if it is not good for the light to remain off for a long time, serial data communication from the cPUIO will continue until Fl11 when the XL2 oscillation rise is guaranteed after the battery is installed. As a result, as soon as the oscillation of XL2 starts, normal operation starts and the display contents change immediately. The contents of the serial data at this time may be data for turning off the light, data for standby display, or any other arbitrary data.

Therefore, the CPU operates after performing the necessary processing immediately after the battery is installed, and when the XL2 oscillation rise is guaranteed.
11*, serial data communication is performed using display data, and after a predetermined period of time, if it is not necessary, the function can be stopped and stopped.However, within the guaranteed rise time of XL2 oscillation, the CPU 10 is Interrupt operations must be prohibited.

- Before the CPU 10 stops - Immediately before the CPU IO stops its operation, the CPU 10 sends standby mode display data to the display. After that, until the CPU 10 starts up again, there is no data transfer, so the display remains unchanged and the standby mode display continues. Just before the main switch SM is turned off and the CPU 10 stops operating, the CPU 10 displays the same message as above. Sends display data for lights-off mode to . After that, there is no data transfer until the main switch SM is turned on again, so the display remains unchanged and remains off.

-ALLON, AL, LOFF- Serial data JIOI jll is the most prioritized data that completely turns off the LCD power supply.

jlO・jll; Lights off when “High”.

On the other hand, data j66 and j67 are prepared for connection checking and are second priority data. j67
When j66="High", a waveform in which all segments are lit, and when j66="Low", a waveform in which all segments are extinguished are output from the COM and SEG terminals, respectively. When each waveform is applied to a normally connected LCD, it will display whether all the lights are on or all the lights are off. However, if the connection to the LCD is misaligned, a part of the LCD may turn off or turn on, or the brightness may be different from the other segments, indicating that there is an obvious connection error. Become. , 11 Also, as a method of providing signals for serial data communication, 5DA
By connecting the TA line to +E through a small resistor, that is, pulling it up, all serial data will be
It becomes "High" information, the priority bit J67 becomes active, and it becomes all lighting mode. On the other hand, when it is connected to GND, that is, it is pulled down, all the serial data is "
Two bits are “Low” information and 36 are priority bits.
6 comes to life and goes into all lights out mode. This is a very simple check even after the camera is assembled.

Furthermore, there is no need to provide a dedicated terminal (which is ideal).

- Off mode and standby mode - Figure 35 shows the display on the external display section 4 in standby mode. Only the bar is lit and all other external displays and internal displays are turned off. As for the camera body, cp
ut o is in a stopped state and is waiting for an input corresponding to an interrupt instruction. Also, power is supplied to the display circuit 20, but no power is supplied to any other circuits (not shown) other than the CPU 10. However, when an interrupt input such as a photometry switch is input to the CPU 10, power is supplied, The circuit also starts working and starts functioning as a camera.

On the other hand, the display in the lights-out mode turns off all displays.

The method is to turn off the LCD drive power by 0FFV LC.
When D is set to "High", the camera body operates only in a stopped state where the CPU 10 is waiting for an input interrupt from the 8M terminal, and there is no power to any other circuits except for the display circuit (not shown). Not supplied.

The main difference between standby mode and lights-off mode is that in lights-off mode, only the main switch SM is active. On the other hand, in the standby mode, other operation start switches such as a photometry switch (not shown) come into play. Further, the current consumption is lower in the off mode, which is energy saving, and the voltage applied to the liquid crystal is zero in the off mode, so the liquid crystal has a good shelf life.

- Manually configurable data indication marks - Figure 29 a, b
In the A mode, since the aperture can be set, the mark 4TA2 on the aperture value side is lit, and the mark TAI on the shutter speed side, which cannot be set, is turned off.

Similarly, in the S mode (shutter priority mode) shown in Fig. 30a and b, since the shutter speed can be set, the beak mark TAI on the shutter speed side is lit, and the one on the aperture value side, which cannot be set, is lit. Mark TA2 goes out.

In Figure 31 i and b, in manual (M) mode, since both values can be set, both black marks TAI and TA2 are displayed.
lights up to indicate that both can be set.

When pressing P in FIG. 28, there is no settable numerical value, so both marks go out to clearly indicate their meaning.

In addition, to turn on or off these marks, use j72 + J73.
The AE mode information is used for control.

However, if a function (not shown) for determining the presence or absence of a lens determines that the lens is closed, the aperture of the lens cannot be set. Therefore, in this case, the setting mark TA2 regarding the aperture is specially set not to light up regardless of the mode. This is controlled by the q40 signal shown in FIG.

1-Open F value display - The aperture value display is a 7-segment numerical display as shown in FIGS. 28 to 31. The contents of the aperture value are shown in Fig. 20, where the rq40J signal is -1 indicating a state equivalent to no lens, and rq433 to rq62J are 0.5EV.
This is the aperture value for each. On the other hand, the open F-number of a lens has conventionally popular values such as 3, 5, and 4.5.

However, these values are not multiplied by the aperture value for every 0.5 EV, so these values are treated as special and prepared as rc+41J and rq42J signals. In this way, the result of the calculation performed by the CPU 10 or the set aperture value is the aperture value (?!l determination is made by an unillustrated aperture signal), and furthermore, the 3.5 in this embodiment is
Or, when it is 4.5 mag, the CPU 10 changes the normally displayed 3.4 color to 4.8 mag, and displays 3.5 or 4.5 mag.
1 display signal is given. Further, when the result of the calculation performed by the CPU 10 or the set aperture value is not the aperture value, the normal display such as 3.4 or 4.8 is used for display.

The above two series of display formats are provided.

As an example, a display example of the open F value is shown in FIG. 33 a+b.

The open F value is determined, for example, as follows.

As shown in Figure 40, in step S1, the control CPU10
reads the aperture F4@jAvo from the lens 3 and stores it in the internal register.Meanwhile, the CPU 10 uses the calculated F value Av calculated in step S2 based on the camera settings and the value obtained from the photometry results, etc., and reads it in step S3. Avo=
Av is determined, and if Avo=AV, the open F@Avo is extracted (step 84), and if Avo≠Av, the calculated F value Av is extracted (step S5), and the data of j12-j16 (AvD S P ) is The determined output is displayed on display WS4 and WS6 (step S6).

1 Override view and metered manual quantity display - Figure 31 +6.5 is the deviation amount of metered manifold 1 full, and is the only internal display of infining - 5 display suru range that is always lit when manifold is full is +6.5
--6.5 EV (see Figure 20), and when that amount is exceeded, +6.5 and -6,5 will blink and display the data at 6 blinks. j61? ”-ta(F)M'dM
OVER+6'-Hi@h" is set.

Also, +1.5 in Figure 33 is the override amount,
Depending on the settings, it always appears when in AE mode other than at manifold. Similarly, it is only the internal display of infying-1
The displayed range is +4.0 to -4.0EV (see diagram 1N20), and settings cannot be made beyond that amount.The override display is always blinking to distinguish it from the metered manual. At the same time, draw attention to override settings.

On the external display, +/- symbols (OR+,
OR-, 0R6) lights up, but in metered manual mode the +/- symbols (OR+, OR-) are lit.

0R8) is turned off and not displayed.

In order to receive and receive the data of each quantity of override and metered manual using the register,
An identification signal is required separately from the original.

This signal is provided by the 5IGN signal of j54 to j56 data.

Table 3 shows the relationship between the data contents of ``54 to j56'' and their output display states, which makes the portions related to j54 to j56 of FIGS. 21 to 23 easier to understand.

-8 and A mode display- The display mode is shown in FIG. 29 and FIG. 30.

FIG. 29 shows the display in A mode, and the A mode display section with an arrow pointing toward the manually settable aperture value display lights up. Figure 30 shows the display in S mode,
Light up the S mode display with an arrow pointing toward the display of the manually settable second time value. By doing this, the meaning of the mode display and the meaning of the numerical display can be understood at a glance, making the mode display very easy to use.

Figure 38 an b shows the display contents during the initial loading after the film is loaded. During the initial loading period, when the film is not fed, the shutter speed is 1/4000 seconds and the aperture value is controlled at the minimum (F22 in this case). be done. At that time, all the exposure mode V displays have disappeared, but this is because the j75 bit is set to "High" and the mode display is extinguished.

Figure 39 at b shows the display contents when the lens is not attached.
If it is detected that there is no , all of the display j12 to j16 are set to Lo@''. This is done in step 818 of the chart 7a in FIG. 41, and the display decoder that receives this is Q40 in FIG. Put out the signal and turn to F62 in Figure 23.
Set it to ``Low''. Therefore, it is displayed as the aperture value.
1 is displayed, and the aperture chain side mark TA of the settable mark is displayed.
2 disappears.

Note that FIG. 42 shows another embodiment in which the camera movement of the internal display section 6 is displayed. In this case, the upper part of the figure (@)
, consists of three segments as shown in 1, and lighting up two of these segments indicates the type of camera. There are two types of selection of these two segments: (b) and (c). Camera shake is displayed by lighting these two types alternately.

FIG. 41 shows an outline of the operation of the control CPU10.

By installing the battery, the CPU 10 starts operating from a reset start (step SO), and at the same time, a voltage is applied to the display circuit. *In fcpuio.

Perform initial settings for both cameras (step 510)
Then, display data, turn-off data, standby data, ISO data, etc. are sent to the display circuit n times (step 811) (n is a value determined according to the time it takes for the display circuit to guarantee normal operation). When finished, interrupts from a switch group (not shown) are permitted (step 512).
, and if there is nothing, the internal operation is stopped and the state is stopped (step 513). Among the switch groups (not shown), the photometry switch 81 or the initial mead switch SB is connected to the main switch SM by the 44th switch. There is a relationship as shown in the figure, and the other switch groups have the same configuration as Sl and SB. When the main switch SM is OFF, the SL and SB large inputs are pulled down and the SL.

S8 input is dead. In this state, only the SM signal generates the INTseL signal that generates an interrupt. When the main switch SM is turned on and the INTset signal is generated, the INT7 lip (not shown) is set, and the CPU10 performs an interrupt operation INT (step 514).
The one input INT7 lip 70 is set at the rising edge, and interrupts are enabled (step 512).
), the INT7 flop is reset and waits for another interrupt.

Now, when INT (step 514) is entered, check the switch SB that detects the initial load state (step 515). If it is 0FF (not in the initial state), power is supplied to the photometry circuit (not shown), etc., and step 3
Start photometry at 16. After that, in step S17, AE calculation is performed, display data necessary for the display circuit is prepared and sent out in step 818, and then the main switch S
M is checked in step S19, and if it is OFF, data for turning off the light is sent as display data in step S20, power supply is stopped, and photometry is stopped in step 821. After that, step S12. The process proceeds to step S13, and if the main switch SM is ON in step 819, the switch S1 is checked (step 826) L, and if it is OFF, data for standby display is sent out as display DATA, and step S16. S21.812. Proceed to S13,
If the status is ONL in step 926, the release switch 82 is checked in step 322. If ON, exposure control (step 523) is performed, and step 817
However, if it is OFF, the process proceeds to step 817 without doing anything and performs the AE calculation again.

On the other hand, if the switch SB that detects the initial load state is ON in step 815, the second and aperture values for the initial mead and the MODE OFF information 5 data = "High" are sent out in step S24, and the Initial loading is performed to control the shutter mechanism using the second value and aperture value (step 525), and then the switch SB is checked again in step SIS, and depending on the state of switch SB, the photometry starts in step 316. enters.

As shown in FIG. 44, the transition from step S13 to step 814 depends on the switches SM, SL, and SB.
At F, the Sl and SB switches are in the "Low" state and are dead as switch signals. Therefore, S.M.
The INTseL signal is generated only in response to the ON of S M h'o N 1 and enters the interrupt (INT) operation.
F) Lil;t S 1 + S B X E/ +
INTset by 81 or SB in lj'live rice
A signal is generated and interrupt (INT) operation begins.

Although the SB switch is not shown, it turns ON when it detects the presence of film and that the back cover is closed, and turns OFF when the film counter (not shown) reaches 1.

FIG. 43 is a 7th chart showing the detection operation for the hand 4I, and in step S31 the CPU 10 reads necessary information such as the focal length from the lens.
1, and in step S32, go to exposure calculation and calculate the TV value for shutter control,
The TVL value of the camera shake warning eye field is calculated from the lens information.

Then, in step S33, the size of TV and TVL is compared, and if the TV (if TVL) is YES, the process proceeds to step 834.
T V > T V L Oak+r N Ot' X
? Proceed to v step S35, LOWSS in step S34
Set the signal to ``High'' and mark CA1. Vibrate CA2 to issue a camera shake warning and turn LOW in step 835
Marks CA1 and CA2 are turned off as the SS signal goes low.

w & 44 Figure 1 shows the relationship between fcPU10 and A4-z+s1+S2°SR,SM.

tJ41 table <combination of r2n and B-> Bl -r51- r53. r61- r652-r
54 83-r55-r58. r67, r68B4 −
rl -r29 BS -r30- r43 BS r59. r60 B7 -r44-r50 8-r66 Table 2 Table 2 (Standard) Table 2 (continued) #l311 ■Turtle.

Effects of a once-in-a-lifetime invention As detailed above, this invention displays the nominal aperture value when the aperture value used in the camera's display am is not in units of 0.5EV. When the camera is used, the displayed value does not differ from the nine nominal aperture values of the lens, as is the case in the past, and it is possible to avoid giving a strange feeling to the user of the camera.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing an example of a camera to which the present invention is applied, FIG. 2 1 is a front view of the camera shown in FIG. 1, and FIG. A diagram showing an example of all segments displayed. FIG. 2C is a diagram showing an example of all segments displayed on the internal display section of the display device of the present invention. FIG. 3 is a block diagram showing one embodiment of the present invention. Figure 4 is a detailed circuit diagram of the oscillation branch in Figure 3, Figure 5 is a detailed circuit diagram of the common driver in Figures #&3, and Figure 6 is
The figure shows a detailed circuit diagram of the segment driver in Figure 3, and Figure 7.
The figure is a detailed circuit diagram of the data latch section in Figure 3, Figure 8 is a detailed circuit diagram of the decoder shown in Figure 3, Figure 9 is a detailed circuit diagram of the switch circuit SWI in Figure 8, and Figure 10 is a detailed circuit diagram of the switch circuit SWI in Figure 8. The figure is a circuit diagram showing details of symbols in the circuit, Figure 1111 is a detailed circuit diagram of the data conversion section, and Figure 12 is the switch circuit SW of Figure 8.
13, 14 and 15 are detailed circuit diagrams of the segment decoder of FIG. 8, and FIG. 16I!
la is a detailed circuit diagram of the output control section in Figure 18, Figure 16 is a detailed circuit diagram of a part of the circuit in Figure 18, and
Figures 7 through 20 are diagrams showing the relationship between input signals and displays, Figures 21Qi through 23 are detailed circuit diagrams of the data conversion section in Figure 8, and Figure 24 is a detailed circuit diagram of the voltage generation section in Figure 3. Detailed circuit diagrams, Figures 25 to 127 are waveform diagrams of the main parts of the circuit in Figure 3, Figures 2-8a, Figures 28 to 34, Figures 34 and 35 are FIG. 36 is a diagram showing various aspects of display; FIG. 37 is a diagram showing the relationship between signals and rexta; FIG.
Figure a * bte + Figure 38 mobs Figure 39 a. b is a diagram showing various aspects of display, FIG. 40 is a table
41 is a 70-chart showing the selection operation of the CPU shown in FIG. 7 of the CPU showing the operation of
0-Chart, FIG. 44 is a circuit diagram showing details of a portion of the CPU of FIG. 3. 4... External display section, 6... Internal display section, 10...
CPU, 22...Data latch, 23...Decoder, 24...Segment driver.

Claims (1)

[Claims] (1) In a camera that displays an aperture value, a first display control means that displays an aperture value in increments of 0.5EV;
a detection means for detecting that a lens having an open aperture value that deviates from the aperture value for each V is attached; A display device for a camera, comprising: a second display control means for displaying a nominal open aperture value when the aperture value is off.