JPS61141427A - Display device of camera - Google Patents

Abstract

PURPOSE:To make the identification of a standby state from other states possible by displaying a set photographing mode in the operating state for photographing, putting out all the segments in the stop state and displaying the specific segments in the standby state. CONSTITUTION:The on-off of a main switch and the operating state of a camera can be distinctly discriminated by putting out the segments when the main switch of the camera is turned off and displaying the standby when nothing is done while the main switch is on. More specifically, the camera is put into the standby state and an FON signal is brought to a 'Low' when PWC rises to a 'High'. The information on the aperture value is then erased by a SW1. The standby state isdisplayed in the above-mentioned manner, then the reduction in the electric current consumption is made possinble when the operator thus off the main switch during the display of the stnadby state while the camera is not in use.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a display device for a camera.

Problems to be Solved by the Invention In a camera that applies a signal obtained from a pull-up resistor connected to a main switch to a control 2II device, it can be determined whether the main switch is on (on) or not (on). Even when the camera is inactive, the current consumption differs depending on the circuit.

Therefore, when the main switch remains on and the camera is in a so-called standby state, which is the operation readiness state 3, unnecessary power will be consumed during that time if the camera is not used.

Conventional technology As a method of clearly indicating that the main switch is on, for example, when the main switch is turned on (L
A technique is known in which each mode display at that time, settable numerical values, counters, etc. are turned on when the OCK is released. However, the content of this display differs depending on the exposure mode, and there is a drawback that the operating state S of the camera at that time cannot be determined.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a camera display device ml- provided with a display means for displaying the standby state Jf of the camera so that it can be distinguished from other states.

Structure of the Invention The camera display device of the present invention has two states: a stopped state in which the main switch is turned off, and a standby state in which the main switch is turned on but the camera is not in the shooting operation state yet.
The present invention is characterized in that it has a display means that displays a set photographing mode in the photographing operation state, turns off all lights in the stopped state, and displays a specific segment in the standby state.

Effect With the above configuration, the display means turns off when the main switch of the camera is turned off, and displays a standby display when the main switch is on and nothing is being done. The operating status of the camera can be clearly distinguished.

By displaying the standby state as described above, if the standby state is displayed when the camera is not in use, the operator can reduce consumption by turning off the main switch. . Further, it is possible to eliminate the annoyance caused by unnecessary display when the camera is not performing photometry or the like.

Embodiment FIG. 1 is a diagram showing four parts of a camera to which this invention is applied. 1 is the camera body, 2 is a gloss button, and 3 is an interchangeable lens lever. Inside the interchangeable lens 3 is the data of the lens, such as the maximum aperture value. A device is provided that outputs data indicating such information as an electrical signal to the camera body. In addition, the shiny button 2 has an α1 button that operates according to the extent to which the button is pressed.
An optical switch 51 and a release switch S2 are provided by a known method.

4 is an external display section, and the calculated EVIL! It is designed to display various data, which will be described in detail later, depending on the mode and operation mode.

5 is a finder, and within the field of view of this finder 5 is provided an internal display section 6 (see FIG. 2) for displaying data and the like displayed on the external display section 4.

SM is the main switch.

FIG. 2 shows details of the external display I] 84, and from the top there are PROCRAMS for AE mode display. A
When E mode is program mode (hereinafter referred to as P mode), PT' (OCRAM is displayed and S is turned off; when in aperture priority mode (hereinafter referred to as °A mode), A is displayed and PROCR, MS are displayed. The light goes out.Manual mode (hereinafter referred to as M
mode) and time priority mode (hereinafter referred to as S mode), M and S are displayed, respectively. Below that is the SO mark in ISOS-mode, immediately below is a 7-segment, 4-digit SS, ISO, and CTR display, and to the right of it is a setting instruction mark TAI. Below that, there is a bar display that only turns off when the camera's main switch SM is turned off, and a 7-segment, 2-digit F, +/- display, and to the right of it is a setting display. There is an instruction mark TA2. To the left of the two digits is an aperture value discrimination mark F, and further to the left end is a +/- mark, which is a sign when setting an override.

Furthermore, FIG. 2C shows details of the display on the internal display section 6.
Starting from the left end, there are 2 adjacent images for displaying camera shake (camera shake).
Mark CAI has two camera shapes.

There is CA2, followed by 7 segment 4 digit SS.

150, a CTR display section, and then S, P, and A for AE mode display. The S mark consists of a 7-segment arrow pointing toward the 4-digit side to indicate shutter speed priority.
Similarly, the A mark is located immediately to the right to indicate aperture priority.
It consists of an arrow pointing towards the 2-digit segment. The P mark has nothing to do with prioritizing both aperture and seconds, so there is no arrow between S and A.The 7 segment 2 digits on the right side for displaying AE mode are for displaying the F value and during F/- mode. Displays the +/- value of. Immediately to the right is the M for AE mode display.
There is a mark. This is because the metered manual display lights up at the same time, so it is displayed near the meter display to make it easier to understand. To the right of it are the override metered manual signs, + and -, followed by a 7-segment numerical value band. This numerical value band displays +/- values during AE mode (P, A.

(S mode only) and metered manual value display in AE mode (M mode only).

Finally, the metering mode display is AS! There is a Tohe S2 mark, and during average metering, only the ASI lights up, and during partial metering,
Both ASI and AS2 are lit.

Fig. 32 a, b and Fig. 33 a, b show the override, but the place where the override value is displayed in the finder internal display is the override C +/-
) mode and AE mode. This is an attempt to display information near the center of the display section during override mode display to make it easier to understand.

FIG. 3 shows the overall configuration of the control device related to the above-mentioned camera display. The CPU+O, which uses a central control microcomputer that controls the operation of the entire camera, is supplied with power +E from the battery 11, includes a main switch SM pulled up by a resistor R, a reference oscillator XL1 for operating the CPU10, and peripheral circuits ( Especially regarding the display), the group of monument signals.

cs, pw, and the norial data S, DATA, and norial clock SCK necessary for norial transfer of data.
is connected to the surrounding area.

An outline of the operation of CPU10 will be described later.

On the other hand, the display circuit section 20 receives the power supply element E from the battery 11 and the main switches SM, CP (signals from JIO).
, 5DATA, SCK, reference oscillator XL2. A reference power supply 21 for driving the liquid crystal is input, and outputs include a group of driving outputs for common and segment electrodes of the external display section 4 and internal display section 6 using a liquid crystal display. The drive output terminal group.

It is connected to the external display section 4 of the camera connected in parallel and the external display section 6 inside the finder.

Inside the display circuit 20, there is a data latch section 22 that latches norial data. Decoder section 23 that decodes the latched data. Segment driver [2] drives the LCDs of external and internal display sections 4 and 6 using decoded signals.
4. Common driver section 25 that drives the common section of LCD
．． Oscillating needle that creates the operating clock for each part! ! Part 4 26.
There is also a voltage generating section 27 that generates a driving voltage for the LCD.

FIG. 4 is a detailed diagram of the oscillation frequency divider 26 shown in FIG.
and a flip-flop (FFI) that divides this reference oscillation.
) and a frequency dividing stage with a +a component. The flip-flop FFI is provided with a reset terminal R so that it can be initialized by installing a battery.

FIG. 5 is a detailed diagram of the common driver section 25.
, VLCD2. Each voltage of VDD is connected to analog switch A.
φ1. through SI~AS4 and PchFET FPl, FP2. The 4111F is configured to output to COMI and C0M2 at the timing of φ1°. Nantes Gate NAI, 2
．． (Noage ~) NRI, 2 and inverter IN3.4 are gates for creating timing, respectively.

FIG. 6 is a part of a detailed diagram of the segment driver g524, and shows VLCD2. The analog switch AS5 and PchFET EP3 for switching each voltage of VDD are made of φ1. φ,. Among the timings of S2n and 52n for segment electrodes,
It is configured to be driven in accordance with the -1 state. Nant gates NA3 to NA7 and inverter IN6.7 are S
2n, 52n-1 constitute a clock selector,
Innovata! N5. The frib flop FF2 is φ1. φ
,. A clock generator is configured to create clocks with four types of phase differences.

The entire segment driver section is of the type shown in FIG. 6, in which the clock selector, analog switch, and PchFET parts are prepared in the number of SEG output devices, and a clock generator is added.

Figure 7 is a detailed diagram of data latch country ≦22.
There are seven 8-bit Novutrenosk SRI to SR7 that are powered by Norreal Data 5DATA, and these 7
There are seven 8-pin parallel outputs that each latch at the falling edge of the TCH signal.
7 is connected.

A reset R input is applied to the lO data of the latch LTI, and a set S input is applied to the Nl data.
The OIt times signal is reset and set. Therefore, the initial situation is j10="Low", jl I="
High”.

On the other hand, the external Norial clock SCK is passed through the OR gate OR+ as the φS signal (N113 to N113).
It becomes the input of R9, and also serves as the φλ power of the counter decoder CD. Set input s of counter decoder CD
When h<High”, output B5 of counter decoder CD
l-B57 are all “High”, and Kaka<L to S
os'', one from BSI to BS7 becomes 1 LO view for every 8 pulses of φλ force.

When any of B11-B57 is “Lo tube @,”
One of the corresponding NOR gates NR3 to NR9 becomes active, and the φS signal, which is the input of the NOR gate, is transferred to one of the
Enter the λ force. In the external control signal FW from the CPU 1O, y is logically summed by the OR gate OR3 to become the P-CS signal, which is input to the other input of the agate OR+ and the S input of the counter decoder J. do. Also, it becomes one input of OR gate 0112, and OR logic is taken with the other input BS7, and flip-flop FF3
and one input of the nut gate NΔ8.

In the flip-flop FF3, the FOR signal is inputted to the set power S, and the 6-output is connected to the other power of NA8. Further, the φ output of FIG. 4 is connected to the φ input of the flip-flop FF3.

FIG. 8 is a detailed block diagram of the decoder section 23 of FIG. 3, and is a detailed block diagram of the switch circuit SW1. SW2. Data change Kuwabe DCI ~ DC
4. Segment decoder sections SDI to SD6. It is composed of an output control flcTLI. The switch circuit SWI receives the output j12~ of the decoder 22 as an input.
j16. j22-j27. 332-j37. j4
25 outputs of decoder 22, 50 to 53, are input to the data conversion IDc3, and outputs jlO and 2 of the decoder 22 are input to the data conversion unit DC4.

+20. ko21. +54~ Ko57. j6
A total of 53 wires, 24 wires from 0 to +67 degrees 470 to j77, are connected to the outputs of latches LTI to T7 in FIG.

Further, two signals SM and PWC from the main switch shown in FIG. 3 are input to the data converter DC4. As shown in FIG. 4, φ14 is connected to the output controller section CTLI as a human power source, and 70 outputs of 5l-S70 are connected to the segment driver section 24.

FIG. 9 is a detailed diagram of the switch circuit SW+ in FIG. 8,
jn from data latch 22 (n = 12 to 47 (excluding 17.20.21.30°3!)) - Pi (
FOM, CTR, ISO using 25 Nant gate NAs for 25 signals from n=12 to 47 (excluding +7.20, 30°31).

It is switched by the SS signal. FON, CTR.

When the ISO and SS signals are “Low”, the Pn signal is -
High” and the jn signal is cut off, but the FON.

When CTn, IsO, and SS signals are “High”, Pn
= jn, and the switch is turned on.

FIG. 10 is a diagram explaining the symbols used in FIG. 11, FIGS. 13 to 15, and FIG. 23, including A, B, and C.

For each human power of D, by marking the intersection of the arrow with the output Q, the I! Show ability. That is, Q=BD.

FIG. 11 is a detailed diagram of the data conversion unit DC3 in FIG.
The logic of outputs p1 to p9 is shown for inputs j50 to j53. This output serves as an input to the switch circuit Sw2 shown in FIG.

FIG. 12 is a detailed diagram of the switch circuit SW2 of FIG. 8, and represents the logic in which inputs p1 to p9 are switched to q71 to q78, 482 to Q89 by the switching signal MON and the +/-ON signal. The input p signal is input to the Nantes gate, the switching signal M ON and the ±/-ON signal are °L Ov”
When , the output q signal becomes "IIigh" and the p signal is cut off. When the MON, +/-ON signal is "High", the output q signal becomes equal to the input p signal, and the switch is turned on (3).

Figure 13 shows segment decoder sections SD1 to 5D in Figure 8.
In the detailed diagram of 4, outputs r1 to r2 for inputs q1 to q39.
It shows the logic of 9. This diagram shows the segemenoto decoder section 5.
Since the basic configuration of DI-5D4 is the same, they are shown in the same drawing, but the important parts of 5DI-5D4 have been extracted from this figure. This output is an input to the output control section CTLI shown in FIG.

FIG. 14 is a detailed diagram of the data converter DC2 of FIG. 8, showing the logic of outputs q40 to Q62 for inputs p12 to p16. This output is from the segment decoder SD in Figure 8.
5 input.

FIG. 15 is a detailed diagram of the segment decoder i<SD5 in FIG. 8, in which inputs q40 to q62. The logic of outputs r30 to r43 is shown for q71 to Q7B. This output is an input to the output control section CTLl shown in FIG.

FIG. 16a is a part of a detailed diagram of the output control section CTL1 in FIG. 8, in which outputs of 81 to 570 are obtained by the outputs of the segment decoder sections 5DI-9D6 and data conversion section DC4 and the clocks φ and 4. .

In this figure, r2n and Ba are shown in arbitrary combinations, or are actually connected in combinations shown in Table 1.

Table 1 shows a truth table by replacing the circuit diagram of FIG. 16a with logical expressions. Furthermore, the combination of r2n and B garden is specifically shown. (I≦self≦8).

(1≦2n≦68) r69 is shown in FIG.

Figure 16 shows the logic to input ``69'' and outputs s69.s70.

FIG. 17 shows the relationship between the outputs q1 to q39 of the data conversion unit DC1 of the decoder unit 23 and the characters displayed on the display units 4 and 6, and the data conversion unit DC! Inputs p22 to p
27. p32-p37, p40-p47. When Ql~Q39 is output according to the state of CTR, Ql~Q39
The displayed characters are controlled according to the state of ``°L, ow'' or ``High''.

In other words, if the output q1 is "High", 5D11, so the 10" digit on the display section 4 (upper and 6) is displayed as 0゜q2h
If it is “High”, the 10° digit will be displayed as 2, and the Tsuyatsuta Hayakei SS value is p22~ρ27.1
For the 50 value, data is given at 932 to p37. For the CTR value, data is given at p40 to p47 and the CTR signal, respectively. Also, p22-p27゜p32-p37, p40-p
47 are all "High", no output is output for that data. Therefore, for example, when the data of p22 to p27 for the Tsuyabuta speed SS value is output, the data of p32 to I)37 of the pond is output. .1)4
It is configured by a data converter DC1 and a switch circuit SWl so that all signals 0 to p47 are set to ``High''. (See Figures 9 and 21.) The contents that can be displayed are illustrated in Figure 18. 36 types for SS value, 31 types for ISO value, CTRIa
ni t”l!I 0ONI6ru.

FIGS. 19 and 20 are diagrams showing the relationship between the data of the data converter a DC2 and the switch circuit SW2 and the characters displayed on the display units 4 and 6, and the input of the data converter DC2,
p12 to p16 and p1 to p9 of SW2, MON, +
/-q40 to q62. depending on the ON state. q71～q7
8. The outputs of q82 to q89 output data as shown in this figure. p12 to p16 for rr value, pl-9 for override value and metered manual value
Each data is given in 9.

Figure 21 is ;F! 8 is a part of a detailed diagram of the data conversion unit DC4, showing the switch switching signals MON, +/-ON, FON of the switch circuits SWI and SW2.

The logic of CTR, ISO, SS,
The logic of the OFF signal and the logic of the OFF V LCD signal applied to the voltage generator 27 in FIG. 3 are shown, respectively.

The input signal is the output J signal of the data controller 1,
jl 1. Ko55. j56. j60
- j67゜jl0. Core 1 and external signal, SM,
is Vσ.

FIG. 22 is a part of a detailed diagram of the data converter DC4 of FIG. 8, and shows the logic of signals 81 to B8 of the CTL1 section.

The input signal is the output signal j20. j55
~j57. j61-j64° j70-j74 and the external signal "Wte".

Figure 23 shows the data conversion ff! of Figure 8. A part of the jT detailed diagram of DC4 shows the logic of the r51 to r69 signals of the control unit CTLI. The input signals are the output signals of the data latch section j21, 354~j57゜j70~37s, j75
~j77 and the output signal of the DC2 section q40. and an external signal "Vσ." In FIGS. 21 to 23, the data converter DC4 in FIG. 8 is all included.

FIG. 24 is a detailed diagram of the voltage generating section 27. Create a reference voltage VLCD by externally connecting a diode D1 and a resistor R1 between +E and GND, and connect a capacitor C+.

By supplying the voltage to the booster circuit 27a (the part surrounded by the broken line) including C1, a double voltage (10E-V LCDI) of (+E-V LCD) is generated. VLCD and VLCD
Both I are VLCDO and VLCD2 respectively by analog switches and output control circuits made with PchFET.
be guided by.

V LCD0 and VLCD21! ,0FFVLCD condition B
The output changes accordingly. 0FFVLCD is “L01@
When , VLCDO=VLCD, VLCD2=VL
CD1, and when 0FFV LCD is "High", V LCD0 = V LCD2 = V DD.

Further, the voltage setting circuit ff127a obtains a clock from φ in FIG. 8 to switch the connection of the capacitors CI and C2 to boost the voltage. Further, FOR is a terminal for starting the booster circuit, and the booster circuit is started by the FOR output shown in FIG.

FIG. 26 is a time chart of the data latch section 22 of FIG. 7. Both external signals pwc and cs become "sov", and shift registers SRI to SR are activated at the falling edge of SCK.
7 data will be rewritten.

At the falling edge of the first 8th pulse of SCK, all the contents of SRI are rewritten, and from the 9th pulse onward, the contents of SRI are rewritten in order from shift registers SR2 to SR7 every 8 pulses.
, BS7 goes low at the rising edge of the 49th pulse immediately after SR6 is rewritten, and at the same time as the rewriting of SR7 begins, flip-flop FF3 reads the D input at the rising edge of φ, so FF3's ζ −Output is °
It does not change until it becomes ``Lov'' and BS7 becomes ``High'' again.

The L T CH pulse is created by the ζ output and the P-CS signal, and the contents of the SRI to SR7 norial renosters are
It will be taken into the latch of TI-LT7.

FIG. 25 is a time chart showing the overall general operation from after the battery is installed in the camera. Immediately after the battery is installed, the display circuit section 20 is initialized by the FOR signal. Signal VLC
DI becomes earth GND level, OF F V LC
D becomes "Higb'". Therefore, no voltage is applied to the liquid crystal. After that, xt and t of CPUto start oscillating, and CPU10 starts operating. After a while, the display circuit te20 starts oscillating [XL2], and the clock φ.

~φ1. starts to start. When the clock φ starts to operate, the data latch section 22 (starts to operate, and when the norial data comes from CPU10, it operates as shown in FIG. 26. When the clock φ starts operating, the voltage generating section shown in FIG. 24 27
operates, and the potential of the signal VLCDI stabilizes after a short period of time. After that, OF F V LC as necessary.
If D is set to "°Low", the liquid crystal drive voltage, VL, c
oo, VLCD2 is supplied to display sections 4 and 6.

28 to 35 and 37 to 39 show various display ideas of the external display section 4 and the internal display 116, and each figure a except for FIG. The figure shows the display on the internal display section 6.

Figures 28'a and b are AE displays in program mode, showing auto second time 1/250, auto aperture value 5.6, program PROGRAM, and decoy.

The mark ASI+ on the right end of Figure 28! This is the display of the photometry mode and shows average photometry.

Figures a and b of Kaya 29 show the AE display in aperture priority mode. 5.6 and auto second time of 1/250, and AE mode is indicated by A with aperture priority and 1/250.

Figures 30a and 30b are AE displays in the Tsuyabuta time priority mode. When the shutter speed setting mark is pressed, the set glossy seconds value is 1/250 and the auto aperture value is 56, and S and G, which give priority to the glossy seconds, represent the AE mode.

FIGS. 31a and 31b are AE displays in manual mode.

The setting mark for the glossy second time and aperture value indicates the set glossy second time value of 8 degrees and the set aperture value of 1.4, and the manual mode M and the figure represent the AE mode. The right end of the internal display is the partial metering mark for the metering mode, and the left side is the error amount of the manual setting value relative to the appropriate value, which is the so-called metered manual indication value, +6.5E.
The mark on the left end that indicates that there is a difference in V indication is a mark that indicates a camera shake (hand shake) warning, and the two marks are lit alternately.

FIGS. 32a and 32b are displays during override setting. The override direction and absolute measurement represent SgV.

FIGS. 33a and 33b show the AE mode display after override setting. Compared to FIG. 28, ten override directions have been added. The internal display also displays the absolute override amount of 1.5 EV. However, +1.5 is blinking on the internal display.

FIGS. 34a and 34b are ISO setting display.

The ISO mark and ISO value 100 are displayed.

However, the ISO mark does not light up on the internal display.

FIGS. 37a and 37b show hand shake (camera shake) warning displays. On the internal display section 6, mark CA on the leftmost camera
I and CA2 light up alternately to indicate movement.

FIG. 37C shows the display on the external display section 4.

FIG. 35 is a display in standby mode.

Only the bar display was dimmed, and all other lights were off. Functions other than camera display are in a stopped state.

Description of Operation> - Overall Operation - The basic operation of the display circuit section 20 will be explained. Electric I
When the DC voltage +E is supplied from the power-on reset circuit 40 (right side of FIG.
By the OR signal, the minute JIB's 7 lip 70 lip FFI (
4), the flip-flop FF2 of the clock generator of the segment driver section 24 (FIG. 6), the flip-flop FF3 of the data latch circuit 23. Latch L
TI (Figure 7), starting FET 27b of voltage generator 27
(FIG. 24) are each set to the initial state. Latch LT
In I, each data terminal is jl0="L ov'
.

jl 1 = “High”, flip-flop F
FI.

In FF2, set the output state to QB'Low' and Q = 'Hi'.
Set to gh'. In FF3, the output state is Q = “H”
igh'.

The voltage generator 27 sets the voltage to FE.
By momentarily turning on T27b, the capacitor Ct is charged, and the level of VLCDI becomes the GND level. In this state, since the crystal oscillation WXL2 of the oscillation unit 41 (Fig. 4) has not started oscillation, there is no circuit operation at all, and the oscillation rise of XL2 ( Waiting for the oscillation rise of =φ. One-way, external display w54.6 LCD display side has COM and 5EG 4 children connected to VDD and VLD.
2, V[DO is given in an indeterminate state, but (
COMI is VLCD2゜C0M2 is VLCDO, 5EG
n is VDD or V depending on the states of S2n and 52n-1.
LCD2) OFF inputted to voltage generator 27
VLCDh< j IO='Low', jl I=
By the initial setting of ``High'', AND gate A50° and inverter I50. 'High through or gate 050
h”, the switch circuit in Figure 24 sets V
LCD2 = V LCD0 = V DD, and the voltages applied to each terminal of the LCD display on the inner and outer mounting portions 4.6 are equal, and there is no DC voltage application state that is harmful to the liquid crystal.

Next, the crystal oscillator XL2 starts oscillating, and φ. When a clock enters the flip-flop FFI in the frequency dividing stage, all parts start operating at the same time.

The clock φ enters the flip-flop FF3 of the data latch section 22, and functions to generate an LTCH pulse when the norial data communication from the CPU10 starts.

The clock φ enters the booster circuit of the voltage generator 27, and C1
, Cr, the voltage boosting operation is performed by switching the capacitors.

Clock φ1. φ,. is a common driver [! E! 25 and segment driver section 24, and serves as a clock for the liquid crystal drive waveform.

Clock φ, 4 is the output controller f of the decoder section 23
It is used to manually control f1cTL+ and control the blinking of display contents.

The operation after the rise of oscillation of the crystal oscillator XL2 will be explained first with respect to the voltage generating section 27. The clock φ input to the booster circuit 27a in FIG. 24 starts the boosting operation, and the initial VLCD
What was the ILCD display level (V DD-2V
(LCD) level to avoid stabilization. From then on,
It continues to work without interruption until the power supply voltage drops and it stops operating, or the oscillation circuit stops, causing the lifting and lowering operation to stop. On the other hand, the data latch circuit 22, which has started operating due to the clock φ, outputs signals to the terminals jlO and jlI.
Low'.

The moment a signal other than "High" is input and latched, 1:0FFVLcD becomes "Lov"i: The analog switch on the right side of Fig. 24 switches, and VLCD2-
Wait for output of VLCDl, VLCDO=VLCD,
Coreraba, each common driver 25. The voltage is guided by the segment driver 24 and applied to the LCD display of the inner and outer display sections 4.6 as a voltage for driving the liquid crystal, and a liquid crystal display is performed based on the latched data.

Next, the data latch section 22 will be explained with reference to FIG. 26. This circuit starts operating when both the pwc and cs multiplied signals become low-. PW is, for example, a timing signal for supplying a 7rL source to a photometry circuit of a camera (not shown), and the photometry circuit starts operating when PWC=-Low-. Further, the signal is a signal that determines the other party for serial data communication, and one signal is output from the CPU 10 to each circuit in the camera (not shown). C
The partner for serial data communication is selected by S=“Lo view”.

When either PWC or CS is -High” 1.:I
The iP・C5 signal is “High”, the counter decoder CD is set, and all BSI to BS7 outputs are “High”.
Also, the output φ of the OR gate OR+
S is °High”, and the output L of nut gate NA8
TCH is also ``High''. When PWC-1d1- is ``Low'', the counter decoder CD becomes active, and OR+ and OR gate OR2 open, and the signals of SCK and BS7 become detectable. Become. S.C.
BSI goes “Low” at the rising edge when the first pulse of K is input.
", and the NOR gate NR3 opens. At the fall of the first pulse, the φλ force of the shift register SRI rises, so the shift register SRI takes in the contents of 5DATA at that time by 1. The data at this time is NO. 0 Next, the second pulse comes and the same operation is repeated.At the falling edge of the male 8 pulse,
8g of data is taken into the shift register SRI, and the eighth data is called jl7. Until this time, the signal BSI is "Low".

When the next 9th pulse rises, BSI becomes "High", BS2 becomes °L ov", and NOR gate NR3 closes.
Noah Gate NR4 opens. 5DAT at that time because the φ input of shift register SR2 rises at the fall of the 9th pulse.
Shift register SR2 takes in only one content of A.
The data at this time is j20. From then on, proceed in the same way and move on to the 4th
At the rising edge of the 9th pulse, BS6 becomes High-, and the BS
7 becomes Low°, Noah gate NR8 closes, and Noah gate NR9 opens. Furthermore, the output of OR gate 0112 becomes °L ov", and the contents of shift register SR7 are taken in from 370-j77 up to the 56th pulse, but from the 1st pulse up to the 56th pulse, LTCH
The output remains °High, and each shift register S
Data is latched from R and data is not taken into T.
Due to the OR gate OR2 opening at the 49th pulse, the output of OR2 becomes "Low", but due to the rise of the clock φ, the 7th lip flop VF3 becomes D.
The input “L ov” is taken in, and the ζ output is “High”.
However, before the C output changes, the other input of the NAND game 'pNA 8 becomes "Low", so the TCH output remains at High-.

At this point, the output of the OR gate OR2 becomes "High" depending on whether the 57th pulse comes or whether one of the 3- pins becomes "High" in p.
Since the output of flip-flop FF3, which is the other input of 8, is also ``High'', the NAND gate N A 8
The output LTCH of becomes °L ov'. This “High”
"→" The fall of L ov- is a latch signal, and the data temporarily stored in the not registers SR1 to SR7 is latched into the data memories of the latches LTI to LT7.

After that, with the rise of the clock φ, the 7-lip flop FF3 takes in the °old gh” of the D input, and the σ output becomes °L.
ow' and the counter decoder CD is pwc
, cs is set to "High", and each returns to the initial state of deafness.

The above is an overview of the operation of the data latch. Here, if the number of clock bytes for 7 real data communication is insufficient, the last latch pulse LTCH will not be output, so no data abnormality will occur, and if the number of clock bytes exceeds 5.
It is automatically turned off at the 7th pulse, and naturally no abnormality occurs.

Furthermore, since the clock within the same byte is processed so as not to be interrupted on the sending CPU side, abnormalities in data communication are completely prevented.

On the other hand, even if the external signals ΣTσ, CS, SCK, and 5DATA operate normally, if the internal φ is not operating, the LT
CH pulse is no longer output and not register SR1~51
The data taken into LTI-LT7 cannot be latched into LTI-LT7 again. This means that when φ is not operating, the liquid crystal driving wave Jl is also not operating, and a DC voltage is applied to the liquid crystal. Therefore, at that time, N O = “Low-, j l l = “l(
igh” is the only thing that holds the TE OF F V LCD= “II
It must be set to igh- so that no voltage is applied to the liquid crystal. For this reason, external data is not taken in when the clock φ is not operating.

Next, the common driver section 25 and the segment driver section 2
I will explain about 4.

In Figures 5, 6, and 27, Nant Gate N
A1. NA2. Noah gate N111.8112, inverter IN3. Analog switch ASI-AS4゜Peh FET F by gate 7 circuit consisting of I84
r'1. Controls each switch of FP2. The input signal of the gate circuit is φ1. φ,. With this timing, C0M2. The COMI outputs each change as shown in FIG. Signals C0M2 and COMI are connected to clock φ7. The period is the same as that of , and there is a shift of 1/4R period from each other.

The output values are vDD and V LCD0 and V LCD2)
It has three levels.

In FIG. 6, four types of clocks generated by the clock φ processed by the clock generator composed of the inverter INS and the flip-flop FF2 and the clock φ111 are selected by the clock selector composed of the Nant gates NA3 to NA7. The condition for selecting 0 is S2n
, 52n-1, and by this condition, 5
The output waveform of EGn is determined.

This situation is shown in FIG. 27, and there are four different states determined by S2n and 52n-1.
The period is the same as that of the clock φ1°, and there is a difference of 174 periods from each other. The output values are VDD and V
It has two LCD levels. Signal C0M1.
The potential difference between 2 and segment signal 5EGn is 2XVLC.
The LCD display lights up depending on the waveform of the portion that becomes D2.

5EGn (LH), 5EGn (H
H) voltage is applied, the CD display segment lights up, and 5EGn (HL), 5E for C0M2.
The segment of the LCD display to which the voltage of Gn (Hl() is applied lights up. 5EGn (LL) is CO
The segments will no longer light up for MI and C0M2.

In other words, the 52n-l signal is a signal that controls lighting of the segment for COMI, and 52n-1="L, o
When 52n='Low', it is OFF, and when S2='High', it is ON.The S2n signal is a signal that controls the lighting of the segment for C0M2, and when 52n='Low', it is OFF, and when 52n=' When it is High', it is ON.

Data latched in Figure 7 j■0~j17°j20~
j27. j30- j37. j40～j47゜J50～
j57゜】60~j671.70~j77 is j17. j
30. Except for the 3 bits of j31, all the bits are manually input to the decoder section shown in FIG. SWI.

SW2, DCI to DC4, and 501 to SD6 are simply gate circuits and have no timing relationship at all.

The explanation is below.

First, the contents of Norial data will be explained.

jlo and jll are signals that control the supply of liquid crystal drive voltage, N O = "Low", jl = "High"
The liquid crystal drive voltage stops only when bo, and the voltage applied to e and the product becomes 0.

02 to j+6 are data signals regarding the aperture value of the camera (see Figures 9, 14, 15, and 20);
There are three types. Moreover, when all of j12 to j16 are "High", nothing is displayed.

J20 is a signal related to a warning of insufficient battery voltage in the camera (see Figure 22), and j20="High"
All the displays displayed at the time are φl.

Repeats blinking at a period determined by .

j21 is a hand shake (camera shake) warning signal (Fig. 23, 11
! ! When the speed becomes slower than the limit that causes camera shake (camera shake).

becomes High'. At this time, the camera shake mark CA1 on the internal display IE6 in the viewfinder. CA2 lights up alternately.

”22 to j27 are data signals (
(see Figures 9, 13, 17, and 18),
There are 36 types of Keyaki. Also, ノ22~''27 are all °II
No display appears when the display is “high”.

j32 to j37 are data signals regarding the ISO value of film sensitivity (Figs. 9, 13, and 17).

(See Figure 18), and there are 3 types. Also, J32~j
When all 37 are "High", no display appears.

j40 to j47 are data signals (
(see Figures 9, 13, 17, and 18),
100 from 0 to 99! There is type i.

Also, when all of j40 to j47 are "High", no display appears.

35G to j53 are data signals regarding the override value and the deviation amount of the metered manual (UE11, Figure 12, Figure 19.20 (see V4)), and depending on the content to be displayed, the override value 9q and the metered manual are displayed. 14 different values of the deviation ヱ are switched and sent from the CPU. When all of j50 to 353 are "High", nothing is displayed.For switching the display contents, please refer to j5.
5. The receiver has the j56 signal (described later).

354 to 356 are 5IGN signals (see Figures 21, 22, and 23) related to the override value, the sign of the metered manual deviation amount, and signal switching, and j54 is "+" and " −” Signal related to the sign,
355 and 56 are signals for switching data between the override value and the metered manual deviation amount for each external display and internal display.

j57 is a signal used to temporarily display a so-called preview (see Figures 22 and 23), which is used to check the change in depth of field by narrowing down the lens aperture before shooting. At one point, this signal becomes ``high'', the aperture mark F on the external display section 4 blinks, and the set number chain belt indication mark TAI.

Performs lighting control for version b of TA2.

j60 is the +50 display priority signal l5OPR+. This means that main switch SM is OFF and 0FFVLC
Is the D signal High'i? J5, even if the liquid crystal drive voltage is stopped, when this signal becomes High-, the liquid crystal drive voltage changes to the segment driver 24. Common driver 2
0FFV LCD signal as supplied to 5°Lo
v” I: Yes, (see Figure 1!21 p@) This signal is not used alone; at the same time as this signal, the ISO!IE display mode and ISO value data are sent from the CPU 10. This is the camera's In terms of operation, this is the state immediately after the battery is installed.

】61 is a blinking signal of the deviation amount of the metered manual M'dMOVER (see Fig. 22), and this signal is "Hi".
gh”, the deviation value of the metered manual flashes.

j62 is a knot signal SH+ for flashing the program mode mark during the shift of the camera's program mode.
FT (i22 Fig. 18), and this mark flashes when j62 is set to "°High". Here, shift means changing the combination of aperture value and glossy seconds value in program mode. Refers to the state in which it is operated.

Incidentally, all AE modes can be blinked as needed, regardless of the program mode.

+63 is the control interlocked warning signal Not, C0NT (22nd
(see figure), and this signal goes “High” when an undesirable exposure value that exceeds the aperture value and second value that the camera can control is required.
h”, and the aperture value and/or second value flashes on the calculation control value side depending on the AE mode to issue a warning.

+64 is the out-of-brightness interlock warning signal BV (see Figure 22), and when the brightness value exceeds the brightness value that can be measured by the camera, this signal becomes ``High'', and the ASI and AS2 during the metering mode display. flashes to warn you.

+65 is the bulb time signal BULB (see Figure 21), which is a "High" signal that causes the camera to switch the 4-digit, 7-segment display content from the flashing seconds display (QuLb) to the bulb exposure seconds count display during bulb exposure. The valve count will be displayed and the contents of j40 to j47 will be displayed.

Noro 6 is the all gate light signal ALL OFF (Cho 21 figure sanuta), and all the waveforms of the driving SEG Zuiko are opFI! This is a signal that controls the temperature to become cedar (see Fig. 27, 5EGn (LL)), and when the temperature is 0 °C, all the signals are OFF. however,
Camera mark CA1. CA2 cannot be controlled.

Noro 7 is the all-on signal ALLON (see Figure 21), which turns all the waveforms of the 5EGia elements for driving into ON waveforms (second
7 Figure 5EGn (HH) # is a signal that is controlled so that the display becomes ``High'' and all are displayed as ON.

However, camera marks CAl and CA2 cannot be controlled.

+70.371 is the camera operation mode signal CALL M
ODE (see Figures 19, 20, and 21),
Normal AE mode, 5TANDBY mode in which the camera is not operating even if the main switch SM is ON, 150 mode for 150 settings and display, +/- for general settings and display
There are four modes, and the display contents are changed according to each mode. (See Figures 28 to 35) +72
．． +73 is the camera's AE mode signal AEMODE (see Figures 22 and 23), which has four states: program mode, aperture priority mode, shutter speed priority mode, and manual setting mode. Switch the displayed content.

Core 4 outputs ISO when prompting to set ISO value.
This is the warning signal ISOARM (see Figure 21), and when this signal goes high, I
The SO mark and ISO value flash.

+75 is the mode off signal MODE OFF (see Figure 23), and when this signal becomes "High", the AE momo display that is being displayed goes off. OFF
Make it.

+76, +771; Lll optical mode switching signal AYE
/5l) OT (see Figure 23), and when the partial side light mode is selected among the two light metering modes, the average metering mode and the partial metering mode (either 376 or 377 or one is LO ) AS on the internal display section 6 of the viewfinder
Turn on 2. ASII! It is always lit during AE mode.

DC4 also uses the external signal SM and Tτ as data, and is connected to the data code conversion section (Fig. 23) and the L of the display section 4.6 for displaying other than the number of positions such as the time value and aperture value.
A decoding unit for controlling blinking of each display segment of the CD display (Fig. 22) and two signal switching units SW1. S
It is divided into three parts: a decoding section (FIG. 21) related to W2.

FIG. 21 is created mainly with switching signals of SWI and SW2, and includes FOM, CTrt, +50. SS signal is SW
I, MON, +/-ON signals control SW2. In addition, the ON and OFF signals are commands to control the CTLI and display an ON display and an OFF display for all segments. Furthermore, the 0FFVI and CD signals function to cut off the liquid crystal drive power supply and the liquid crystal drive circuit when this signal is "High". The purpose of this is to display the liquid crystal 1. : Prevention of applied DC voltage and reduction of power consumption when the main switch SM of the camera is turned off. On the other hand, the CALL MODE signal j70. j'7 I
represents four camera operation modes, j70 and j71
--When it is "High", it is called the AE mode for normal shooting. When it is j70-・J71="old gh", it is called IsO mode for +50 sensitivity setting.Noah 0・j711"It
When it is igh-, the camera timing state STΔND[3Y mode is called. When j70 and j7+ = ``High'', it is called +/- mode for override setting.

To explain the signals for SW1 and SWZ in accordance with the above four modes (see Figure 21), during the AE mode, V
W becomes “Lov” (camera starts operating.

), the FON signal becomes “High” and SWI
Power function, aperture t) value tet information j12 to j16 are selected,
Decoded and displayed. pwc- becomes “High” (
The camera goes into standby mode. ] and FON
The signal becomes "°L ov", and the aperture value information is erased by SWI.

On the other hand, when VW is "Lov" and 365 is low (normal time), the SS signal becomes "High" and one of the glossy seconds information No. 22 to No. 27 is selected and displayed in a decoded manner. At this time, the other CTn signals and tsol;? are -L
ow", and the timer count information and 150 value information are erased by SWI.

When PWC is l, ow" and j65 becomes °High" (during valve count), the CTIt signal becomes °lligh.
", and timer count information 340 to j47 are selected and decoded and displayed. At this time, Ike no. 5Sli, I
The sO signal is “Low” and the tweeter seconds information and 1
50 value information is erased by SWI.

Also, the +/-ON signal is °L ov", but the MON signal pw is Low", and j50 or j56 deke is 'Hi'.
If it is "gh", it is "High", so the value information of the metered manual deviation amount is selected and decoded and displayed by SW2, but the value information of the override is erased.

During 150% mode, SS, CTR, FON, MON.

↓/-ON signals are all "Low", only the ISO signal becomes "High", SW1 is activated, and ISO value information 332 to j37 are selected and decoded and displayed. At this time, the pond numerical band is erased.

5 During TANDBY mode, SS, CTR, FON, I
The SO, MON, +/-ON signals are all "L ov", and all numerical bands are erased.

During +/- mode, SS, ISO, CTR, FON, M
All ON signals become “Low” and pwc becomes “Low”.
”, the +/-ON signal becomes °High'.

At this time, override information %jj50 to j53 are selected and decoded and displayed.

Figure 22 shows the creation of one control word for the blinking display of each display segment, and when the outputs 81-88 become ")(high", the corresponding segment (see Table 1) lights up. The Baso segment flashes.

The B8 signal is a signal that causes the F mark on the external display ff14 to blink, and is mainly controlled by the j57 data.

The B7 signal is the 7th segment of the LCD of the internal display section 6.
This is a signal that flashes the numbers 8 and 8 and the second digit of c012 between them, mainly j55. j56. It is controlled by the data of j61.

The B6 signal is a signal that causes AS+ and AS2 of the internal display section 6 to blink, and is mainly made up of 364 data for $111.

The B5 signal is a signal that causes numbers 5 and 6 of the 7 segments, cal, and l to blink on both the external and internal display sections 4 and 6, and is mainly controlled by the Colo 3 data.

The B4 signal is a signal that flashes numbers 1 to 4 of 7 segments for both external and internal display ff14.6, and is mainly 363, j7.
It is controlled by the data of 4.

The B3 signal is a signal that causes both the external and internal display sections 4.6 to flash, and is mainly controlled by 362 data.

The B2 signal is a signal that causes the ISO mark on the external display section 4 to blink and is mainly controlled by 374 data.

The Bl signal has no fixed data signal that can prevent all segments except CAI and CA2 from blinking among the segments other than the segments 88 to B2. However, the blinking control from 82 to B8 including [31] is performed by the j20 data.

FIG. 23 shows a decoder for seven segments for displaying numbers in the inner/outer representation part 4.6, except for 1 to 8 and cal, l, cal, and 2. Norial data j54-j57. j70-j73. j75-j77, j
21. The output is controlled by signals q40, external signal PW, and decoding DC2 output signal, and the outputs range from "51 to r69", and when each output becomes "High", each corresponding segment lights up.

FIG. 9 shows SWI, which selects signals.

The input signal is the calibration value of j12~month 6, j22~
Glossy second time value of j27, ISO value of 532 to j37,
These are the timer count values of j40 to j47, and when the 0 selection signal with the FON signal, CTR signal, rso signal, and SS signal that selects each is 'Higb', the NAND gate opens, and output data p = input data j. On the other hand, when 'Lo ma°', the NAND gate closes and the output data p
= “High”.

(Example) When FON=“High” Outputs p12 to p16 transmit inputs j12 to j16 as they are.

When FON=-Low”, outputs p+2 to p16 are all °
becomes “High”.

Next, although there are no detailed diagrams, DCI will be explained.

DCI is Norial data j2 processed by SWI
2-J27. j32~j37, j40~j47
++22 to p27. p32-p37, p40
This is a data converter (decoder) that inputs ~p47 and outputs Ql-439 data corresponding to the 7-segment 4-digit part. Figure 17.

Figure 18 is for explaining the concept of DCI,
The human power data corresponds to p22 to p27 with 36 types of glossy seconds (SS values) (buLb -1/4000) and A
LLHigh, ISOSS value 1 (IS06 to l506400) corresponding to p32 to p37 and ALLHigh,
There are 100 types of timer count values (CTR values) (0° to 99°) corresponding to p40 to p47 and ALLHigh.

For example, data p27~ corresponding to rbuLbJ of ssm
When p22="LLLLLL" is input (other data P32 to p37.p40 to p47 at that time are ALLHigh)
It is processed using DC4 and SWI so that it becomes h. ) Output data is q7 data “bo” for segment decoder SDI, QI8 data “Lo, S
For C2, q29 data is 1u0, and for SC4, Q39 data is "b9."

In addition, data p37 to p corresponding to r200J of 150 value
32 = “LHHHLL” is manually input, other data at that time I) 22-p27. p40-p47 are ALLHigh
It is processed using DC4 and SWI so that it becomes h. ) Output data is Ql data for segment decoder SDI, q8 data for SC2, and Q for SC2.
21 data, and data for SC4 is not output.

Also, p22-p27, p32-p37. p4
When all of p0 to p47 are 'High', no output is output to the segment decoders SDI to SD4.

All segments for 5DI-SC4 are turned off.

It is composed of a gate circuit having the above configuration.

Next, the C segment decoders SDI to SD4 shown in FIG.
I will explain about it. The data signals q1 to q39 obtained in the previous section are respectively q1 to q7 to SDI and q8 to q18 to SC.
2, q19 to q29 to SC2, Q30 to q39 to S
Enter it in D-mail. The internals of SD1 to SD4 are basically the same, but among the 14 inputs, terminals to which no corresponding data signals are input are pulled up to the +- source side in each block. The input of this circuit is configured so that a forward-moving output can be obtained when it becomes 'Low'.For example, SD
When the q7 data signal (b of buLb) is output to I,
The input will be “L ov”, and at this time, the inputs that have been pulled up manually by other SDIs will be “lli”.
Outputs (c), (d), (e), (r), (g) related to the line that is “gh” but becomes “shiOv”
are all °High” and the ponds (a), (b), (
h) The line is “Low”. This output (c),
(d), (e), (f), and (g) correspond to SDI terminals r3 to r7, which are the next-stage CTLI terminals.
This led to human power and LCD displays. This r output corresponds to the liquid crystal segment and the ratio 1 to 1 (see FIGS. 16a, 2, c, and Table 2). The output here (c
), (d), (e), (D.

(g) each corresponds to the numerical segment name of the 7-segment note, and represents the letter ``6J'' (see Figure 2).

Furthermore, for example, q21 data signal (r2
When J) appears, ■Manpower is °Lo Shirakonari (a).

(1+), (d), (e), (g) Force High
” Then the character “2” will be displayed.

p12 to p16 obtained by SWI enter the decoder DC2 shown in FIG. 14. When pI6 to p12="LLLLL", the output is Q40, and a "Low" output is output.

The output of q40 goes to segment decoder SD5 while it goes to decoder DC4.

Other outputs are exclusively connected to SC2.

The contents of the outputs of q4Q to q62 based on the data of p12 to p16 include 1123 types of apertures shown in the concept of SC2 shown in FIGS. 19 and 20. These are shown in Figure 15 with SD5
A segment decoder is performed on a part of (the input part of q40 to q62), and outputs of ``30 to ``43 are obtained.

For data j50 to j53, decoder D in FIG.
There is C3. j50 data is decimal data,
A p1 output and a p2 output are obtained.

j51=j53 data represents the information of O to 6, and its output is p3 to p9, and the output is in the active state at "High". This output is input to the switch SW2 in FIG. 12, and the selection information MON, The output light is switched by +/ON.When MON is "High", +/-ON is "ShiOIt", and the outputs of l)2 to I)9 are inverted and output to 482 to q89. However, Q71-Q78 become "High". -Sumo wrestler/-ONh<'High
”, MON is “Low” and the output of p1 to p7 or the inverted form is output to q71-177, but the output of q82 to p7 is
All q89s are "High" (1). Moreover, q78 is °Low-. MON.

When both +/-ON are "off", all outputs of Q71-478°q82-q89 become "High".

The output of SW2 is q71-Q78 to SC2, q82 to q
89 is output to SC2.

q71 to q78. output by SW2. The contents of q82 to QB9 are shown in Figures 19 and 20. q71 to Q78 are the override value 7F1 and 1 decimal point, and q82
~q89 is the number of integer digits for metered manual values (including override values)! ! It corresponds to 7 poles and decimal display II.

Although the contents of SC2 are not shown, the basic idea is the same as that of SDI to SD4 in FIG. 13, and is shown in FIG.

The gate configuration is such that there is a relationship between the data shown in FIG. 20 and the output display example.

Finally, r made by 5DI-5D6 and DC4
l-r69 and Bl-B8. When ON and OFF signals and φ and 4 clocks are input, the output control section CT
LI will be explained.

The internal configuration of CTLI is already shown in FIG.

r69-969. Except for the configuration of the portion 570, the configuration is basically as shown in FIG. 16a. First, in Figure 16, when the °High- signal is input to r69, S69 and 5
The gate for 70 is opened and by the clock of φI6, "
lligh'', ``Lo meeting is repeated, but S69 and 5
70 is output for reverse use. In this way, the corresponding CA1.
The CA2 mark lights up alternately, giving the impression that the camera mark is blurring. Regarding circuits for signals other than r69, logical expressions and truth tables showing the relationship between the output S and the human power r are shown in Table 1.

As shown in this table, when the δma signal reaches "L ov", all outputs S except S69 and S70 become "High" and the display contents become CA1. All lights except CA2.

Next, when the ON signal is “High”, the OFF signal is “High”.
When the 1-th gh" is reached, all outputs S except S69 and S70 become °Low", and CA1. All displays except CA2 go out.

Signal edge l-1ight” at σ, OF signal is °L
ov", Bs (B l~l38) is °Low"
When this happens, the output becomes S-, and the display is lit in accordance with the display information given by the Norial data.

ON signal is “High”, OFF signal is high
-, Ba (Bl-88) becomes °High" by DC4, depending on the combination of B and r under the truth table in Table 1, if any part of " The output S corresponding to φ1 blinks according to the display content at that time in response to the clock of φ1.

For example, the B6 signal is “High” and the other 81 to B5
．． B7. When the B8 signal is “Low-”, the corresponding outputs S59 and S of R59 and “60” in the B6 signal group are
60 repeats °High', "Lov".

However, if the states of S59 and r60 are "Lov", S59 and 560 cannot become High. Therefore, As2 and AS corresponding to S59 and 560
If + is lit, it will change to flashing.

The outputs 5l-570 obtained by the above CTLI are input to each segment driver (Fig. 6), and output as the liquid crystal drive waveform (Fig. 27 1) to the final output SEG terminal (SEGI-SEG35). .

The relationship between the CTLI output S and the SEG terminal is shown in Table 2.

The names of the segments shown in this table are the same as the names of all the segment diagrams shown in FIG. 2C.

When the camera is started - When the camera is started by turning on the main switch SM, an interrupt is generated in CPU+O, the CPU10 is released from the stop state, and the internal r(OM) starts operating according to the program. Then, voltage is supplied to a photometric circuit (not shown), but it takes several tens of seconds for the photometric circuit to operate reliably and provide the necessary data to the CPU10.
time is required.

However, the CPU 10, which operates at high speed, has communicated seven real data with the display circuit section one or more times at this point. The contents of the noreal data communication (36th diagram) mainly include exposure information such as glossy seconds and aperture value, but when the photometering circuit etc. is not operating normally, these exposure 44%i Accurate values cannot be obtained. Therefore, it is not a good idea to perform norial data communication in this situation because it not only makes no sense but also causes erroneous display. Therefore, at startup, until the CPU10 takes in accurate information and completes the calculation, a troublesome inaccurate value is displayed on the display by sending data to turn off the lights or data for standby display. You can make things go away. The display section of the embodiment has a structure in which the previous display is maintained unless new norial data is communicated. There is no particular problem as long as no real data is exchanged until the calculation is completed using this, but since the program 70- is created in such a way that the CPU10 program does not generate special cases as much as possible, serial The method of performing data exchange 1t is better in the sense that it does not increase the capacity of the ROM for programming. Therefore, the above method becomes better.

Immediately after the battery is installed in the camera, +E voltage is applied to the CPU 10 and the display circuit section 20, and each starts operating. Each circuit has separate crystal oscillators XLI and XL2.
, and starts operating independently, but in this case, XLI
Generally speaking, XL has a higher frequency than XL2.
+ starts oscillating early. After oscillation starts, CPLIIO starts operating according to the program in the internal ROM, but since there is little work to be done immediately after battery installation, it takes several tens of asec.
Due to the incident, he became deaf and stopped functioning, and was waiting for him to wake up again. Generally, at this point,
L2 oscillation rise (generally 1001 sec to I se
c) is not guaranteed. When XL2 of the display section is not oscillating, communication of 7 real data with CPU10 is not received, and the clock φ shown in FIG. 7 is not generated, so the time chart shown in FIG. It does not operate and no LTCH pulse is generated. Further, even if XL2 is oscillating, the data in the display circuit section 20 is not rewritten unless there is communication of norial data. (F in Figure 7
BS7 because -, σS, 5DATA, and SCK do not come in W
does not occur, and no LTCH pulse occurs. ), the operation of the CPU 10 as described above is not good because the display content continues to be displayed indefinitely immediately after the battery is installed. Therefore, in Figure 7 of this circuit, IO reset, jll set, Figure 24, 2
As shown in Figure 5, the power-on reset circuit provides 1! for LCD driving. One countermeasure is to prevent the initial indefinite display by turning off the power source. Furthermore, if the power-on reset circuit does not work for some reason, or if it is not good for the display to remain off, continue serial data communication from CPU10 until the guaranteed time for the XL2 oscillation to rise after the battery is installed. As soon as the oscillation of XL2 starts, normal operation starts and the display contents change immediately. The contents of the serial data at this time may be data for turning off the light, data for displaying standby, or any other data.

Therefore, the CPU operates by performing serial data communication using display data from the time it performs necessary processing immediately after the battery is installed until the guaranteed start-up time of the XL2 oscillation, and after a predetermined period of time, if necessary. It is in a stopped state! ! ! All you have to do is stop the performance. However, the CPU 1O must prohibit interrupt operations during the guaranteed rise time of the XL2 oscillation.

- Before CPUIO stops - Immediately before cpu+o stops operating, CPU10 sends standby mode display data to the display. After that, until the CPU+O is activated again, there is no data transfer, so the display remains unchanged and the standby mode display continues. Immediately before the main switch SM is turned off and the CPU10 stops operating, CPU10 sends the display data for the light-off mode to the display in the same manner as described above. After that, there is no data transfer until the main switch SM is turned on again, so the display remains unchanged and remains off.

-ALLON and ALLOFF- Norial data jlO and jlI are the most prioritized data that completely cut off the LCD 1ji.

The light turns off when r'djll='High'.

On the other hand, data j6671 and j67 are prepared for connection checking and are second priority data. j
When j67="High", a waveform in which all segments are lit, and when j66="Lov", a waveform in which all segments are extinguished are output from the COM and SEG terminals, respectively.

When each waveform is applied to a normally connected LCD,
The display will show whether all lights are on or all lights are off. However, if the connection with the LCD is misaligned, a part of the LCD may turn off or turn on, or the brightness may be different from other segments, making it obvious that the connection is abnormal. .

Also, as a method of providing signals for serial data communication, 5DA
Pass the TA line through a small resistor to 10E (by connecting it, that is, pulling it up, all serial data becomes "High" information and is a priority bit) 67 comes alive and enters full lighting mode.Meanwhile, By connecting it to GND, in other words, if you pull it down, all serial data will be erased.W° information, priority bit, j66 will be activated and all lights will be turned off.This is a check that can be done even after the camera is assembled, and is extremely important. This is an easy way to check.

Furthermore, there is no need to provide a dedicated terminal, which is ideal.

- Off mode and standby mode - Fig. 35 shows the display on the external display section 4 in standby mode. Only the bar is lit and all other external and internal displays are turned off. As the camera body, the CPU
l0 is in a stopped state and is waiting for an input corresponding to an interrupt instruction. In addition, although power is supplied to the display circuit 20, no power is supplied to any circuits other than cr'u+o (not shown). The pond's circuits begin to function and function as a camera.

On the other hand, the display in the lights-out mode turns off all displays.

The method is to turn off the LCD drive power by 0FFV LC.
D is set to ``°High''.The camera body at this time only operates in the stop E state where cr'u+o is waiting for the input interrupt from the 5M terminal, and all other circuits except the display circuit (not shown) are in operation. Power is not supplied to the

The problem with cameras in standby mode and lights-out mode is that only the main switch SM is active in lights-out mode. On the other hand, in standby mode, other operation start switches such as a photometry switch (not shown) come into play. In addition, the current consumption is lower in the lights-off mode, which saves energy, and the voltage applied to the liquid crystal is zero in the 11-light mode, so the storage life of the liquid crystal is also good.

- Manually configurable data indication marks - Figure 29 a, b
In the A mode, since the aperture can be set, the mark 4TA2 on the aperture value side is lit, and the mark 4TA2 on the shutter speed side, which cannot be set, is turned off.

Similarly, in the S mode (shutter priority mode) shown in Figures 30a and b, since the glossy second time can be set, the gray mark TAI on the shutter speed side is lit, and the gray mark TAI on the aperture value side, which cannot be set, is lit. Mark TA2 goes out.

In FIGS. 31a and 31b, in manual (M) mode, since both numerical values can be set, both black marks TA1. TA2
lights up to indicate that both can be set.

In the P mode shown in FIG. 28, there are no numerical values that can be set, so both marks and tJ are turned off to clearly indicate their meaning.

Please note that these marks can be turned on or off using j72. Control is performed using the AE mote information provided by j73 as is.

However, if a function (not shown) for determining the presence or absence of a lens determines that there is no lens, the aperture of the lens cannot be set. Therefore, in this case, the setting mark TA2 regarding the aperture is specially set so that it does not light up regardless of the mode. This is controlled by the q40 signal shown in FIG.

1-Open Fla display - The aperture value display is a 7-segment numerical display as shown in FIGS. 28 to 31. The contents of the aperture value are shown in FIG. Here rq40. The l signal indicates a state equivalent to no lens when it is displayed as -1. rq43J to rq62J is 0.5E
This is the aperture value rounded to each V. On the other hand, the lens' open F-number values are 35 and 45 Kasa, which have been popular for a long time. However, since these values are not multiplied by the aperture value for each 0.5 EV, these values are treated as special and used as the rQ41J and rq42J signals. In this case, if the result of the calculation by CPUl0 or the set aperture value is the aperture value (judgment is made by an unillustrated aperture signal), and furthermore, it is 35 or 4.5 in this embodiment, etc. is the normal display 3
．． 3.5 or 4.5 instead of 4 or 4.8 mag.
A display signal is given from CPU+o so as to display the following. Further, when the result of the calculation performed by the CPU 10 or the set aperture value is not the aperture value, the normal display such as 3.4 or 4°8 is used for display.

The display form of the above two series was changed to H.

As an example, FIGS. 33a and 33b show display examples of the open F value.

The determination of open FM is performed, for example, as follows.

As shown in FIG. 40, in step Sl, the control CPU l0
reads the aperture F value Avn from the lens 3 and stores it in the internal renostar. On the other hand, in CPU10, eig is
Avo in step S3 using the calculated II calculation FiLAv.
= Av is determined, and if Avo = AV, open F value Avo
Step S4), if Avo≠Av, round the $ calculation FQI%Av to every 0.5EV and take it out Step S5), determine the data (AvDSP) of 02 to j16, and output the extracted output. The information is displayed on display sections 4 and 6 (step 56).

-Display of override index and metered manual- The +65 in Figure 31 is the deviation of 1 for the metered manual, and it is always lit during the manual mode, which is the only internal display of the Inno Finder. The displayed range is +6.5~
-6.5EV (see PA in Figure 20), and when it exceeds 1, +65 and -65 are displayed in a decaying manner. The data at the time of annihilation is ノθ1DAY9 ノM'dM OV E
R is set to "High".

Also, J-15 in Figure 33 is override 1,
It always appears depending on the settings when using AE mode other than manual mode. Similarly, this is only the internal display of the InnoFinder.

Display range is +40 to -4.0EV (see Figure 20)
, and cannot be set beyond that amount. Here, the override display is constantly flashing to distinguish it from the metered manual, and at the same time draws attention to the override setting.

In the external display, +/- symbol (01'1) is displayed when overriding.
．． OR-, 0R5) lights up, but in metered manual mode the +/- symbol (OR+, OR-) lights up.

0RS) is turned off and not displayed.

In order to receive and receive data on each quantity of override and metered manual using the same Renostar,
A separate identification signal is required.

This signal is provided by the 5IGN signal of the data 54 to 56.

Table 3 shows the relationship between the data contents of 54 to 56 and their output display states. This is to make the 4° portions of the backs j54 to j56 of FIGS. 21 to 23 easier to understand.

-8 and A mode display- Display #3 is shown in Figures 29 and 30.

FIG. 29 shows the display in A mode, and the Δ mode display section with an arrow pointing toward the display of the manually settable aperture value is lit. Figure 30 shows the display in S mode,
Light up the S mode display section with an arrow pointing toward the manually settable glossy seconds value display. By doing this, the color of the mode display and the meaning of the numerical value can be understood at a glance, making the mode display very easy to use.

FIGS. 38a and 38b show the display contents at the time of initial loading after mounting the film. During initial film loading, the film is fed at the glossy speed of I/4001.
It is controlled by the minimum aperture value (here F22). At that time, all exposure mode displays have disappeared, but this is]
The mode display is turned off by setting 75 bits to ``High''.

Figures 39a and 39b show the display contents when the lens is not attached. When the CPU10 detects that there is no lens by a mechanism not shown, it sets all display j12 to j16 to "L ov". This is done in step S+8 of the flowchart of FIG. 41, and the display decoder receives this. outputs the 440 signal in Figure 20 and turns 62 to L in Figure 23.
Make it ov'. Therefore, the display is displayed as the aperture value.
1 is displayed, and the aperture value open mark TA of the settable mark is displayed.
2 disappears.

FIG. 42 shows another embodiment for displaying camera shake on the internal display section 6. In this case, as shown in (a) in the figure, it is composed of three segments, and the type of camera is indicated by lighting two of these segments. This 2
There are two types of segment selection, (1) and (e), and upstream camera shake is displayed by lighting these two types alternately.

FIG. 41 shows an outline of the operation of the control CPU+o.

By installing the battery, CPLIIO starts creating from a reset start (step So). At the same time, a voltage is applied to the display circuit. First, in cputo.

Perform the initial settings of the camera (Step S!0)
Then, display data, turn-off data, standby data, +50 data, etc. are sent to the display circuit (step 511). (n is a value determined depending on the time it takes for the display circuit to guarantee normal operation) When the sending is finished, the switch group (not shown) is allowed to input (step 512).
. If there is nothing, the internal operation clock is stopped and the system enters a stopped state (step 5I3). Among the switch groups not shown, the photometric switch SL or the initial load switch SB has a relationship with the main switch SM as shown in FIG. 44, and has the same configuration as the other switch groups SL and SB. . Main switch SMh (SL when OFF, 58 manual power is pulled down and SL.

513 people are dead. In this state, only the SM signal generates the INTse signal that generates an interrupt. Main switch SM is turned on! When the N T seL signal is generated, an INT flip-flop (not shown) is set, and the CPU 10 enters an interrupt operation I NT (step 514). The INT7 lip-flop is set so that it can be set at the rising edge, and when interrupts are enabled (step 512), the INT flip-flop is set and waits for another interrupt to occur.

Now, when entering l NT (step 514), check the switch SB that detects the initial load state (step 515), and if it is 0FF (not in the initial state), supply the i source to a photometry circuit (not shown), etc. (step 516). Start metering. After that, in step S+7, AE
The calculation is performed, and the display data necessary for the display circuit is sent out in step S18. Thereafter, the main switch SM is checked in step 519, and if it is OFF, data for turning off the light is sent as display DATA in step S20, the r4 source supply is stopped, and the fpI destination is stopped in step S21. After that, step S12. Proceed to S13.

Step 51 again? If main switch SMh<ONL, check switch Sl (step 526) L, O
If it is FF, data for standby display is sent as display DATA, step 516. S21. S12.
Proceed to S13. Also, if it is ON in step 526, check S2 of the release switch in step S22. If it is ON, exposure control (step 523) is performed and the process proceeds to step S17, but if it is OFF and A1, the process proceeds to step S17 without doing anything and the operation is performed again.

On the other hand, if the switch S[3 for detecting the initial load state is ON in step S15, the second value and aperture value for initial load and MODE OFF information 5 data = "High" are sent out in step S24. And the second value and aperture value are 7! IJI
performs an initial load to control (step 525
). Thereafter, in step S15, the switch SB is checked again by 4°, and depending on the state of the switch SH, the photometry starts in step S+6.

The increase in time from step S13 to S14 depends on the switches SM, SL, and 5B, as shown in FIG. It's dead as a signal.However,
Only when SM(1) is ON, the INT seL signal is generated to enter the interrupt (INT) operation. Also, SM is ON
When , the SL and SB switches come alive and the INTset signal is generated by SL or SR, causing an interrupt (INT).
Get into action.

Although the SB switch is not shown, it turns ON when it detects the presence of 4 films and the back lid is closed, and turns OFF when the film counter (not shown) reaches 1. Become.

FIG. 43 is a flowchart showing the operation for detecting camera shake. In step S31, the CPU 10 reads necessary information such as focal length from the lens. Then, in step S32, a TV value for reshooter control is calculated by exposure calculation, and a TVL value of the camera shake warning limit is calculated from the lens (1 signal. Then, in step S33, the TV value for camera shake warning limit is calculated from
Compare the size of and TVL, and if TV<TVL, then YES
Then, the process proceeds to step S34, and if TV>TvL, the process proceeds to step S35 if NO. In step S34, the LOWSS signal is set to High to vibrate marks CA1 and CA2 to issue a camera shake warning. Turn off CA2.

Figure 44 shows CPUl0 and switch S1.52°SB, S
Indicates the relationship with M.

Table 1 <Combination of r2++ and B-> Bl-r51-r53. r61-r652-r54 B3-r55-r58. r67, r6BB4-rl
~r29 B5 - r3 (1-r43 B6-r59.r60 B7 - r44~r50 B8 -r66 Table 2 Table 2 (Continued) Table 2 (Continued) Effects of the Invention As described above, according to this invention, By displaying the standby state of the camera, you can clearly distinguish between standby and complete stoppage, you can know when the main switch is in a no-off state, and you can also check whether the camera is in operation such as metering, etc. It is possible to clearly determine whether

[Brief explanation of drawings]

FIG. 1 is a perspective view showing an example of a camera to which the present invention is applied, FIG. 2a is a front view of the viewfinder of the camera of FIG. 1, and FIG. FIG. 2C is a diagram showing an example of all the segments displayed on the internal display section of the display device of the present invention, and FIG. 3 is a diagram showing an example of the entire segment displayed on the internal display section of the display device of the present invention. Block diagram, Figure 4 is a detailed circuit diagram of the oscillation divider section in Figure 3, Figure 5 is a detailed circuit diagram of the common driver in Figure 3, and Figure 6 is a detailed circuit diagram of the segment driver in Figure 3. Circuit diagram, FIG. 7 is a detailed circuit diagram of the data latch section in FIG. 3, FIG. 8rA is a detailed circuit diagram of the decoder section in FIG. 3, and FIG. 9 is a detailed circuit diagram of the switch circuit SWI in FIG. 8. Figure 10 is a circuit diagram showing details of symbols in the circuit, Figure 11 is a detailed circuit diagram of the data conversion section, and Figure 12 is the switch circuit SW2 of Figure 8.
The detailed circuit diagrams of Figures 13, 14 and 15 are shown in Figure 8.
16a is a detailed circuit diagram of the output control section of FIG. 8; FIG. 16 is a detailed circuit diagram of a part of the circuit of FIG. 8; FIG. 17 Figures 20 to 20 are diagrams showing the relationship between input signals and displays;
Figures 23 to 23 are detailed circuit diagrams of the data converter in Figure 8, Figure 24 is a detailed circuit diagram of the voltage generator in Figure 3, and Figures 25 to 27 are detailed circuit diagrams of the voltage generator in Figure 3. Waveform diagram of main parts,
Figure 28a, Figures 28 to 34a, Figures 34 and 35 are diagrams showing various aspects of display, and Figure 36 is a diagram showing the relationship between signals and registers. Figure 37 a, b, e,
Figure 38a, b, Figure 39a. FIG. 40 is a flowchart of the CPU showing the display selection operation, and FIG. 41 is a diagram showing various aspects of display.
FIG. 42 is a flowchart showing the operation of the CPU shown in FIG. 42 is a diagram showing another aspect of the camera shake display, FIG. 43 is a flowchart of the CPU showing the operation of the camera shake display, and FIG. 44 is a part of the CPU in FIG. FIG. 4. External display section, 6. Inner display section, 10. CPU
, 22... data latch, 23... decoder, 24...
・Segment driver. Patent Applicant Minolta Camera Co., Ltd. Agent Patent Attorney Aoyama Aoyama (2 others) Figure 2 a Figure 2 Figure 2 C Figure 20 SC2505 23 Q40 Loincloth 2 Rei No. 0.5 ■ 1.5 Self e , 5 Yo 3.5 5.5 No two 1: v: ay Rui Nao (Hinoki - / (- Bui Koie 4
+Mun 14th Figure 19 Figure 28 (a) P mode 1/250 F5. SAVE13°:T
,;:; I5. S port Fig. 29 (0) A:E-)'(/250 F5.6 AVE, ErS
LM B5. :E, mouth Fig. 30 (0) S mode 1/250 F5.6 AVε-ζ口ε″5:j5 ri, 2° Fig. 31 (a) M mode J-' 8” Fl, 4 5POT meter +6.5Ev C8″h 1.l-, l hard 8.5.cause 32nd
Figure (a) Sζ + 1, -1 Figure 33 (a) PROGRAM: f r4 n rt L jl ! J J, I IE'C::::::: [U:', 5 +:
, 1 Exit Fig. 34 (a) Fig. 34 (b) 11J IJ Fig. 35 Fig. 37 C Fig. 37 exit 'fLl (JIJ l)? mouth Figure 39 mouth; 4) 5 -m -h (i!ilN mouth Figure 40 Figure 41 Figure 42 (a) (b) (C) Figure 43 Figure 44

Claims (1)

[Claims] (1) There is a stop state in which the main switch is turned off, a standby state in which the main switch is turned on but not yet in the shooting operation state, and a shooting operation state. display mode,
A display device for a camera, comprising display means that turns off all lights in a stopped state and displays a specific segment in a standby state.