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JPS57211780A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57211780A
JPS57211780A JP56097209A JP9720981A JPS57211780A JP S57211780 A JPS57211780 A JP S57211780A JP 56097209 A JP56097209 A JP 56097209A JP 9720981 A JP9720981 A JP 9720981A JP S57211780 A JPS57211780 A JP S57211780A
Authority
JP
Japan
Prior art keywords
steep slope
slope
plane
substrate
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56097209A
Other languages
Japanese (ja)
Inventor
Hisashi Haneda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56097209A priority Critical patent/JPS57211780A/en
Publication of JPS57211780A publication Critical patent/JPS57211780A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
    • H10D64/027—Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations

Landscapes

  • Weting (AREA)

Abstract

PURPOSE:To permit the manufacture of a short-channel MOSFET with high accuracy by a method wherein an{111}easy slope and a{111}steep slope are formed on a substrate having a{211}plane by anisotropic etching and the steep slope is used as a schannel region. CONSTITUTION:An etching-resistant film 32 is formed on a semiconductor substrate 31 including a <110> crystal axis at a main plane and which is near at a{211}plane and an opening section (a) in which two faced sides are in parallel with the <110> is provided at the film and a{111}easy slope 33 and a{111}steep slope 34 are formed by applying anisotropic etching. Next, an impurity is vertically implanted in the substrate 31 to form source and drain regions 36, 37 and a gate electrode 38 is also formed at the{111}steep slope 34 through a gate insulating film. This can easily make a short channel MOSFET with high accuracy.
JP56097209A 1981-06-23 1981-06-23 Manufacture of semiconductor device Pending JPS57211780A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56097209A JPS57211780A (en) 1981-06-23 1981-06-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56097209A JPS57211780A (en) 1981-06-23 1981-06-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57211780A true JPS57211780A (en) 1982-12-25

Family

ID=14186226

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56097209A Pending JPS57211780A (en) 1981-06-23 1981-06-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57211780A (en)

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