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JPS56104470A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS56104470A
JPS56104470A JP686880A JP686880A JPS56104470A JP S56104470 A JPS56104470 A JP S56104470A JP 686880 A JP686880 A JP 686880A JP 686880 A JP686880 A JP 686880A JP S56104470 A JPS56104470 A JP S56104470A
Authority
JP
Japan
Prior art keywords
layer
oxide film
type
gate
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP686880A
Other languages
Japanese (ja)
Inventor
Hideshi Ito
Kazutoshi Ashikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP686880A priority Critical patent/JPS56104470A/en
Publication of JPS56104470A publication Critical patent/JPS56104470A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To decrease the channel of the semiconductor device in an MOSFET by injecting impurity ion through a gate oxide film and forming a low impurity density layer connected to a drain by self-alignment as a high withstand voltage layer. CONSTITUTION:A polysilicon layer is formed through a gate oxide film 2 on a p type Si substrate 1, and etched with the gate 8a and the periphery 8b retained. Then, the parts 6, 7 becoming the source and drain regions are removed from the oxide film thereon, impurity is diffused, and a polysilicon gate high density layer 8c and source and drain n<+> type diffused regions 6, 7 are simultaneously formed. Thereafter, a mask 9 for covering the polysilicon gate part 8c and the source 6 is formed, and the polysilicon gate part not covered by the mask is etched and removed. Phosphorus ions are eventually implanted to form an n<-> type layer 10 becoming a high withstand voltage layer is formed on the surface of the p type Si substrate through the oxide film 2a.
JP686880A 1980-01-25 1980-01-25 Semiconductor device and manufacture thereof Pending JPS56104470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP686880A JPS56104470A (en) 1980-01-25 1980-01-25 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP686880A JPS56104470A (en) 1980-01-25 1980-01-25 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS56104470A true JPS56104470A (en) 1981-08-20

Family

ID=11650208

Family Applications (1)

Application Number Title Priority Date Filing Date
JP686880A Pending JPS56104470A (en) 1980-01-25 1980-01-25 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS56104470A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5874340A (en) * 1996-07-17 1999-02-23 Advanced Micro Devices, Inc. Method for fabrication of a non-symmetrical transistor with sequentially formed gate electrode sidewalls
US5904529A (en) * 1997-08-25 1999-05-18 Advanced Micro Devices, Inc. Method of making an asymmetrical IGFET and providing a field dielectric between active regions of a semiconductor substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5874340A (en) * 1996-07-17 1999-02-23 Advanced Micro Devices, Inc. Method for fabrication of a non-symmetrical transistor with sequentially formed gate electrode sidewalls
US5904529A (en) * 1997-08-25 1999-05-18 Advanced Micro Devices, Inc. Method of making an asymmetrical IGFET and providing a field dielectric between active regions of a semiconductor substrate

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