JPS5661163A - Preparation of charge connecting element - Google Patents
Preparation of charge connecting elementInfo
- Publication number
- JPS5661163A JPS5661163A JP13850479A JP13850479A JPS5661163A JP S5661163 A JPS5661163 A JP S5661163A JP 13850479 A JP13850479 A JP 13850479A JP 13850479 A JP13850479 A JP 13850479A JP S5661163 A JPS5661163 A JP S5661163A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline
- layer
- pattern
- wiring
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000012535 impurity Substances 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 238000000034 method Methods 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 238000000992 sputter etching Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0198—Integrating together multiple components covered by H10D44/00, e.g. integrating charge coupled devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Abstract
PURPOSE:To improve the integration of an element without increasing photoetching accuracy by a method wherein a reverse pattern is provided during the manufacturing process when forming two layers of wiring patterns on a charge connecting element to form polycrystalline Si wiring by utilizing the patterns. CONSTITUTION:The laminated layers of SiO2 18 and Si3N4 19 are attached to an Si substrate 17, on which a reverse pattern 20 opposite to the electrode wiring in the first layer to be formed later using a SiO2 layer is formed. Next, a resist mask 21 located partly above the pattern 20 and partly above the film 19 is provided on the pattern 20 in order to form a region 22 by injecting the ions of impurities B1. Then, the whole surface is covered with polycrystalline 23 containing inpurities to be used as the first layer wiring and a resist mask 24. Sputter-etching B2 is provided then to allow the polycrystalline 23 on only the pattern 20. This process is repeated to further provide a layer of impurities 27 and bury the second layer of polycrystalline 28 containing impurities between the region 27 and the polycrystalline 23 via an SiO2 film 25.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13850479A JPS5661163A (en) | 1979-10-25 | 1979-10-25 | Preparation of charge connecting element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13850479A JPS5661163A (en) | 1979-10-25 | 1979-10-25 | Preparation of charge connecting element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5661163A true JPS5661163A (en) | 1981-05-26 |
Family
ID=15223666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13850479A Pending JPS5661163A (en) | 1979-10-25 | 1979-10-25 | Preparation of charge connecting element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5661163A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0715347A2 (en) * | 1994-12-02 | 1996-06-05 | Eastman Kodak Company | Method of making a charge coupled device with edge aligned implants and electrodes |
-
1979
- 1979-10-25 JP JP13850479A patent/JPS5661163A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0715347A2 (en) * | 1994-12-02 | 1996-06-05 | Eastman Kodak Company | Method of making a charge coupled device with edge aligned implants and electrodes |
| EP0715347A3 (en) * | 1994-12-02 | 1996-09-11 | Eastman Kodak Co | Method of manufacturing a charge transfer device with self-aligned implant and electrode edges |
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