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JPS5687343A - Forming method of wiring - Google Patents

Forming method of wiring

Info

Publication number
JPS5687343A
JPS5687343A JP16391779A JP16391779A JPS5687343A JP S5687343 A JPS5687343 A JP S5687343A JP 16391779 A JP16391779 A JP 16391779A JP 16391779 A JP16391779 A JP 16391779A JP S5687343 A JPS5687343 A JP S5687343A
Authority
JP
Japan
Prior art keywords
pattern
resist
resist film
etching
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16391779A
Other languages
Japanese (ja)
Inventor
Koji Hirano
Takeshi Nakajima
Toshiro Tsumori
Atsu Touto
Mitsuru Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP16391779A priority Critical patent/JPS5687343A/en
Publication of JPS5687343A publication Critical patent/JPS5687343A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form a very fine wiring pattern in good uniformity by a method wherein the first resist layer and the second resist layer slower in etching speed than the former are laminated on a substrate side and applied plasma etchings. CONSTITUTION:An SiO2 substrate 1 is applied a coating with an intensifying resist layer 2, a baking, and further coating with the second resist film 3 and a baking to obtain two coating films different in sensitivity. The resist film 3 is exposed and developed by an ordinary method, by which a desired resist pattern is attained, and then, the resist film 2 is applied an etching to obtain the pattern 5, using a plasma etching device. Subsequently, Al is evaporated and the others except for the Al on the substrate are removed by a fuming nitric acid. Thus, the pattern in under-cut like can be obtained due to the resist film of more than 10 times in the etching speed.
JP16391779A 1979-12-17 1979-12-17 Forming method of wiring Pending JPS5687343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16391779A JPS5687343A (en) 1979-12-17 1979-12-17 Forming method of wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16391779A JPS5687343A (en) 1979-12-17 1979-12-17 Forming method of wiring

Publications (1)

Publication Number Publication Date
JPS5687343A true JPS5687343A (en) 1981-07-15

Family

ID=15783272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16391779A Pending JPS5687343A (en) 1979-12-17 1979-12-17 Forming method of wiring

Country Status (1)

Country Link
JP (1) JPS5687343A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892224A (en) * 1981-11-27 1983-06-01 Matsushita Electronics Corp Pattern formation
JPS61263131A (en) * 1985-05-15 1986-11-21 Nippon Telegr & Teleph Corp <Ntt> Formation of finely-patterned layer
JPS62120046A (en) * 1985-11-20 1987-06-01 Sanyo Electric Co Ltd Manufacture of semiconductor device
JPH0518593U (en) * 1991-08-21 1993-03-09 株式会社トミー Orbital toy

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892224A (en) * 1981-11-27 1983-06-01 Matsushita Electronics Corp Pattern formation
JPS61263131A (en) * 1985-05-15 1986-11-21 Nippon Telegr & Teleph Corp <Ntt> Formation of finely-patterned layer
JPH0461492B2 (en) * 1985-05-15 1992-10-01 Nippon Telegraph & Telephone
JPS62120046A (en) * 1985-11-20 1987-06-01 Sanyo Electric Co Ltd Manufacture of semiconductor device
JPH0518593U (en) * 1991-08-21 1993-03-09 株式会社トミー Orbital toy

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