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JPS57130431A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57130431A
JPS57130431A JP1673381A JP1673381A JPS57130431A JP S57130431 A JPS57130431 A JP S57130431A JP 1673381 A JP1673381 A JP 1673381A JP 1673381 A JP1673381 A JP 1673381A JP S57130431 A JPS57130431 A JP S57130431A
Authority
JP
Japan
Prior art keywords
film
wiring
etching
mask
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1673381A
Other languages
Japanese (ja)
Inventor
Akira Abiru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1673381A priority Critical patent/JPS57130431A/en
Publication of JPS57130431A publication Critical patent/JPS57130431A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain an Al wiring having a desired width by a method wherein a resist film-made mask of a predetermined pattern is provided on an Al thin film to form a wiring of minute pattern thereon, the entire face is covered with oxide film, an etching is provided, an oxide film having the width same as a wiring width is left in the side wall of resist film and an etching is provided for a thin film by using the oxide film as the mask. CONSTITUTION:An Al thin film 3 for forming a wiring of minute pattern is attached through SiO2 film 2 onto an Si substrate 1, and a photo resist film 4 formed as a predetermined pattern is provided thereon. Subsequently, an SiO2 film 5 having the same thickness as the thin film 3 is grown onto the entire face containing the foregoing area, a reactive ion etching is provided by using the gas of fluorocarbon like CF4 or CHF3 for reaction gas and the remaining area is removed while leaving the SiO2 film 5' along the side wall 4' of the film 4. Thereafter, the film 4 is removed by a plasma ashing, a plasma etching is provided by usng the film 5' for a mask to remove the film 3 in the exposed area and the unnecessary film 5' is removed to leave only a desired minute wiring 3'.
JP1673381A 1981-02-06 1981-02-06 Manufacture of semiconductor device Pending JPS57130431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1673381A JPS57130431A (en) 1981-02-06 1981-02-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1673381A JPS57130431A (en) 1981-02-06 1981-02-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57130431A true JPS57130431A (en) 1982-08-12

Family

ID=11924460

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1673381A Pending JPS57130431A (en) 1981-02-06 1981-02-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57130431A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58217499A (en) * 1982-06-10 1983-12-17 Toshiba Corp Fine working method of thin film
JPS59110168A (en) * 1982-12-15 1984-06-26 Nippon Telegr & Teleph Corp <Ntt> Manufacturing method of semiconductor device
JPS59132627A (en) * 1983-01-20 1984-07-30 Matsushita Electronics Corp Pattern formation
JPS6010732A (en) * 1983-06-30 1985-01-19 Toshiba Corp Manufacture of semiconductor device
JPS62105426A (en) * 1985-10-30 1987-05-15 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション Formation of mask structure of the extent of sub-microns
JPS62126637A (en) * 1985-11-18 1987-06-08 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション Formation of aperture
WO2008149989A1 (en) * 2007-06-08 2008-12-11 Tokyo Electron Limited Patterning method

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58217499A (en) * 1982-06-10 1983-12-17 Toshiba Corp Fine working method of thin film
JPH0370370B2 (en) * 1982-12-15 1991-11-07 Nippon Telegraph & Telephone
JPS59110168A (en) * 1982-12-15 1984-06-26 Nippon Telegr & Teleph Corp <Ntt> Manufacturing method of semiconductor device
JPS59132627A (en) * 1983-01-20 1984-07-30 Matsushita Electronics Corp Pattern formation
JPS6010732A (en) * 1983-06-30 1985-01-19 Toshiba Corp Manufacture of semiconductor device
JPS62105426A (en) * 1985-10-30 1987-05-15 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション Formation of mask structure of the extent of sub-microns
JPH0529133B2 (en) * 1985-10-30 1993-04-28 Intaanashonaru Bijinesu Mashiinzu Corp
JPS62126637A (en) * 1985-11-18 1987-06-08 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション Formation of aperture
JPH0543287B2 (en) * 1985-11-18 1993-07-01 Ibm
WO2008149989A1 (en) * 2007-06-08 2008-12-11 Tokyo Electron Limited Patterning method
JP2009016814A (en) * 2007-06-08 2009-01-22 Tokyo Electron Ltd Method for forming fine pattern
JP4589984B2 (en) * 2007-06-08 2010-12-01 東京エレクトロン株式会社 Method for forming fine pattern
KR101011490B1 (en) 2007-06-08 2011-01-31 도쿄엘렉트론가부시키가이샤 Patterning method
US8168375B2 (en) 2007-06-08 2012-05-01 Tokyo Electron Limited Patterning method

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