JPH11202970A - Clock skew preventing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output a clock signal having no clock skew by inputting clock signals having clock skews and to prevent the waveform of the outputted clock signal from being weakened. SOLUTION: This circuit is equipped with plural input lines 11a, 11b, and 11c for inputting plural clock signals and also equipped with a logic circuit 14 which inputs the plural clock signals and outputs a clock signal synchronized with the slowest clock signal among them. Then this circuit is equipped with output lines 17a, 17b, and 17c which input the clock signal outputted from this logic circuit 14 to a buffer and output plural clock signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock skew prevention circuit which receives a plurality of clock signals having a clock skew and outputs a plurality of clock signals having the same period.

[0002]

2. Description of the Related Art For example, in an integrated circuit such as an LSI,
A configuration is adopted in which one clock line is divided into a plurality of clock lines, and a clock buffer provided for each clock line is made as small as possible. In the case of this configuration, a phenomenon in which the cycle of the clock signal flowing through each clock line slightly shifts due to a difference in the size of the load connected to each clock line or the length of the wiring of each clock line, that is, a so-called clock skew occurs. May be.

[0003] Eliminating such clock skew,
As a clock output circuit for outputting a plurality of clock signals of the same cycle, there is a conventional configuration as shown in FIG. In this configuration, for example, three clock signals Sa and S
Buffers 2a, 2b, 2c are connected to three input lines 1a, 1b, 1c for inputting b and Sc, and output lines 3a, 3b, 3c are connected to these buffers 2a, 2b, 2c. Then, the three output lines 3a, 3b, 3c
Are short-circuited by the short-circuit line 4, that is, three buffers 2
The outputs of a, 2b, and 2c are configured to be short-circuited.

[0004]

In the above-mentioned conventional configuration, for example, three clock signals Sa, Sb, Sc having a clock skew as shown in FIG.
It is assumed that b and 1c are input. In this case, the rising of the clock signal Sa is fast, but the rising of the clock signals Sb and Sc are slow. Therefore, even if the signal output from the buffer 2a is at a high level, the signals output from the buffers 2b and 2c are at a low level. As a result, the clock signals Saout, Sbout, Sc output from the three output lines 3a, 3b, 3c short-circuited by the short-circuit line 4
Out has a problem that the waveform is distorted as shown in FIG. Then, the clock signal Saout,
When the waveforms of Sbout and Scout are rounded, various problems occur.

More specifically, when the buffers 2a, 2b and 2c are composed of, for example, CMOS integrated circuits, a through current flows. Further, when the next-stage circuit connected to the output lines 3a, 3b, 3c is formed of, for example, a CMOS integrated circuit, a drawback is that a through current flows through this circuit and the operation of the circuit is slowed down. there were. Furthermore,
In the above-described configuration, the case where three clock signals Sa, Sb, and Sc in which clock skew has occurred has been described. However, if the number of input clock signals further increases,
There is a tendency that the rounding of the waveform of the output clock signal becomes even worse.

SUMMARY OF THE INVENTION An object of the present invention is to provide a configuration in which a plurality of clock signals having a clock skew are input and a clock signal having the same cycle is output, thereby preventing the output clock signal from becoming distorted. A clock skew prevention circuit is provided.

[0007]

A clock skew prevention circuit according to the present invention (see FIG. 1) has a plurality of input lines for inputting a plurality of clock signals, and a plurality of input lines for inputting the plurality of clock signals, and a slowest clock among the input lines. It is characterized by comprising a logic circuit that outputs a clock signal synchronized with a signal, and an output line that inputs a clock signal output from the logic circuit to a buffer and outputs a plurality of clock signals.

In the above configuration, the logic circuit outputs a clock signal synchronized with the slowest clock signal among the plurality of input clock signals. Then, this clock signal is input to the buffer and output from the output line as a plurality of clock signals. In the case of this configuration, a plurality of clock signals with clock skew can be input and a clock signal with zero clock skew can be output. Further, since this processing is executed by a logic circuit, the output clock signal No rounding of the waveform occurs.

It is more preferable to provide a feedback circuit for self-holding the level of the signal output from the buffer (see FIG. 3).

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an electric circuit diagram of the clock skew prevention circuit of the present embodiment.
In FIG. 1, three input lines 11a, 11a, 1c for inputting a plurality of, for example, three clock signals Sa, Sb, Sc.
1 b and 11 c are connected to the input terminals of the three-input NAND circuit 12 and to the input terminals of the three-input NOR circuit 13. In this case, the NAND circuit 12 and the NOR circuit 13 constitute a logic circuit 14.

The output terminal of the NAND circuit 12 is connected to P
It is connected to the gate of the channel MOS transistor 15. The output terminal of the NOR circuit 13 is an N-channel MO
Connected to the gate of S transistor 16. The source of the P-channel MOS transistor 15 is a DC voltage terminal V
It is connected to the _DD, the source of the N-channel MOS transistor 16 is connected to the ground _{V SS.} And P
The drain of the channel MOS transistor 15 and the drain of the N-channel MOS transistor 16 are connected,
Further, three output lines 17a, 17b, 17
c is connected. In this case, the buffer 18 is configured by a CMOS circuit including a P-channel MOS transistor 15 and an N-channel MOS transistor 16.

Next, the operation of the above circuit will be described with reference to FIG. In this case, three clock signals Sa, S
It is assumed that clock skews shown in FIGS. 2A, 2B, and 2C exist in b and Sc.

First, in a period Ta until time t1, the three clock signals Sa, Sb, Sc are all at low level, so that the output signal Sd of the NAND circuit 12 becomes high level, and the output signal Se of the NOR circuit 13 becomes High level. Therefore, when the P-channel MOS transistor 15 is turned off and the N-channel MOS transistor 16 is turned on, the low-level output signals Saout, Sbout, Sc from the output lines 17a, 17b, 17c.
out is output.

In a period Tb from time t1 (the time when the earliest clock signal Sa rises to the high level) to time t2 (the time when the latest clock signal Sc rises to the high level), the output of the NAND circuit 12 is output. The signal Sd becomes high level, and the output signal S
e becomes low level. Accordingly, the P-channel MOS transistor 15 and the N-channel MOS transistor 16 are both turned off (dynamic period), and the output line 17
a, 17b, 17c output signals Saout, Sbout
t and Scout maintain the current state, that is, the low level.

Next, at time t2 (the latest clock signal S
During a period Tc from the time point when c rises to the high level to the time t3 (the time point when the earliest clock signal Sa falls to the low level), the output signal S of the NAND circuit 12 is output.
d goes low, and the output signal Se of the NOR circuit 13
Becomes low level. Therefore, the P-channel MOS transistor 15 turns on, and the N-channel MOS transistor 1
6 are turned off, the output lines 17a, 17b, 17
c to output signals Saout, Sbout,
Scout is output.

Subsequently, during a period Td from time t3 (the time when the earliest clock signal Sa falls to the low level) to time t4 (the time when the latest clock signal Sc falls to the low level), the output signal of the NAND circuit 12 is output. Sd goes high, and the output signal S of the NOR circuit 13
e becomes low level. Accordingly, the P-channel MOS transistor 15 and the N-channel MOS transistor 16 are both turned off (dynamic period), and the output line 17
a, 17b, 17c output signals Saout, Sbout
t and Scout maintain the current state, that is, the high level.

Thereafter, in a period Te after time t4 (the point at which the latest clock signal Sc falls to a low level), the output signal Sd of the NAND circuit 12 becomes high and the output signal Se of the NOR circuit 13 becomes high. Level. Accordingly, when the P-channel MOS transistor 15 is turned off and the N-channel MOS transistor 16 is turned on, low-level output signals Saout, Sbout, and Scout are output from the output lines 17a, 17b, and 17c.

That is, in the above-described clock skew prevention circuit, when three clock signals Sa, Sb, Sc having a clock skew are input, a clock signal synchronized with the slowest clock signal Sc (of the same period) is input. Clock signals) are output signals Saout, Sbout
It is configured to be output from output lines 17a, 17b, and 17c as t and Scout.

With such a circuit configuration,
Three clock signals Sa and S with clock skew
By inputting b and Sc, three clock signals Saout, Sbout and Scout having zero clock skew can be output. Moreover, in the case of this configuration, the three clock signals Sa, Sb, S
The clock signals Saout, Sbout, and Scout synchronized with the slowest clock signal Sc of c can be output. Output clock signals Saout, S
bout and Scout are buffers 18 by a logic circuit.
Therefore, the rounding of the waveform as shown in FIG. 7 does not occur. Thereby, the output lines 17a, 1
The next stage circuit connected to 7b, 17c is, for example, CMOS
When an integrated circuit is used, a through current can be prevented from flowing through this circuit, and the operation of the next-stage circuit can be accelerated.

In the above embodiment, since the buffer 18 is provided on the output side of the logic circuit 14, the driving signals required for the clock signals Saout, Sbout, and Scout output from the output lines 17a, 17b, 17c are provided. A force (a driving force for driving a connected load) can be applied. Further, in the above embodiment, the buffer 18
Is controlled by the logic circuit 14, the period during which both the P-channel MOS transistor 15 and the N-channel MOS transistor 16 are turned on is eliminated. Therefore, the buffer 18
Can be prevented from flowing through, and power consumption can be reduced.

FIGS. 3 and 4 show a second embodiment of the present invention. Differences from the first embodiment will be described. The same parts as those in the first embodiment are denoted by the same reference numerals. In the second embodiment, as shown in FIG.
An inverter 19 and a clocked inverter 20 are connected between the output terminal of the D circuit 12 and the gate of the P-channel MOS transistor 15 as shown in FIG.
An inverter 21 and a clocked inverter 22 are connected between the output terminal of the R circuit 13 and the gate of the N-channel MOS transistor 16 as shown. Note that the clocked inverters 20 and 22 have two P-channel M
An OS transistor and two N-channel MOS transistors are connected as shown.

The P-channel MOS transistor 15
And the gate of the N-channel MOS transistor 16 are connected. Further, a connection point between these gates (hereinafter, this point is referred to as BufferIn) and a connection point where the drain of the P-channel MOS transistor 15 and the drain of the N-channel MOS transistor 16 are connected (that is, three output lines 17a) , 17b, 17c), a feedback inverter 23 is connected as shown. In the case of this configuration, the feedback circuit 23 of the present invention is provided by the feedback inverter 23 connected as described above.
4 are configured.

Next, the operation of the above circuit will be described with reference to FIG. In this case, three clock signals Sa, S
It is assumed that clock skews as shown in FIGS. 4A, 4B, and 4C exist in b and Sc.

First, in the period Ta ', the output signal Sd of the NAND circuit 12 goes high and the output signal Sf of the inverter 19 goes low, so that the clocked inverter 20 closes (high impedance). At the same time, the output signal Se of the NOR circuit 13 goes high and the output signal Sg of the inverter 21 goes low, so that the clocked inverter 22 becomes active and the clocked inverter 22
3 output signal Se, that is, the high-level signal is
Output to erIn.

At this time, the output lines 17a, 17b, 17c
Of the output signals Saout, Sbout, and Scout, which are the previous values, go to the low level through the feedback inverter 23, and this low level signal is supplied to the BufferIn. Therefore, the low-level signal from the feedback inverter 23 and the high-level signal from the clocked inverter 22 quarrel. However, in this case, the transistor size of the feedback inverter 23 is set to the minimum size that can maintain the level of BufferIn when both the clocked inverters 20 and 22 are closed (turned off). Therefore, the high-level signal from the clocked inverter 22 wins, the P-channel MOS transistor 15 turns off, and the N-channel
When the S-transistor 16 is turned on, low-level output signals Saout, Sbout, and Scout are output from the output lines 17a, 17b, and 17c.

Subsequently, in the period Tb ', the NAND
Since the output signal Sd of the circuit 12 becomes high level and the output signal Sf of the inverter 19 becomes low level, the clocked inverter 20 closes (becomes high impedance). At the same time, the output signal Se of the NOR circuit 13 goes low, and the output signal Sg of the inverter 21 goes high, so that the clocked inverter 22 closes (becomes high impedance). In this case, the output signals Saout, S of the output lines 17a, 17b, 17c are output.
The low level, which is the current value of bout, Scout,
It goes high through the feedback inverter 23, and this high level signal is provided to the BufferIn.

Therefore, P-channel MOS transistor 1
5 is turned off and the N-channel MOS transistor 16 is turned on, so that the output signals Saout, Sbout, Scout of the output lines 17a, 17b, 17c maintain the current state, that is, the low level. That is, in the period Tb ', the output signal S output from the buffer 18 by the feedback inverter 23 of the feedback circuit 24.
The state of aout, Sbout, and Scout is configured to be self-held.

Next, in the period Tc ', the output signal Sd of the NAND circuit 12 becomes low level and the output signal Sf of the inverter 19 becomes high level, so that the clocked inverter 20 becomes active. With this, N
Since the output signal Se of the OR circuit 13 becomes low level and the output signal Sg of the inverter 21 becomes high level, the clocked inverter 22 is closed (has high impedance). Then, since the clocked inverter 20 becomes active, the clocked inverter 20 outputs the output signal Sd of the NAND circuit 12, that is, outputs a low level signal to BufferIn.

At this time, the output lines 17a, 17b, 17c
Of the output signals Saout, Sbout, and Scout of FIG. 2 go to the high level through the feedback inverter 23, and the high-level signal
provided to uufferIn. Therefore, the high-level signal from the feedback inverter 23 and the clocked inverter 2
The low level signal from 0 fights. However, in this case, as described above, the transistor size of the feedback inverter 23 is set to the minimum size that can maintain the level of BufferIn when the clocked inverters 20 and 22 are both closed (off). , The low level signal from the clocked inverter 20 wins.
Therefore, the P-channel MOS transistor 15 turns on,
When the N-channel MOS transistor 16 is turned off, the high-level output signals Saout, Sbout, S
cout is output from the output lines 17a, 17b, 17c.

In the period Td ', the NAND
Since the output signal Sd of the circuit 12 becomes high level and the output signal Sf of the inverter 19 becomes low level, the clocked inverter 20 closes (becomes high impedance). At the same time, the output signal Se of the NOR circuit 13 goes low, and the output signal Sg of the inverter 21 goes high, so that the clocked inverter 22 closes (becomes high impedance). In this case, the output signals Saout, S of the output lines 17a, 17b, 17c are output.
The high level which is the current value of bout, Scout is
It goes low through the feedback inverter 23, and this low level signal is provided to the BufferIn.

Therefore, P-channel MOS transistor 1
5 is turned on and the N-channel MOS transistor 16 is turned off, so that the output signals Saout, Sbout, Scout of the output lines 17a, 17b, 17c maintain the current state, that is, the high level. That is, the above period Td
′, Output signals Saout, S output from the buffer 18 by the feedback inverter 23 of the feedback circuit 24.
The state of bout and Scout is self-held.

Subsequently, in the period Te ', the NAND
Since the output signal Sd of the circuit 12 becomes high level and the output signal Sf of the inverter 19 becomes low level, the clocked inverter 20 closes (becomes high impedance). At the same time, the output signal Se of the NOR circuit 13 goes high and the output signal Sg of the inverter 21 goes low, so that the clocked inverter 22 becomes active and the clocked inverter 22
3 output signal Se, that is, the high-level signal is
Output to erIn.

At this time, the output lines 17a, 17b, 17c
Of the output signals Saout, Sbout, and Scout of the above-mentioned output signal go to the low level through the feedback inverter 23, and the low-level signal
provided to uufferIn. Therefore, the low-level signal from the feedback inverter 23 and the clocked inverter 2
The high level signal from 2 fights. However, in this case, since the transistor size of the feedback inverter 23 is set to the minimum size as described above, the high-level signal from the clocked inverter 22 wins. As a result, the P-channel MOS transistor 15 is turned off,
When the channel MOS transistor 16 is turned on, the low-level output signals Saout, Sbout, S
cout is output from the output lines 17a, 17b, 17c.

The configuration of the second embodiment other than that described above is the same as the configuration of the first embodiment. Therefore, in the second embodiment, substantially the same operation and effect as in the first embodiment can be obtained. In particular, in the second embodiment, the feedback inverter 23, the inverters 19 and 21, and the clocked inverters 20 and 22 are provided, and the output signals Saout, Sbout, and Scout output from the buffer 18 are provided in the periods Tb 'and Td'. The level state is self-held by feedback. As a result, the dynamic period (specifically, the period Tb and the period Td) existing in the first embodiment can be eliminated, and a circuit that is stable against noise and the like and operates stably can be realized.

Incidentally, in the first embodiment, in the period Tb and the period Td, the P-channel MOS transistor 1
5 and the N-channel MOS transistor 16 are both turned off, and the output signals Saout, Sbout, and Scout of the output lines 17a, 17b, and 17c are dynamically held. In this state, if noise or the like acts on the output lines 17a, 17b, and 17c, the levels of the output signals Saout, Sbout, and Scout may fluctuate.

The first embodiment includes an inverter 19,
21, since the clocked inverters 20 and 22 do not exist, the circuit operates quickly. Therefore, when the influence of noise or the like is hardly affected, for example, when the dynamic period (the period Tb and the period Td) is a very short time (that is, when the clock skew of the clock signals Sa, Sb, Sc is small), The circuit configuration of the first embodiment is sufficient. On the other hand, when the clock skew becomes large and the dynamic period becomes long, it is liable to be affected by noise or the like. Therefore, it is preferable to configure as in the second embodiment.

In each of the above embodiments, three clock signals Sa, Sb, and Sc are input. However, the present invention is not limited to this configuration. Four or more clock signals are input. In that case, a NAND circuit having four inputs or more and a NOR circuit having four inputs or more may be used. Here, when the number of inputs of the NAND circuit and the NOR circuit increases, the number of inputs is fixed to an appropriate number in design, a plurality of clock signals are divided for each fixed number of inputs, and synchronization is established. The obtained output signal may be synchronized again. Hereinafter, a third embodiment shown in FIG. 5 will be described as an example of such a configuration.

In the third embodiment, for example, 100 clock signals are input, and while these 100 clock signals are signal-processed into ten sets of ten signals, for example, 100 clock signals of the same period are processed. It is configured to output a signal. Specifically, first, the 100 clock signals S001 to S100 are divided into 10 groups of 10 clock signals, and the first 10 clock signals S0 out of the divided groups are divided into 10 groups.
01 to S010 to the first clock skew prevention circuit 25
-1 and the next ten clock signals S011 to S011
S020 is input to the second clock skew prevention circuit 25-2,..., And the last ten clock signals S09.
1 to S100 are replaced by a tenth clock skew prevention circuit 25.
-10.

The above ten clock skew prevention circuits 2
5-1 to 25-10 all have the same circuit configuration. In the clock skew prevention circuit of the first embodiment or the second embodiment, instead of the NAND circuit 12 and the NOR circuit 13, a 10-input NAND circuit and 10-input NOR
This is a circuit in which a circuit is provided and an output line is further integrated.

The output signal Smot1 from the first clock skew prevention circuit 25-1 and the output signal Smot2 from the second clock skew prevention circuit 25-2.
,..., The tenth clock skew prevention circuit 25-
The output signal Smot10 from the tenth clock is input to the eleventh clock skew prevention circuit 26-1. Also,
The output signal Smot1 from the first clock skew prevention circuit 25-1 and the second clock skew prevention circuit 25
-2, and the output signal Sm from the tenth clock skew prevention circuit 25-10.
ot10 and the twelfth clock skew prevention circuit 26.
-2.

Hereinafter, similarly, the output signals Smot1 to S10 from the first clock skew prevention circuit 25-1 are output.
The output signal Smot10 from the clock skew prevention circuit 25-10 of FIG.
6-3,..., Twentieth clock skew prevention circuit 2
6-10.

Here, the ten clock skew prevention circuits 26-1 to 26-10 all have the same circuit configuration. In the clock skew prevention circuit of the first embodiment or the second embodiment, a NAND circuit is used. This circuit is provided with a 10-input NAND circuit and a 10-input NOR circuit in place of the 12 and the NOR circuit 13, and further has 10 output lines.

As a result, 100 clock signals Sout001 to Sout100 are output from the ten clock skew prevention circuits 26-1 to 26-10, and these 100 clock signals Sout001 to Sout100 are output.
out100 is a clock signal of the same cycle. In this case, the output clock signals Sout001 to Sout
100 is the input 100 clock signals S001
The clock signal is synchronized with the slowest clock signal of S100 and has zero clock skew.

Although the third embodiment is applied to a configuration in which 100 clock signals are input, it may be applied to a configuration in which 99 or less or 101 or more clock signals are input. In the third embodiment, the present invention is applied to the configuration in which the clock signal is divided into ten sets.
You may apply to the structure divided into sets or more. Further, the third
In the embodiment, the divided clock signal is configured to be synchronized in two stages. However, the divided clock signal may be configured to be synchronized in three or more stages.

[0045]

As is apparent from the above description, the present invention has a logic circuit which receives a plurality of clock signals and outputs a clock signal synchronized with the slowest clock signal among them. It is possible to input a plurality of clock signals with clock skew and output a clock signal with zero clock skew, while preventing the output clock signal from being distorted. It works.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart

FIG. 3 is a view corresponding to FIG. 1, showing a second embodiment of the present invention;

FIG. 4 is a diagram corresponding to FIG. 2;

FIG. 5 is a block diagram showing a third embodiment of the present invention.

FIG. 6 is a diagram corresponding to FIG. 1 showing a conventional configuration.

FIG. 7 is a diagram corresponding to FIG. 2;

[Explanation of symbols]

11a, 11b and 11c are input lines, 12 is a NAND circuit, 13 is a NOR circuit, 14 is a logic circuit, 15 is a P-channel MOS transistor, 16 is an N-channel MOS transistor, 17a, 17b and 17c are output lines, and 18 is a buffer. , 19 is an inverter, 20 is a clocked inverter, 21 is an inverter, 22 is a clocked inverter,
23 is a feedback inverter, 24 is a feedback circuit, and 25-1 and 25-2
5-10 is a clock skew prevention circuit, 26-1 to 26
-10 indicates a clock skew prevention circuit.

Claims (3)

[Claims] 1. A plurality of input lines for inputting a plurality of clock signals, a logic circuit receiving the plurality of clock signals and outputting a clock signal synchronized with the slowest clock signal among the input lines, and an output from the logic circuit An output line for inputting the clock signal to a buffer and outputting a plurality of clock signals. 2. The clock skew prevention circuit according to claim 1, wherein a buffer is provided on an output side of said logic circuit. 3. The clock skew prevention circuit according to claim 2, further comprising a feedback circuit for self-holding a level of a signal output from said buffer.