JPH05145385A - Cmos output buffer circuit - Google Patents

Abstract

PURPOSE:To obtain the CMOS output buffer circuit in which the production of switching noise is reduced with low power consumption. CONSTITUTION:A P-channel MOS transistor(TR) 3 and an N-channel MOS TR 4 connected in series between a power supply and ground are provided to the title circuit, its connecting pint is used for an output terminal 2, the output terminal of a NAND element 5 is connected to the gate of the P-channel MOS TR 3 and the output terminal of a NOR element 6 is connected to the gate of the N-channel MOS TR 4. Then an input signal IN from the input terminal 1 is inputted to one input terminal of the NAND element 5 and the NOR element 6 and a delayed input signal IN' through a delay circuit 7 is inputted to the other input terminal of the NAND element 5 and the NOR element 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS output buffer circuit which consumes less power and produces less noise.

[0002]

2. Description of the Related Art In recent years, in CMOS output buffer circuits that drive large currents due to speeding up due to miniaturization of CMOS devices and improvement in driving capability, the output logic level is changed from "L" to "H" level or "H" level. At the time of switching from "H" to "L" level, current consumption increases due to current flowing from the power supply to the ground side within the period in which the P-channel and N-channel MOS transistors are simultaneously turned on. As a result, ringing occurs, which causes problems such as circuit malfunction and adverse effects on other equipment due to switching noise.

In order to solve these problems, it has been proposed to reduce the through current and the consumption current and the switching noise by means as disclosed in Japanese Patent Laid-Open No. 2-101817 as a prior art. ing.
The principle of this proposed means is as shown in FIG.
ND element 104, 2-input NOR element 105, NOT element
103 and a P-channel M connected in series between the power supply and ground
OS transistor 106 and N-channel MOS transistor 1
07, and one input end of the NOR element 105 is fixed to the ground level, and one input end of the NAND element 104 is NO.
The power supply level is fixed by the T element 103, the input terminal 101 of the output buffer circuit is connected to the other input terminal of the NAND element 104 and the NOR element 105, and the output terminal 102 is the P channel MOS transistor 106 and the N channel MOS transistor 107. It is configured to derive from the connection point of.

When an input signal IN as shown in FIG. 7 is applied, assuming that the logical threshold voltage of the NAND element 104 is V _b and the logical threshold voltage of the NOR element 105 is V _a , they have the same size. N of MOS transistor
When an AND element and a NOR element are configured, V _a <
Using the relationship of V _b , the NAND element 104 and the NO
The signal waveforms at the output terminals of the R element 105, that is, at the nodes A and B, are generated as shown in FIG. 7 so that the P-channel MOS transistor 106 and the N-channel MOS transistor 107 are not turned on at the same time. In FIG. 7, OUT is an output signal waveform.

[0005]

However, in the CMOS output buffer circuit proposed above, the device speed is improved due to the miniaturization of the device, and the driving capability is improved due to the further miniaturization, so that the input signal IN shown in FIG. When the rising time and the falling time of the NAND element become short, the signals at the nodes A and B change almost at the same time, and the NAND element
104 switching time from “H” to “L” level and switching time from “L” to “H” level,
NOR element 105 Not only is it difficult to obtain a period in which the P-channel and N-channel MOS transistors 106 and 107 are not turned on at the same time due to the difference in switching time, but also the time difference is extremely shortened due to the speedup due to the miniaturization of the element. There is a problem that a sufficient effect cannot be achieved due to variations and the like.

The present invention has been made to solve the above-mentioned problems in the conventional CMOS output buffer circuit. Even if the element speed is improved, the P-channel and N-channel MOS transistors for the output buffer are surely turned on at the same time. It is an object of the present invention to provide a CMOS output buffer circuit that eliminates the period of time for which the current is consumed and reduces the consumption current and switching noise due to the through current.

[0007]

In order to solve the above-mentioned problems, according to the present invention, as shown in the conceptual diagram of FIG.
The gate of the P-channel MOS transistor 3 at the final stage of the CMOS output buffer circuit composed of the channel MOS transistor 3 and the N-channel MOS transistor 4 is NA
In the CMOS output buffer circuit which is driven through the ND element 5 and the gate of the N-channel MOS transistor 4 is driven through the NOR element 6, one input terminal of each of the NAND element 5 and the NOR element 6 receives an input signal. IN is input, and the delayed input signal IN ′ obtained through the delay circuit 7 is input to the other input ends of the NAND element 5 and the NOR element 6.

In the CMOS output buffer circuit configured as described above, by inputting the input signal IN to the delay circuit 7, a delayed input signal IN 'as shown in the timing chart of FIG. 2 is generated. The input signal IN and the delayed input signal IN 'are transferred to the NAND element 5 and the NOR element 6
To the P-channel MOS transistor 3 and the N-channel MOS transistor 4, respectively, by generating the output signals A and B from the NAND element 5 and the NOR element 6, respectively. As a result, the P-channel MOS transistor 3 and the N-channel M at the final stage of the output buffer circuit
When the OS transistors 4 are not turned on at the same time, NAN
In addition to the propagation delay time from “H” to “L” level or “L” to “H” level of the D element 5 and the NOR element 6, the time difference between the input signal IN and the delay input signal IN ′ by the delay circuit 7 Only the period can be secured, and the period in which both the transistors 3 and 4 are turned on can be surely eliminated, thereby reducing the through current and the switching noise.

[0009]

EXAMPLES Next, examples will be described. FIG. 3 is a circuit configuration diagram showing a first embodiment of a CMOS output buffer circuit according to the present invention, and the same or corresponding members as those in the conceptual diagram shown in FIG. 1 are designated by the same reference numerals. In the figure, 1 is an input terminal for an input signal IN to the output buffer circuit, 2 is an output terminal for an output signal OUT of the output buffer circuit, 11 and 12
Is a transmission gate formed of a CMOS transistor, 5 is a 2-input NAND element, 6 is a 2-input NOR element, 3 is a P-channel MOS transistor, 4 is an N-channel MOS transistor, and they are connected in series between the power supply and ground. .. And the input terminal 1 is, as shown in the figure, NA
It is connected to one input terminal of the ND element 5 and the NOR element 6 and one input / output terminal of the transmission gates 11 and 12, and the other input / output terminal of the transmission gate 11 is connected to the other input terminal of the NAND element 5. And the other input / output terminal of the transmission gate 12 is NOR
It is connected to the other input terminal of the element 6. Also NAND
The output terminal of the element 5 is connected to the gate of the P-channel MOS transistor 3 and each gate input terminal of the transmission gate 11, and the output terminal of the NOR element 6 is connected to the gate of the N-channel MOS transistor 4 and each gate input terminal of the transmission gate 12. Each is connected.

Next, the operation of the CMOS output buffer circuit thus configured will be described based on the timing chart shown in FIG. The state of the circuit will be described assuming that the output is "L" level and the input is "L" level. First, when the input signal IN is at "L" level and the output signal OUT is at "L" level, the output C of the NAND element 5 is "H".
The level and the output D of the NOR element 6 are also at "H" level. At this time, when the input signal IN changes to "H" level, the output D of the NOR element 6 immediately becomes "L" level as shown in FIG. 4, and the N-channel MOS transistor 4 is turned off. Further, in the transmission gate 11, since the output C of the NAND element 5 is at the “H” level, only the N-channel MOS transistor forming the transmission gate 11 is turned on, and the ON resistance of this MOS transistor and the NAND element Due to the delay due to the gate capacitance of 5, the output A of the input signal IN
4, the output C of the NAND element 5 goes to the "L" level and the P channel MOS transistor 3
Is turned on, and the output signal OUT becomes "H" level. On the other hand, in the transmission gate 12, since the output D of the NOR element 6 is at the “L” level, only the P-channel MOS transistor forming the transmission gate 12 is turned on, and the input signal IN changes as shown in FIG. After a delay, its output B becomes "H" level.

Next, when the input signal IN changes to "L" level, the output C of the NAND element 5 immediately becomes "H" level and the P-channel MOS transistor 3 is turned off.
Further, in the transmission gate 12, since the output D of the NOR element 6 is at "L" level, the P channel MOS transistor forming the transmission gate 12 is turned on, and its output B is delayed with respect to the change of the input signal IN. Then, as shown in FIG. 4, it becomes "L" level and NO.
The output D of the R element 6 becomes "H" level and the N channel M
The OS transistor 4 is turned on and the output signal OUT is "L".
It becomes a level. On the other hand, the transmission gate 11
Since the output C of the NAND element 5 is at the "H" level, the N-channel MO which constitutes the transmission gate 11 is
The S transistor is turned on, and its output A becomes "L" level after the change of the input signal IN, as shown in FIG.

Thus, the transmission gate 1
When switching the NAND element 5 and the NOR element 6, 1 and 12 turn on the N-channel MOS transistor in the transmission gate 11 and turn on the P-channel MOS transistor in the transmission gate 12,
A delay is generated by the ON resistance and the gate capacitances of the NAND element 5 and the NOR element 6, but in a steady state after switching, the transmission gate 11 is a P channel MOS transistor and the transmission gate 12 is an N channel MOS transistor. Thus, it operates so as to keep the potentials of its outputs, the nodes A and B.

Next, a second embodiment will be described with reference to FIG. In the first embodiment described above, the two-input element is used as the NAND element and the NOR element, but the second embodiment uses the multi-input NAND element 15 and the NOR element 16 as shown in the figure. The input signal IN is input to one of these input terminals, and the other input / output terminals of the transmission gates 11 and 12 are commonly connected to the remaining input terminals.

In the CMOS output buffer circuit configured as described above, not only the delay is increased by using the NAND element and the NOR element as multiple inputs, but also the ON resistance of the MOS transistor forming the transmission gate,
The gate capacitances of the NAND element and the NOR element make the waveforms of the nodes A and B which are the outputs of the transmission gates round, and the difference in the logical inversion voltage between the NAND element and the NOR element is used to delay the waveform from the input signal IN. Can be generated and a similar effect can be obtained.

[0015]

As described above on the basis of the embodiments,
According to the present invention, the period in which the P-channel MOS transistor and the N-channel MOS transistor at the final stage of the CMOS output buffer circuit are not simultaneously turned on can be ensured only during the time difference between the input signal and the delay input signal by the delay circuit. In addition, it is possible to reduce the through current and the switching noise by eliminating the period in which both transistors are turned on.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing the principle of a CMOS output buffer circuit of the present invention.

FIG. 2 is a timing chart for explaining the operation of the CMOS output buffer circuit shown in FIG.

FIG. 3 is a circuit configuration diagram showing a first embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the first embodiment.

FIG. 5 is a circuit configuration diagram showing a second embodiment of the present invention.

FIG. 6 is a circuit configuration diagram showing a configuration example of a conventional CMOS output buffer circuit.

FIG. 7 is a timing chart for explaining the operation of the conventional example shown in FIG.

[Explanation of symbols]

 1 Input Terminal 2 Output Terminal 3 P Channel MOS Transistor 4 N Channel MOS Transistor 5 NAND Element 6 NOR Element 7 Delay Circuit

Claims (4)

[Claims] 1. A CMOS output buffer circuit composed of a P-channel MOS transistor and an N-channel MOS transistor, wherein the gate of the P-channel MOS transistor at the final stage is driven through a NAND element to produce an N-channel MOS transistor.
In a CMOS output buffer circuit in which a gate of a transistor is driven through a NOR element, a NAND
A CMOS output characterized in that an input signal is input to one input terminal of the element and the NOR element, and an input signal is input to the other input terminal of the NAND element and the NOR element via a delay circuit. Buffer circuit. 2. The delay circuit is composed of two CMOS transmission gates, an input signal is input to one input / output terminal of the first CMOS transmission gate, and the other input / output terminal is the other input of the NAND element. The output of the NAND element is input to the gate input terminal, the input signal is input to one input / output terminal of the second CMOS transmission gate, and the other input / output terminal is connected to the NOR element. Connect to the other input,
2. The CMOS output buffer circuit according to claim 1, wherein the gate input terminal is configured to input the output of the NOR element. 3. The CMOS transmission gate comprises P that constitutes the CMOS transmission gate.
3. The C according to claim 2, wherein one of the channel MOS transistor and the N-channel MOS transistor is configured to be operated in an ON state.
MOS output buffer circuit. 4. The NAND element and the NOR element are composed of multi-input elements, an input signal is input to one input terminal of each of the NAND element and the NOR element, and the other of the CMOS transmission gates is input to the remaining input terminal. The input and output terminals of are connected.
CMOS output buffer circuit described.