JP2001203328A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Problem] To provide a semiconductor integrated circuit capable of reducing the skew of a rising portion of a clock pulse without increasing the size of the circuit. SOLUTION: A plurality of buffers 11 to 13 are arranged and connected in a tree shape from the front end to the end. The input of the buffer 11 at the tip is connected to the output of the inverter 14,
On the other hand, the output of the terminal buffer 13 is connected to the input of the inverter 15. Each of the buffers 11 to 13 outputs the input pulse without inverting it. The clock signal is supplied to the input of the inverter 14, while the output of the inverter 15 is connected to the clock terminal CLK of the D-type flip-flop 16. The inverters 14 and 15 are
Inverts the input pulse and outputs it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit including a so-called clock tree circuit for branching an input clock signal into a plurality of clock signals for output. In particular, the present invention relates to a semiconductor integrated circuit that can reduce the skew at the rising edge of each pulse output from the clock tree circuit without increasing the size of the circuit.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit, a clock tree circuit is provided between a clock input and a plurality of flip-flops for branching an input clock signal into a plurality of clock signals and outputting the resulting signal. May be connected. Conventionally, a circuit as shown in FIG. 2 or 3 has been used as this type of circuit.

In FIG. 2, a plurality of buffer cells 1
01 to 104 are arranged and connected in a tree shape from the front end to the end. Each buffer cell outputs an input signal without inverting it. For the input of the buffer cell 101 at the tip,
A clock signal is provided. On the other hand, the output of the terminal buffer cell 104 is connected to the clock terminal CLK of the D-type flip-flop 105.

The leading buffer cell 101 outputs the input clock signal without inverting it, and
The signal is supplied to the next buffer cell 102 connected to 01.
Hereinafter, the buffer cells 102 to 104 also output the input clock signal without inverting it. Then, the clock signal output from the terminal buffer cell 104 is input to the clock terminal CLK of the D-type flip-flop 105.

The D flip-flop 105 has an input terminal D and an output terminal Q in addition to the clock terminal CLK.
The D-type flip-flop 105 holds the data input to the input terminal D at the rising edge of the clock pulse input to the clock terminal CLK, and outputs the data from the output terminal Q. That is, after the data input to the input terminal D is read at the rise of the clock pulse input to the clock terminal CLK of the D-type flip-flop 105, the clock pulse is kept at a low level, so that the data input to the input terminal D is maintained. Data can be stored (latched). Therefore, the timing of the rise of the clock pulse is very important.

On the other hand, in FIG. 3, an even number of inverter cells 201 to 204 are arranged and connected in a tree shape from the front end to the end. Each inverter cell inverts and outputs an input signal. A clock signal is supplied to an input of the leading inverter cell 201. On the other hand, the output of the terminal inverter cell 204 is a D-type flip-flop 1
05 is connected to the clock terminal CLK.

The leading inverter cell 201 inverts and outputs the input clock signal and supplies the inverted clock signal to the next inverter cell 202 connected to the inverter cell 201. Hereinafter, the inverter cells 202 to 204 also invert and output the input clock signal, and the terminal inverter cell 204 outputs a clock signal having the same phase as the clock signal input to the front inverter cell 201.
Then, the clock signal output from the terminal inverter cell 204 is input to the clock terminal CLK of the D-type flip-flop 105.

The buffer cells 101 to 104 and the inverter cells 201 to 204 are usually composed of complementary MOS.
(Hereinafter abbreviated as CMOS). As shown in FIG. 4, a circuit of a CMOS inverter cell is configured by complementarily connecting a P-channel transistor and an N-channel transistor which form a complementary pair. FIG. 4 is a circuit configuration diagram of a CMOS inverter cell.

In this inverter circuit, the gate electrodes of the P-channel transistor and the N-channel transistor are commonly connected to apply an input voltage V _IN , and the drain electrodes are commonly connected to extract an output voltage V _OUT . The source of the P-channel transistor is the power supply voltage V _DD on the high potential side.
Connected to. On the other hand, the source of the N-channel transistor is connected to the lower potential power supply voltage V _SS . Note that one of the power supply voltages V _DD and V _SS may be the ground potential. Also, C
A MOS buffer cell is usually configured by connecting two stages of inverter circuits in series.

[0010]

However, a parasitic capacitance (capacitance that does not appear as a circuit component in the circuit diagram) exists between the gate and the drain and between the gate and the source of each of these transistors. Input capacity. The greater the number of cells connected in parallel, the greater the effect of the input capacitance. In addition, a stray capacitance exists between a wiring between cells and the ground, and the like. Therefore, when the rising or falling portion of the pulse is input to each cell, skew (waveform distortion) occurs at the rising and falling portions of the pulse output from each cell due to charging and discharging of these capacitors.
Will occur. Here, since the N-channel transistor in the CMOS circuit has a higher driving capability (for example, two to three times) than the P-channel transistor, the skew of the pulse output from each cell is larger at the rising part than at the falling part.

Actually, in the clock tree circuits shown in FIGS. 2 and 3, a large skew is added every time the rising portion of the clock pulse is output from the buffer cells 101 to 104 and the inverter cells 201 to 204. Therefore, a large skew occurs at the rising portion of the clock pulse output from the terminal buffer cell 104 shown in FIG. Also, in the clock pulse output from the terminal inverter cell 204 shown in FIG. 3, the same skew occurs in the rising part and the falling part.

On the other hand, in order to reduce the skew of the clock pulse output from the terminal buffer cell 104 or the inverter cell 204, measures are taken to increase the area of the P-channel transistor constituting the CMOS and increase the drive capability of the P-channel transistor. Is also conceivable. However, this countermeasure has a disadvantage that the circuit is enlarged.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor integrated circuit capable of reducing the skew of a rising portion of a clock pulse without increasing the size of the circuit.

[0014]

In order to solve the above problems, in a semiconductor integrated circuit according to the present invention, an inverter cell and a buffer cell include a drain of a P-channel transistor and an N-channel transistor.
A semiconductor integrated circuit configured to obtain a complementary output from a drain of a channel transistor, comprising: a first inverter cell that inverts and outputs an input clock signal; A combination circuit of a buffer cell to be output, which receives a clock signal output from a first inverter cell, branches the clock signal into a plurality of clock signals, and outputs the plurality of clock signals. And at least one second inverter cell that receives at least one clock signal, inverts the clock signal, and outputs the inverted signal.

Here, the semiconductor device may further include at least one flip-flop that operates in synchronization with a rising edge of a pulse included in the clock signal output from the at least one second inverter cell. Further, the combination circuit may include a plurality of buffer cells connected in series by a wiring layer.

In the above-described semiconductor integrated circuit, the first inverter cell inverts and outputs an input clock signal. The signal output from the first inverter cell is transmitted and output without inversion through a combinational circuit configured by connecting a plurality of buffer cells. Then, the signal output from the combination circuit is supplied to the second inverter cell, and then inverted and output.

Here, the CMOS constituting the buffer cell
The N-channel transistor has higher driving capability than the P-channel transistor. Therefore, the skew at the rising portion of the clock pulse output from the second inverter cell can be reduced. In addition, since it is not necessary to increase the area of the P-channel transistor in order to increase the driving capability, the circuit does not increase in size. Furthermore, if the skew of the rising portion of the pulse output from the second inverter cell is the same as the conventional case, the number of the second inverter circuit cells immediately before the FF can be reduced, and the number of stages of the clock tree circuit can be reduced. Can be reduced as compared with the related art.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a part of a semiconductor integrated circuit according to one embodiment of the present invention. The semiconductor integrated circuit shown in FIG. 1 includes a clock tree circuit that branches a clock signal input to an input terminal into a plurality of clock signals and outputs the plurality of clock signals. In this circuit, for example, in order to drive a plurality of D-type flip-flops, a plurality of buffer cells 11 to 13 are combined to form a circuit network.

The buffer cells 11 to 13 are constituted by CMOS. The input of buffer cell 11 is connected to the output of inverter cell 14, while the output of buffer cell 13 is connected to the input of inverter cell 15. The buffer cells 11 to 13 output the input signals without inverting them.

The inverter cells 14 and 15 are composed of CMOS (see FIG. 4). A clock signal is supplied to the input of the inverter cell 14, while the output of the inverter cell 15 is connected to the clock terminal CLK of the D-type flip-flop 16. Inverter cell 1
5 and 16 invert the input signal and output it.

The inverter cell 14 inverts and outputs the input clock signal and supplies the inverted clock signal to the buffer cell 11. The buffer cell 11 outputs the input clock signal without inverting the clock signal and supplies the clock signal to the next buffer cell 12 connected to the buffer cell 11. Hereinafter, buffer cell 1
2 and 13 also output the input clock signal without inverting it. That is, the clock signal inverted by the inverter 14 is transmitted while being inverted between the buffer cells 11 to 13.

The clock signal output from the buffer cell 13 is supplied to the inverter cell 15. Inverter cell 15 inverts the input clock signal and outputs the inverted clock signal. The inverter cell 15 allows the buffer cell 11
Then, the clock signal transmitted while the signal between .about.13 is inverted is inverted again to return the same phase as the clock signal input to the clock tree circuit.

The D-type flip-flop 16 has an input terminal D and an output terminal Q in addition to the clock terminal CLK. D
The flip-flop 16 has an input terminal D at the rising edge of the clock pulse input to the clock terminal CLK.
, And outputs this from the output terminal Q. That is, at the rising edge of the clock pulse input to the clock terminal CLK of the D-type flip-flop 16, the data input to the input terminal D is read, and then the clock pulse is kept at a low level so that the input to the input terminal D is maintained. Data can be stored (latched).
Therefore, the timing of the rise of the clock pulse is very important.

According to this embodiment, the rising portion of the clock pulse input to the clock tree circuit is transmitted between the buffer cells 11 to 13 as the falling portion. Here, the N-channel transistor constituting the CMOS has higher driving ability than the P-channel transistor. Therefore, the falling portion of the clock pulse input to the buffer cell 11 is
Since the skew can be reduced during the transmission of the clock signal 3, the skew at the rising portion of the clock pulse inverted and output by the inverter cell 15 can be reduced. In addition, since it is not necessary to increase the area of the P-channel transistor in order to increase the driving capability, the circuit does not increase in size.

[0026]

As described above, according to the present invention,
The rising portion of the input clock pulse is inverted by the first inverter cell, and then transmitted between the plurality of connected buffer cells as a falling portion having a small skew, and further inverted by the second inverter to rise. Return to the part. Therefore, it is possible to reduce the skew at the rising portions of a plurality of clock pulses generated based on the input clock pulses. In addition, since it is not necessary to increase the area of the P-channel transistor in order to increase the driving capability, the circuit does not increase in size.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a part of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a part of a conventional semiconductor integrated circuit.

FIG. 3 is a circuit diagram showing a part of another conventional semiconductor integrated circuit.

FIG. 4 is a circuit diagram of a CMOS inverter cell.

[Explanation of symbols]

 11 to 13 buffer cells 14, 15 inverter cells 16 D-type flip-flop CLK clock terminal D input terminal Q output terminal

Claims (3)

[Claims] 1. An inverter cell and a buffer cell are P
A semiconductor integrated circuit configured to obtain a complementary output from a drain of a channel transistor and a drain of an N-channel transistor, comprising: a first inverter cell for inverting and outputting an input clock signal; Circuit for outputting a clock signal in phase with the clock signal output from the first inverter cell, branching the clock signal into a plurality of clock signals, and outputting the divided clock signal. And at least one second inverter cell that receives at least one clock signal output from the combinational circuit, and inverts and outputs the clock signal. 2. The semiconductor device according to claim 1, further comprising at least one flip-flop that operates in synchronization with a rising edge of a pulse included in a clock signal output from said at least one second inverter cell. Semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 1, wherein said combination circuit includes a plurality of buffer cells connected in series by a wiring layer.