JPH0264235U - - Google Patents
Info
- Publication number
- JPH0264235U JPH0264235U JP14297088U JP14297088U JPH0264235U JP H0264235 U JPH0264235 U JP H0264235U JP 14297088 U JP14297088 U JP 14297088U JP 14297088 U JP14297088 U JP 14297088U JP H0264235 U JPH0264235 U JP H0264235U
- Authority
- JP
- Japan
- Prior art keywords
- operating state
- signal
- input signal
- flop
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000630 rising effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Manipulation Of Pulses (AREA)
- Measurement Of Unknown Time Intervals (AREA)
Description
第１図は本考案に係るカウンタ計数用のクロツ
ク信号入力回路の一実施例を示す回路図、第２図
は第１図の回路図のタイムチヤート、第３図は本
考案に係るカウンタ計数用のクロツク信号入力回
路の他の実施例を示す回路図、第４図は従来例の
カウンタ計数用のクロツク信号入力回路の回路図
、第５図は第４図の従来例の回路図のタイムチヤ
ートである。
４……カウンタ、５……ＡＮＤゲート、６……
Ｄ型フリツプフロツプ、１２……ＪＫフリツプフ
ロツプ。
Fig. 1 is a circuit diagram showing an embodiment of the clock signal input circuit for counter counting according to the present invention, Fig. 2 is a time chart of the circuit diagram of Fig. 1, and Fig. 3 is a circuit diagram for counter counting according to the present invention. FIG. 4 is a circuit diagram of a conventional clock signal input circuit for counter counting, and FIG. 5 is a time chart of the conventional circuit diagram of FIG. 4. It is. 4...Counter, 5...AND gate, 6...
D-type flip-flop, 12...JK flip-flop.
Claims (1)
ツク入力信号に対するイネーブル信号により制御
され、前記動作状態のときに前記外部からのクロ
ツク入力信号の立ち上がりエツジを検出し、その
出力状態を変化させるフリツプフロツプと、 その入力側の一端に前記外部からのクロツク入
力信号を受け、その他端側に前記フリツプフロツ
プの出力を受けるゲート回路とからなるカウンタ
計数用のクロツク信号入力回路。[Claims for Utility Model Registration] Its operating state and non-operating state are controlled by an enable signal for an external clock input signal, and when it is in the operating state, it detects the rising edge of the external clock input signal. A clock signal input circuit for counter counting comprising a flip-flop that changes the output state, and a gate circuit that receives the clock input signal from the outside at one end of its input side and receives the output of the flip-flop at the other end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988142970U JPH087701Y2 (en) | 1988-10-31 | 1988-10-31 | Clock signal input circuit for counting counter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988142970U JPH087701Y2 (en) | 1988-10-31 | 1988-10-31 | Clock signal input circuit for counting counter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0264235U true JPH0264235U (en) | 1990-05-15 |
| JPH087701Y2 JPH087701Y2 (en) | 1996-03-04 |
Family
ID=31409371
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988142970U Expired - Lifetime JPH087701Y2 (en) | 1988-10-31 | 1988-10-31 | Clock signal input circuit for counting counter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH087701Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63131724A (en) * | 1986-11-21 | 1988-06-03 | Mitsubishi Electric Corp | Counter input gate circuit |
| JPH01190121A (en) * | 1988-01-26 | 1989-07-31 | Matsushita Electric Works Ltd | Reset synchronization delay circuit |
-
1988
- 1988-10-31 JP JP1988142970U patent/JPH087701Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63131724A (en) * | 1986-11-21 | 1988-06-03 | Mitsubishi Electric Corp | Counter input gate circuit |
| JPH01190121A (en) * | 1988-01-26 | 1989-07-31 | Matsushita Electric Works Ltd | Reset synchronization delay circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH087701Y2 (en) | 1996-03-04 |
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