JPH01190121A - Reset synchronization delay circuit - Google Patents

Abstract

PURPOSE:To obtain a pulse signal with a constant duty by using plural FFs using a system clock signal as a trigger, shifting a reset signal and outputting a signal synchronously with the clock signal as the final FF output. CONSTITUTION:A data at a data terminal D is set synchronously with the system clock signal VC fed to a trigger terminal T in FF, F1, F2. Thus, an output Q1 of the F1 goes to L, H when the reset signal Vr goes to L, H and the output Q2 of the F2 reaches L, H at the leading of the signal VC just after the output Q1 goes to L, H. Thus, the inverse of output Q2 of the F2 is coincident with the inverting point of time of the signal VC and the internal clock signal phi outputted via q gate G opened by the output Q2 is a signal having a delay time of a prescribed value at all times to the signal Vr and the pulse with a prescribed duty is obtained as a signal phi.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reset synchronization delay circuit that generates a reset pulse for power-on reset or system reset when power is turned on.

[Prior Art] Conventionally, this type of reset synchronization delay circuit that generates a reset pulse for performing a power-on reset or a system reset when the power is turned on is connected to inverters I, to I4 and a NAND circuit, as shown in FIG. When the reset signal Vr inputted from the outside becomes "H", the system clock signal Vc is made up of the internal clock signal φ,
It was supposed to be output as φ.

[Problems to be Solved by the Invention] However, in such a conventional example, the internal clock signal φ to be output, the delay time td of φ with respect to the reset signal Vr, and the first pulse depend on the rise timing of the reset signal Vr. There was a problem in that there were cases where the duty could not be secured. That is, as shown in FIG. 6(b), when the system clock signal Vc is "H"
``If the reset signal Vr rises during the period, a normal delay time td of a certain time or more is obtained, and
The duty of the first pulse is also normal internal clock signal φ
, φ are output, but as shown in FIG. 6(a),
“L” period reset signal V of system clock signal Vc
When r rises, the delay time cannot be obtained, and the duties of the first pulses of the output internal clock signals φ and φ are significantly different, and this internal clock signal φ
, φ is used to set the system operation timing, there is a problem in that the shifter or counter in the system may operate abnormally.

The present invention has been made in view of the above points, and its purpose is to output an internal clock signal that always has a delay time of a certain time or more with respect to a reset signal,
Moreover, it is an object of the present invention to provide a reset synchronization delay circuit that can obtain pulses with a constant duty from the beginning.

[Means for Solving the Problems] In order to achieve the above object, the present invention connects a plurality of flip-flops to which a system clock signal is applied to the terminals, and connects the output of the 707 flip-flops in the preceding stage to the output of the flip-flop in the succeeding stage. A system clock signal is input to the data terminal and connected in cascade, and a reset signal is applied to the data terminal of the first stage flip-flop, and the system clock signal output via the gate opened at the final stage flip-flop output is used as the internal clock signal. This is what I did.

[Function 1] As described above, the present invention shifts a reset signal using a plurality of flip-flops triggered by a system clock signal, and outputs a signal synchronized with the system clock signal ( This signal is used as a gate control signal to extract the system clock and obtain the internal clock.
An internal clock signal that always has a delay time longer than a certain time with respect to the reset signal is output, and a pulse signal with a constant duty from the first to the last pulse is obtained as the internal clock signal.

[Embodiment] FIG. 1 shows an embodiment of the present invention, in which the system clock signal Vc is applied to the terminal T of two flip-flops F, , F, and the output of the previous flip-flop F. Q, is input to the data terminal of the subsequent flip-flop F2 and connected in cascade.
At the same time, a reset signal Vr is applied to the data terminal 1, and a system clock signal Vc outputted through a gate G consisting of a NOR circuit opened at the final stage 70-tube F2 output Q2 is used as the internal clock signal φ. This is what I did. In the embodiment, the power-on signal Pon indicating power-on and the reset signal Vr are NOR-operated by the NOR circuit NO2 to generate the flip-flop F.

The power-on signal Pon is input to the set terminal S of the flip-flop F2.

The operation of the embodiment will be described below. Now, the operating waveforms of each part are as shown in FIG. The output Q of the flip-flop F1 goes low at the rising time t2 of the system clock signal Vc immediately after the reset signal ■ becomes low at the time t. When the reset signal Vr becomes H'', it becomes H''. On the other hand, the output Q2 of the flip-flop F2 in the subsequent stage becomes "L"' at the rising edge of the system clock signal Vc immediately after the output Q of the flip-flop F becomes "L", and the output Q2 of the flip-flop F2 becomes "L"'. , becomes H'' at the rising edge of the system clock signal Vc immediately after the output Q-, of
''. Therefore, the output Q of flip-flop F2
The inversion of 2 coincides with the inversion point (rising edge in this embodiment) of the system clock signal VC, and the internal clock signal φ outputted via the gate G opened by the flip-flop F2 output Q2 is equal to the reset signal Vr. The signal always has a delay time longer than a certain time (at least 3/2 period of the system clock signal Vc) relative to the internal clock signal φ, and a pulse with a constant density from the beginning to the end is obtained as the internal clock signal φ. In other words, in the present invention, the reset signal Vr is shifted using a plurality of 79x70x F, , F2 triggered by the system clock signal Ve, and the final stage flip-flop F2 output Q2 left A signal synchronized with the system clock signal Vc (the inversion time coincides) is obtained, and this signal is used as a gate control signal to control the system clock signal Vc.
Since the internal clock signal - is obtained by extracting the internal clock signal φ, an internal clock signal φ that always has a delay time longer than a certain time with respect to the reset signal Vr is output. This results in a pulse signal of . Therefore, an internal clock signal φ is obtained that allows the shifters and counters in the system to always operate normally.

FIG. 3 shows a flip-flop F in the above embodiment.

are added to form three flip-flops F, , F2 . F.

4 is an explanatory diagram of the operation.
The off-delay and on-delay can be shifted by one pulse of the system clock signal, and if a multi-stage configuration is used, the off-delay and on-delay can be set arbitrarily.

[Effects of the Invention] The present invention is configured as described above, and a reset signal is shifted using a plurality of flip-flops triggered by a system clock signal, and the system clock signal is output as the final stage flip-flop output. A signal synchronized with (the inversion point coincides) is obtained, and this signal is used as a gate control signal to extract the system clock to obtain the internal clock, so the internal clock always has a delay time of a certain amount of time or more with respect to the reset signal. This has the effect that a signal is output, and a pulse signal with a constant duty from the first to the last pulse can be obtained as an internal clock signal.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of one embodiment of the present invention, Fig. 2 is an explanatory diagram of the same operation as above, Fig. 3 is a circuit diagram of another embodiment, Fig. 4 is an explanatory diagram of the same as the above, and Fig. 5 is a conventional diagram. An example circuit diagram, FIG. 6, is an explanatory diagram of the same operation as above. F l* F z huff 'J 7' 71:l ”
p 7', Tl: 1lJ7y4 child, D is data terminal, S
is a set terminal, Q, , Q is an output, and G is a gate. Agent Patent Attorney Mr. Ishi 1) Figure 7 5 φoka Figure 6 A April 16, 1986

Claims (1)

[Claims] (1) Multiple flip-flops to which a system clock signal is applied to the trigger terminal are connected in cascade by inputting the output of the previous flip-flop to the data terminal of the subsequent flip-flop, and a reset signal is sent to the data terminal of the first flip-flop. 1. A reset synchronization delay circuit characterized in that an internal clock signal is a system clock signal outputted through a gate opened at the output of a final stage flop-flop.