JPS62158932U - - Google Patents
Info
- Publication number
- JPS62158932U JPS62158932U JP4699486U JP4699486U JPS62158932U JP S62158932 U JPS62158932 U JP S62158932U JP 4699486 U JP4699486 U JP 4699486U JP 4699486 U JP4699486 U JP 4699486U JP S62158932 U JPS62158932 U JP S62158932U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- outputs
- analog switch
- gate
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000630 rising effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
Description
第１図はこの考案の一実施例を示すブロツク回
路図、第２図はそのタイミングチヤートである。
図中、１…第１のワンシヨツト回路、２…Ｄ―
フリツプフロツプ、３…第２のワンシヨツト回路
、４…アナログスイツチ。
FIG. 1 is a block circuit diagram showing an embodiment of this invention, and FIG. 2 is a timing chart thereof. In the figure, 1...first one-shot circuit, 2...D-
Flip-flop, 3...second one-shot circuit, 4...analog switch.
Claims (1)
対応してパルス幅が正規信号のパルス幅より短い
負の基準パルスを出力する第１のワンシヨツト回
路と、 上記基準パルスをクロツク信号とし、その立上
がり時の入力信号の状態を保持して出力し、下記
アナログスイツチの出力をクリア信号とするＤ―
フリツプフロツプと、 上記Ｄ―フリツプフロツプの出力に基づいて入
力の正規信号のパルスに対応する所定時間下記ア
ナログスイツチのゲートをＯＮするためのゲート
制御信号を出力する第２のワンシヨツト回路と、 上記ゲート制御信号によつて上記の所定期間ゲ
ートがＯＮされているときに入力信号を通過させ
るアナログスイツチと、 よりなるＰＬＬのノイズカツト回路。[Claims for Utility Model Registration] A first one-shot circuit that outputs a negative reference pulse whose pulse width is shorter than the pulse width of the normal signal in response to the rise of an input signal that includes noise in the normal signal; D-- which uses the clock signal as a clock signal, maintains the state of the input signal at the rising edge and outputs it, and uses the output of the analog switch below as a clear signal.
a flip-flop; a second one-shot circuit that outputs a gate control signal for turning on the gate of the analog switch described below for a predetermined time corresponding to a pulse of the input regular signal based on the output of the D-flip-flop; and the gate control signal A PLL noise cut circuit comprising: an analog switch that allows an input signal to pass when the gate is turned on for a predetermined period; and a PLL noise cut circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986046994U JPH0445296Y2 (en) | 1986-03-28 | 1986-03-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986046994U JPH0445296Y2 (en) | 1986-03-28 | 1986-03-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62158932U true JPS62158932U (en) | 1987-10-08 |
| JPH0445296Y2 JPH0445296Y2 (en) | 1992-10-26 |
Family
ID=30867175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986046994U Expired JPH0445296Y2 (en) | 1986-03-28 | 1986-03-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0445296Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5167056A (en) * | 1974-12-09 | 1976-06-10 | Fujitsu Ltd | |
| JPS5670572U (en) * | 1979-08-09 | 1981-06-10 |
-
1986
- 1986-03-28 JP JP1986046994U patent/JPH0445296Y2/ja not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5167056A (en) * | 1974-12-09 | 1976-06-10 | Fujitsu Ltd | |
| JPS5670572U (en) * | 1979-08-09 | 1981-06-10 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0445296Y2 (en) | 1992-10-26 |
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