JPH0310639U - - Google Patents
Info
- Publication number
- JPH0310639U JPH0310639U JP7158489U JP7158489U JPH0310639U JP H0310639 U JPH0310639 U JP H0310639U JP 7158489 U JP7158489 U JP 7158489U JP 7158489 U JP7158489 U JP 7158489U JP H0310639 U JPH0310639 U JP H0310639U
- Authority
- JP
- Japan
- Prior art keywords
- input
- flop
- flip
- clock
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000630 rising effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Tests Of Electronic Circuits (AREA)
- Manipulation Of Pulses (AREA)
- Dc Digital Transmission (AREA)
Description
第１図は本考案に係るデータのフオーマツト切
り替え回路の一実施例を示す構成図、第２図はそ
の動作を説明するための波形図、第３図は従来の
データのフオーマツト切り替え回路の構成図、第
４図はその動作を説明する為の波形図である。
１０……第１のフリツプフロツプ、１１，１３
……デイレイライン、１２……ＡＮＤゲート、１
４……第２のフリツプフロツプ。
Fig. 1 is a block diagram showing an embodiment of the data format switching circuit according to the present invention, Fig. 2 is a waveform diagram for explaining its operation, and Fig. 3 is a block diagram of a conventional data format switching circuit. , FIG. 4 is a waveform diagram for explaining the operation. 10...first flip-flop, 11, 13
...Delay line, 12...AND gate, 1
4...Second flip-flop.
Claims (1)
端子に入力され、クロツクの立ち上がりエツジ信
号がそのクロツク端子に入力される第１のフリツ
プフロツプと、 フオーマツトの選択信号とクロツクの立ち下が
りエツジ信号が入力されるゲートと、 このゲートの出力がそのクロツク端子に入力さ
れ、前記第１のフリツプフロツプの出力がそのリ
セツト端子に入力される第２のフリツプフロツプ
とを有し、 この第２のフリツプフロツプの出力を前記第１
のフリツプフロツプのリセツト端子に入力するよ
うにしたことを特徴とするデータのフオーマツト
切り替え回路。[Claims for Utility Model Registration] A first flip-flop to which data whose format is to be converted is input to its data terminal and a rising edge signal of a clock is input to its clock terminal; a format selection signal and a falling edge of the clock; The second flip-flop has a gate to which an edge signal is input, and a second flip-flop to which the output of the gate is input to its clock terminal and the output of the first flip-flop is input to its reset terminal. The output of the first
A data format switching circuit characterized in that the data is input to a reset terminal of a flip-flop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7158489U JPH0310639U (en) | 1989-06-19 | 1989-06-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7158489U JPH0310639U (en) | 1989-06-19 | 1989-06-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0310639U true JPH0310639U (en) | 1991-01-31 |
Family
ID=31608748
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7158489U Pending JPH0310639U (en) | 1989-06-19 | 1989-06-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0310639U (en) |
-
1989
- 1989-06-19 JP JP7158489U patent/JPH0310639U/ja active Pending
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