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JPS60119138U - Pulse generation circuit - Google Patents

Pulse generation circuit

Info

Publication number
JPS60119138U
JPS60119138U JP1984005896U JP589684U JPS60119138U JP S60119138 U JPS60119138 U JP S60119138U JP 1984005896 U JP1984005896 U JP 1984005896U JP 589684 U JP589684 U JP 589684U JP S60119138 U JPS60119138 U JP S60119138U
Authority
JP
Japan
Prior art keywords
generation circuit
flop
flip
pulse generation
delay line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984005896U
Other languages
Japanese (ja)
Inventor
楠本 一秀
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP1984005896U priority Critical patent/JPS60119138U/en
Publication of JPS60119138U publication Critical patent/JPS60119138U/en
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の微小パルス幅発生回路のブロック回路図
、第2図はこの考案の一実施例による微小パルス幅発生
回路のブロック回路図、第3図は第2図のタイミング図
である。 6・・・フリップ・フロップ、8・・・遅延線。なお、
図中、同一符号は同−又は相当部分を示す。
FIG. 1 is a block circuit diagram of a conventional minute pulse width generation circuit, FIG. 2 is a block circuit diagram of a minute pulse width generation circuit according to an embodiment of this invention, and FIG. 3 is a timing diagram of FIG. 2. 6...Flip-flop, 8...Delay line. In addition,
In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力パルス信号の入力タイミングでセットされるフリッ
プ・フロップと、このフリップ・フロップの出力を所定
時間の間遅延させる遅延線とによって構成され、この遅
延線出力によって上記フリップ・フロップをリセットす
ることにより、上記遅延線の遅延時間に等しいパルス幅
のパルスを発生出力することを特徴とするパルス発生回
路。
It consists of a flip-flop that is set at the input timing of an input pulse signal and a delay line that delays the output of this flip-flop for a predetermined period of time, and by resetting the flip-flop with the output of this delay line, A pulse generating circuit characterized in that it generates and outputs a pulse having a pulse width equal to the delay time of the delay line.
JP1984005896U 1984-01-19 1984-01-19 Pulse generation circuit Pending JPS60119138U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984005896U JPS60119138U (en) 1984-01-19 1984-01-19 Pulse generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984005896U JPS60119138U (en) 1984-01-19 1984-01-19 Pulse generation circuit

Publications (1)

Publication Number Publication Date
JPS60119138U true JPS60119138U (en) 1985-08-12

Family

ID=30482834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984005896U Pending JPS60119138U (en) 1984-01-19 1984-01-19 Pulse generation circuit

Country Status (1)

Country Link
JP (1) JPS60119138U (en)

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