JPS62203521U - - Google Patents
Info
- Publication number
- JPS62203521U JPS62203521U JP9184286U JP9184286U JPS62203521U JP S62203521 U JPS62203521 U JP S62203521U JP 9184286 U JP9184286 U JP 9184286U JP 9184286 U JP9184286 U JP 9184286U JP S62203521 U JPS62203521 U JP S62203521U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- flip
- outputs
- flop
- logic gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案によるデジタルフイルタ回路の
一実施例の回路構成図、第２図は第１図に示す回
路の動作を説明するタイミングチヤート、第３図
は本考案の他の実施例の回路構成図、第４図は従
来のデジタルフイルタ回路の回路構成図、第５図
は第４図に示す回路の動作を説明するためのタイ
ミングチヤートである。
図面中、１は第１のフリツプフロツプ回路、２
は第２のフリツプフロツプ回路、３は第１のアン
ド回路、４は第２のアンド回路、５は第３のフリ
ツプフロツプ回路、６は第１のフリツプフロツプ
回路、７は第２のフリツプフロツプ回路、８は第
１のノア回路、９は第２のノア回路、１０，１１
はノア回路、１２は入力信号、１３はクロツクパ
ルス、１４は正出力である。
FIG. 1 is a circuit configuration diagram of one embodiment of a digital filter circuit according to the present invention, FIG. 2 is a timing chart explaining the operation of the circuit shown in FIG. 1, and FIG. 3 is a circuit diagram of another embodiment of the present invention. FIG. 4 is a circuit diagram of a conventional digital filter circuit, and FIG. 5 is a timing chart for explaining the operation of the circuit shown in FIG. In the drawing, 1 is a first flip-flop circuit; 2 is a first flip-flop circuit;
is the second flip-flop circuit, 3 is the first AND circuit, 4 is the second AND circuit, 5 is the third flip-flop circuit, 6 is the first flip-flop circuit, 7 is the second flip-flop circuit, and 8 is the third flip-flop circuit. 1 is the NOR circuit, 9 is the second NOR circuit, 10, 11
12 is an input signal, 13 is a clock pulse, and 14 is a positive output.
Claims (1)
り込む第１のフリツプフロツプ回路と、第１のフ
リツプフロツプ回路の出力を前記クロツクパルス
により取り込む第２のフリツプフロツプ回路と、
第１及び第２のフリツプフロツプ回路の正出力の
論理積信号を出力する第１の論理ゲート回路と、
第１及び第２のフリツプフロツプ回路の反転出力
の論理積信号を出力する第２の論理ゲート回路と
、上記第１及び第２の論理ゲート回路の出力によ
つてセツト及びリセツトされる第３のフリツプフ
ロツプ回路とからなることを特徴とするデジタル
フイルタ回路。 a first flip-flop circuit that receives a digital input signal using a clock pulse; a second flip-flop circuit that receives an output of the first flip-flop circuit using the clock pulse;
a first logic gate circuit that outputs an AND signal of the positive outputs of the first and second flip-flop circuits;
a second logic gate circuit that outputs an AND signal of the inverted outputs of the first and second flip-flop circuits; and a third flip-flop circuit that is set and reset by the outputs of the first and second logic gate circuits. A digital filter circuit characterized by comprising a circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9184286U JPS62203521U (en) | 1986-06-18 | 1986-06-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9184286U JPS62203521U (en) | 1986-06-18 | 1986-06-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62203521U true JPS62203521U (en) | 1987-12-25 |
Family
ID=30952993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9184286U Pending JPS62203521U (en) | 1986-06-18 | 1986-06-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62203521U (en) |
-
1986
- 1986-06-18 JP JP9184286U patent/JPS62203521U/ja active Pending
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