JPS63185319U - - Google Patents
Info
- Publication number
- JPS63185319U JPS63185319U JP7589687U JP7589687U JPS63185319U JP S63185319 U JPS63185319 U JP S63185319U JP 7589687 U JP7589687 U JP 7589687U JP 7589687 U JP7589687 U JP 7589687U JP S63185319 U JPS63185319 U JP S63185319U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- pulse width
- data latch
- gate circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
- Dc Digital Transmission (AREA)
- Selective Calling Equipment (AREA)
Description
第１図は本考案の実施例を示す回路図、第２図
は第１図に示された回路の動作を示すタイミング
図、第３図は従来例を示す回路図、第４図は第３
図の動作を示すタイミング図である。
４……入力端子、５……データラツチ回路、６
……ゲート回路、８……パルス幅弁別回路。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the circuit shown in FIG. 1, FIG. 3 is a circuit diagram showing a conventional example, and FIG.
FIG. 3 is a timing chart showing the operation shown in FIG. 4...Input terminal, 5...Data latch circuit, 6
...Gate circuit, 8...Pulse width discrimination circuit.
Claims (1)
記入力信号とその反転信号を前記データラツチ回
路の出力信号により切換出力するゲート回路と、
該ゲート回路の出力の信号変化に基いて基準クロ
ツクパルスを計数し前記ゲート回路のパルス幅が
所定のパルス幅以上のとき前記データラツチ回路
にラツチパルスを印加するパルス幅弁別回路とを
備え、前記入力信号に混入するノイズを除去する
ことを特徴とする信号入力回路。 a data latch circuit to which an input signal is applied; a gate circuit that switches and outputs the input signal and its inverted signal according to the output signal of the data latch circuit;
a pulse width discrimination circuit that counts reference clock pulses based on signal changes in the output of the gate circuit and applies a latch pulse to the data latch circuit when the pulse width of the gate circuit is equal to or greater than a predetermined pulse width; A signal input circuit characterized by removing mixed noise.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7589687U JPS63185319U (en) | 1987-05-20 | 1987-05-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7589687U JPS63185319U (en) | 1987-05-20 | 1987-05-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63185319U true JPS63185319U (en) | 1988-11-29 |
Family
ID=30922466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7589687U Pending JPS63185319U (en) | 1987-05-20 | 1987-05-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63185319U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0746125A (en) * | 1993-07-28 | 1995-02-14 | Nec Corp | Pll circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58100533A (en) * | 1981-12-10 | 1983-06-15 | Fujitsu Ltd | Anti-chattering circuit |
-
1987
- 1987-05-20 JP JP7589687U patent/JPS63185319U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58100533A (en) * | 1981-12-10 | 1983-06-15 | Fujitsu Ltd | Anti-chattering circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0746125A (en) * | 1993-07-28 | 1995-02-14 | Nec Corp | Pll circuit |
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