[go: up one dir, main page]

JP5972324B2 - 基板処理装置及び基板処理方法 - Google Patents

基板処理装置及び基板処理方法 Download PDF

Info

Publication number
JP5972324B2
JP5972324B2 JP2014164897A JP2014164897A JP5972324B2 JP 5972324 B2 JP5972324 B2 JP 5972324B2 JP 2014164897 A JP2014164897 A JP 2014164897A JP 2014164897 A JP2014164897 A JP 2014164897A JP 5972324 B2 JP5972324 B2 JP 5972324B2
Authority
JP
Japan
Prior art keywords
gas
substrate
process gas
substrate processing
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2014164897A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016034009A (ja
Inventor
ピョンソー シン
ピョンソー シン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PSK Inc
Original Assignee
PSK Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PSK Inc filed Critical PSK Inc
Publication of JP2016034009A publication Critical patent/JP2016034009A/ja
Application granted granted Critical
Publication of JP5972324B2 publication Critical patent/JP5972324B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • H01L21/02507Alternating layers, e.g. superlattice
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/016Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including vertical IGFETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP2014164897A 2014-07-30 2014-08-13 基板処理装置及び基板処理方法 Active JP5972324B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2014-0097244 2014-07-30
KR1020140097244A KR101603971B1 (ko) 2014-07-30 2014-07-30 기판 처리 장치 및 기판 처리 방법

Publications (2)

Publication Number Publication Date
JP2016034009A JP2016034009A (ja) 2016-03-10
JP5972324B2 true JP5972324B2 (ja) 2016-08-17

Family

ID=55248970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014164897A Active JP5972324B2 (ja) 2014-07-30 2014-08-13 基板処理装置及び基板処理方法

Country Status (4)

Country Link
JP (1) JP5972324B2 (zh)
KR (1) KR101603971B1 (zh)
CN (1) CN105321846B (zh)
TW (1) TWI559398B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111115561B (zh) * 2019-12-05 2023-05-12 中国科学院微电子研究所 一种微纳通孔的制备方法及具有微纳通孔的结构
KR102540773B1 (ko) * 2021-01-19 2023-06-12 피에스케이 주식회사 패러데이 실드 및 기판 처리 장치

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0793366B2 (ja) * 1984-10-08 1995-10-09 日本電信電話株式会社 半導体メモリおよびその製造方法
US5413670A (en) * 1993-07-08 1995-05-09 Air Products And Chemicals, Inc. Method for plasma etching or cleaning with diluted NF3
US6296780B1 (en) * 1997-12-08 2001-10-02 Applied Materials Inc. System and method for etching organic anti-reflective coating from a substrate
KR100558922B1 (ko) * 2004-12-16 2006-03-10 (주)퓨전에이드 박막 증착장치 및 방법
KR100807223B1 (ko) * 2006-07-12 2008-02-28 삼성전자주식회사 상변화 물질층, 상변화 물질층 형성 방법 및 이를 이용한상변화 메모리 장치의 제조 방법
JP2010177652A (ja) * 2009-02-02 2010-08-12 Toshiba Corp 半導体装置の製造方法
KR101573697B1 (ko) * 2009-02-11 2015-12-02 삼성전자주식회사 수직 폴딩 구조의 비휘발성 메모리 소자 및 그 제조 방법
KR101603731B1 (ko) * 2009-09-29 2016-03-16 삼성전자주식회사 버티칼 낸드 전하 트랩 플래시 메모리 디바이스 및 제조방법
US9536970B2 (en) * 2010-03-26 2017-01-03 Samsung Electronics Co., Ltd. Three-dimensional semiconductor memory devices and methods of fabricating the same
KR101209003B1 (ko) * 2010-10-14 2012-12-06 주식회사 유진테크 3차원 구조의 메모리 소자를 제조하는 방법 및 장치
US9318341B2 (en) * 2010-12-20 2016-04-19 Applied Materials, Inc. Methods for etching a substrate
KR102010928B1 (ko) * 2012-06-07 2019-10-21 삼성전자주식회사 저항 변화 메모리 장치, 그 동작 방법 및 제조 방법
TWI496249B (zh) * 2013-01-09 2015-08-11 Macronix Int Co Ltd 三維反及快閃記憶體

Also Published As

Publication number Publication date
CN105321846A (zh) 2016-02-10
KR20160015454A (ko) 2016-02-15
JP2016034009A (ja) 2016-03-10
KR101603971B1 (ko) 2016-03-17
CN105321846B (zh) 2018-02-06
TWI559398B (zh) 2016-11-21
TW201604952A (zh) 2016-02-01

Similar Documents

Publication Publication Date Title
US8119530B2 (en) Pattern forming method and semiconductor device manufacturing method
KR101250057B1 (ko) 절연막의 플라즈마 개질 처리 방법 및 플라즈마 처리 장치
CN110809817B (zh) 蚀刻方法和蚀刻装置
US20170356084A1 (en) Processing method of silicon nitride film and forming method of silicon nitride film
US11631591B2 (en) Methods for depositing dielectric material
KR20110056551A (ko) 플라즈마 cvd 방법, 질화 규소막의 형성 방법 및 반도체 장치의 제조 방법
CN110890263A (zh) 干法清洗设备和干法清洗方法
KR101276258B1 (ko) 반도체 제조 장치 및 반도체 제조 방법
JP2022100339A (ja) 基板処理装置及び基板処理方法
US7910495B2 (en) Plasma oxidizing method, plasma processing apparatus, and storage medium
KR20100129311A (ko) 질화규소막의 제조 방법, 질화규소막 적층체의 제조 방법, 컴퓨터 판독 가능한 기억 매체, 및 플라즈마 cvd 장치
US20150064921A1 (en) Low temperature plasma anneal process for sublimative etch processes
JP5460011B2 (ja) 窒化珪素膜の成膜方法、コンピュータ読み取り可能な記憶媒体およびプラズマcvd装置
JP5972324B2 (ja) 基板処理装置及び基板処理方法
US20110254078A1 (en) Method for depositing silicon nitride film, computer-readable storage medium, and plasma cvd device
KR20160113410A (ko) 기판 처리 장치 및 기판 처리 방법
US10580658B2 (en) Method for preferential oxidation of silicon in substrates containing silicon and germanium
KR102052337B1 (ko) 기판 처리 장치 및 기판 처리 방법
KR101909110B1 (ko) 기판 처리 방법
JP7220603B2 (ja) 膜をエッチングする方法及びプラズマ処理装置
KR102095982B1 (ko) 기판 처리 장치 및 기판 처리 방법
KR20150110948A (ko) 기판 처리 장치 및 챔버 제조 방법
KR102581739B1 (ko) 기판 처리 방법 및 기판 처리 장치
JP2009267391A (ja) 窒化珪素膜の製造方法、窒化珪素膜積層体の製造方法、コンピュータ読み取り可能な記憶媒体およびプラズマcvd装置
JP2016039355A (ja) 基板処理装置及び基板処理方法

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160223

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160520

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20160621

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20160712

R150 Certificate of patent or registration of utility model

Ref document number: 5972324

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250