JP5155644B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5155644B2 JP5155644B2 JP2007316920A JP2007316920A JP5155644B2 JP 5155644 B2 JP5155644 B2 JP 5155644B2 JP 2007316920 A JP2007316920 A JP 2007316920A JP 2007316920 A JP2007316920 A JP 2007316920A JP 5155644 B2 JP5155644 B2 JP 5155644B2
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Description
図1は本発明の実施の形態の半導体装置の構造の一例を示す平面図、図2は図1のA−A線に沿って切断した構造の一例を示す断面図、図3は図1のB−B線に沿って切断した構造の一例を示す断面図、図4は図1に示す半導体装置の組み立てにおけるワイヤボンディング完了までの製造プロセスの一例を示す断面図、図5は図1に示す半導体装置の組み立てにおけるワイヤボンディング後の製造プロセスの一例を示す断面図である。また、図6Aは図1に示す半導体装置の組み立てに用いられるリードフレームの構造の一例を示す部分平面図、図6Bは図6Aに示す半導体装置の組み立てに用いられるリードフレームの一部を示す部分拡大平面図、図7は図1に示す半導体装置の組み立てに用いられるリードフレームの第2オフセット部の構造の一例を示す部分平面図、図8は図7のA−A線に沿って切断した構造の一例を示す断面図である。さらに、図9は図1に示す半導体装置の組み立てにおけるワイヤボンディング時のクランプ領域の一例を示す平面図、図10は図1に示す半導体装置の組み立てにおけるワイヤボンディング時のクランプ構造の一例を示す断面図、図11は図1に示す半導体装置の組み立てにおける樹脂モールディング後の構造の一例を封止体を透過して示す部分平面図である。
る。これによって、ワイヤ流れ、タブ1cの変形、ボイドの発生等を防ぐことができる。
ても封止用樹脂と大タブ1uとの界面において生じる剥離の問題を抑制するものである。
チップ2のパッド2aとインナリード1aと接続されるワイヤ4の本数を省略している。
1a インナリード(リード)
1b アウタリード(リード)
1c タブ(チップ搭載部)
1d チップ支持面
1e 吊りリード
1f バーリード(共通リード)
1f' めっき膜(めっき層)
1g 第1スリット
1h 第1インナリード
1i 第2インナリード
1j 第1連結部
1m 第1オフセット部
1n 第2スリット
1p 第2オフセット部
1q テープ材
1r 第2連結部
1s 第3スリット
1t 蛇行部
1u 大タブ(チップ搭載部)
1v 貫通孔
1w 迫り出し部(共通リード)
2 半導体チップ
2a 主面
2b 裏面
2c パッド(電極)
3 封止体
4 ワイヤ
4a 第1のワイヤ
4b 第2のワイヤ
5 銀ペースト
6 QFP(半導体装置)
7 ポッティングノズル
8 吸着コレット
9 キャピラリ
10 ボンディングステージ
10a 吸着孔
11 クランパ
11a クランプ部
12 外装めっき
13 QFP(半導体装置)
14 モールド金型
14a 上型
14b キャビティ面
14c 下型
14d キャビティ面
15 QFN(半導体装置)
16 SOP(半導体装置)
17 SON(半導体装置)
18 QFN(半導体装置)
19 SON(半導体装置)
Claims (5)
- チップ搭載部と、
主面、前記主面に形成された第1電極、前記主面に形成された第2電極、および前記主面とは反対側の裏面を有し、前記チップ搭載部に搭載された半導体チップと、
前記チップ搭載部を支持する複数の吊りリードと、
平面視において、前記チップ搭載部の周囲に配置された複数の共通リードと、
平面視において、前記チップ搭載部の周囲に配置された複数のリードと、
前記複数の第1電極と前記複数の共通リードとをそれぞれ電気的に接続する複数の第1ワイヤと、
前記複数の第2電極と前記複数のリードとをそれぞれ電気的に接続する複数の第2ワイヤと、
前記半導体チップ、前記複数の第1ワイヤおよび前記複数の第2ワイヤを封止する封止体と、
を含み、
前記チップ搭載部、前記複数の吊りリード、前記複数の共通リードおよび前記複数のリードは、銅を主成分とする金属から成り、
前記複数の共通リードのそれぞれは、平面視において、前記複数の吊りリードのうちの互いに隣り合う吊りリード間に配置され、
前記複数の共通リードのそれぞれは、平面視において、前記チップ搭載部と前記複数のリードとの間に配置され、
前記複数の共通リードのそれぞれは、前記複数の吊りリードのそれぞれの第1部分に連結され、
前記複数の吊りリードのそれぞれの前記第1部分には、スリットが形成されており、
前記複数の共通リードのそれぞれは、直線状に形成され、
前記複数の吊りリードのそれぞれの前記第1部分に形成され、かつ前記複数の共通リードのそれぞれには形成されない前記スリットは、前記複数の共通リードのそれぞれの延長線上に位置していることを特徴とする半導体装置。 - 請求項1において、
前記チップ搭載部の平面視における外形寸法は、前記半導体チップの平面視における外形寸法よりも小さいことを特徴とする半導体装置。 - 請求項2において、
前記複数の吊りリードのそれぞれは、前記第1部分よりも前記チップ搭載部に近い第2部分に形成された第1オフセット部を有していることを特徴とする半導体装置。 - 請求項2において、
前記複数の共通リードのうちの第1共通リードは、前記複数のリードのうちの第1リードと繋がっていることを特徴とする半導体装置。 - 請求項4において、
前記複数の共通リードのうちの第2共通リードは、前記複数のリードと繋がっていなく、
前記第2共通リードは、第2オフセット部を有していることを特徴とする半導体装置。
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