JP5798021B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5798021B2 JP5798021B2 JP2011263744A JP2011263744A JP5798021B2 JP 5798021 B2 JP5798021 B2 JP 5798021B2 JP 2011263744 A JP2011263744 A JP 2011263744A JP 2011263744 A JP2011263744 A JP 2011263744A JP 5798021 B2 JP5798021 B2 JP 5798021B2
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- 239000004065 semiconductor Substances 0.000 title claims description 99
- 238000007789 sealing Methods 0.000 claims description 74
- 239000000725 suspension Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 11
- 229920005989 resin Polymers 0.000 description 15
- 239000011347 resin Substances 0.000 description 15
- 238000012986 modification Methods 0.000 description 14
- 230000004048 modification Effects 0.000 description 14
- 238000000034 method Methods 0.000 description 12
- 230000002093 peripheral effect Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- 238000000465 moulding Methods 0.000 description 6
- 239000012466 permeate Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004873 anchoring Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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Description
図1は本発明の実施の形態1の半導体装置の構造の一例を示す平面図、図2は図1の半導体装置の構造を封止体を透過して示す平面図、図3は図1の半導体装置の構造の一例を示す裏面図、図4は図1の半導体装置の構造の一例を示す側面図、図5は図2のA−A線に沿って切断した構造の一例を示す断面図である。また、図6は図2のW部の構造を示す拡大部分平面図、図7は図6のC−C線に沿って切断した構造の一例を示す断面図、図8は図6のD−D線に沿って切断した構造の一例を示す断面図、図9は図6のE−E線に沿って切断した構造の一例を示す断面図、図10は図6のF−F線に沿って切断した構造の一例を示す断面図である。
図26は本発明の実施の形態2の半導体装置の構造の一例を封止体を透過して示す平面図である。
1a 表面(主面)
1b 裏面
1c 電極パッド
2 リードフレーム
2a リード
2aa 上面
2ab 下面
2b アウター部
2c,2ca 吊りリード
2d ダイパッド
2da 上面
2db 下面
2e インナー部
2f 外側端面
2g 内側端面
2h,2i 側面
2j 中央リード
2k 先端部
2m 後端部
2n,2p,2q 段差部
2r 迫り出し面
2s デバイス領域
2t 枠部
2u 幅広部
2v ワイヤ接合部
2w 延在方向
3 ワイヤ
4 封止体
4a 側面
4b 下面
4c 一括封止体
5 QFN(半導体装置)
6 ダイボンド材
7 中心線
8 延在方向
9 ブレード
10 ダイシングテープ
11 QFN(半導体装置)
Claims (10)
- ダイパッドと、
前記ダイパッドを支持する複数の吊りリードと、
前記複数の吊りリードの間に配置された複数のリードと、
主面、前記主面に形成された複数の電極パッド、および前記主面とは反対側の裏面を有し、かつ前記ダイパッドの上面に搭載された半導体チップと、
前記半導体チップの前記複数の電極パッドと前記複数のリードとをそれぞれ電気的に接続する複数のワイヤと、
前記複数のリードのそれぞれの下面が露出するように、前記半導体チップおよび前記複数のワイヤを封止する封止体と、
を含み、
前記複数のリードのそれぞれは、前記封止体から露出する前記下面と、前記下面とは反対側の上面と、前記上面と前記下面との間に位置し、かつ、前記ダイパッドと対向する内側端面と、前記内側端面とは反対側に位置し、かつ、前記封止体から露出する外側端面と、前記上面と前記下面との間に位置し、かつ、前記内側端面と前記外側端面との間に位置する第1側面と、前記第1側面とは反対側の第2側面と、を有しており、
さらに、前記複数のリードのそれぞれは、前記複数のリードのそれぞれの延在方向において、前記内側端面側に位置する第1部分と、前記第1部分よりも前記外側端面側に位置する第2部分と、を有しており、
前記第1側面における前記第1部分で、かつ、前記下面よりも前記上面側には、前記第1側面から突出するように第1ひさし部が形成されており、
前記第2側面における前記第2部分で、かつ、前記下面よりも前記上面側には、前記第2側面から突出するように第2ひさし部が形成されており、
前記第1側面における前記第2部分には、前記第1および第2ひさし部は形成されていなく、
前記第2側面における前記第1部分には、前記第1および第2ひさし部は形成されていないことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記複数のリードのそれぞれの前記内側端面で、かつ、前記下面よりも前記上面側には、前記内側端面から突出するように第3ひさし部が形成されていることを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記第3ひさし部の前記ダイパッド方向への迫り出し量は、前記第1ひさし部の隣り合った前記リード方向への迫り出し量、および前記第2ひさし部の隣り合った前記リード方向への迫り出し量よりそれぞれ大きいことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記封止体の平面形状は、四角形からなり、前記複数のリードは、平面視において、前記封止体の各辺に沿って奇数本ずつ配置され、
前記各辺において、前記奇数本の前記リードにおける中央リードを線対称とした形態になるように、前記複数のリードのそれぞれの前記第1および前記第2ひさし部が形成されていることを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、
前記中央リードの第1部分には、平面視で幅広となる幅広部が形成されていることを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、
前記第1ひさし部が形成された前記第1側面は、前記ワイヤの延在方向側であることを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、
前記各辺の前記奇数本の前記リードのうち、前記中央に配置される前記リード以外のリードは、それぞれの前記リードの第1部分の平面視の形状が、前記ワイヤの延在方向に沿うように屈曲していることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記封止体の平面形状は、四角形からなり、前記複数のリードは、平面視において、前記封止体の各辺に沿って偶数本ずつ配置され、
前記各辺において、前記偶数本の前記リードは、各リードの前記第1および前記第2ひさし部が前記偶数本の前記リードの配列方向に対してそれぞれ同一の向きに形成されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記複数のリードのそれぞれは、エッチング加工によって形成されたものであることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記複数のリードのそれぞれの前記第2側面の前記第2部分に形成された前記第2ひさし部は、前記封止体の内部で終端していることを特徴とする半導体装置。
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CN104347570B (zh) * | 2013-07-26 | 2018-07-20 | 恩智浦美国有限公司 | 无引线型半导体封装及其组装方法 |
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US8802500B2 (en) * | 2009-11-11 | 2014-08-12 | Stats Chippac Ltd. | Integrated circuit packaging system with leads and method of manufacture thereof |
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