DE68924366D1 - Verfahren zur Herstellung einer Halbleitervorrichtung. - Google Patents

Verfahren zur Herstellung einer Halbleitervorrichtung.

Info

Publication number: DE68924366D1
Authority: DE; Germany
Prior art keywords: manufacturing; semiconductor device; semiconductor
Prior art date: 1988-05-10
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

DE68924366T

Other languages

English (en)

Other versions

DE68924366T2 (de

Inventor

Tomoyuki Furuhata

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Seiko Epson Corp

Original Assignee

Seiko Epson Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1988-05-10

Filing date

1989-04-06

Publication date

1995-11-02

1989-04-06 Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp

1995-11-02 Application granted granted Critical

1995-11-02 Publication of DE68924366D1 publication Critical patent/DE68924366D1/de

1996-04-11 Publication of DE68924366T2 publication Critical patent/DE68924366T2/de

2009-04-07 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Classifications

- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D84/401—Combinations of FETs or IGBTs with BJTs
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
- H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/009—Bi-MOS

DE68924366T 1988-05-10 1989-04-06 Verfahren zur Herstellung einer Halbleitervorrichtung. Expired - Fee Related DE68924366T2 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
JP63111421A JPH01282857A (ja)	1988-05-10	1988-05-10	半導体装置及びその製造方法

Publications (2)

Publication Number	Publication Date
DE68924366D1 true DE68924366D1 (de)	1995-11-02
DE68924366T2 DE68924366T2 (de)	1996-04-11

Family

ID=14560749

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE68924366T Expired - Fee Related DE68924366T2 (de)	1988-05-10	1989-04-06	Verfahren zur Herstellung einer Halbleitervorrichtung.

Country Status (6)

Country	Link
US (1)	US5059549A (de)
EP (1)	EP0341821B1 (de)
JP (1)	JPH01282857A (de)
KR (1)	KR930008983B1 (de)
DE (1)	DE68924366T2 (de)
HK (1)	HK30297A (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPH0348459A (ja) *	1989-04-26	1991-03-01	Matsushita Electric Ind Co Ltd	半導体装置及びその製造方法
US5124271A (en) *	1990-06-20	1992-06-23	Texas Instruments Incorporated	Process for fabricating a BiCMOS integrated circuit
US5281544A (en) *	1990-07-23	1994-01-25	Seiko Epson Corporation	Method of manufacturing planar type polar transistors and combination bipolar/MIS type transistors
JP2825169B2 (ja) *	1990-09-17	1998-11-18	キヤノン株式会社	半導体装置
US5387811A (en) *	1991-01-25	1995-02-07	Nec Corporation	Composite semiconductor device with a particular bipolar structure
JP2950009B2 (ja) *	1992-02-26	1999-09-20	日本電気株式会社	ＢｉＣＭＯＳ集積回路装置及びその製造方法
US5648288A (en) *	1992-03-20	1997-07-15	Siliconix Incorporated	Threshold adjustment in field effect semiconductor devices
US6249030B1 (en)	1992-12-07	2001-06-19	Hyundai Electronics Industries Co., Ltd.	BI-CMOS integrated circuit
KR940018967A (ko) *	1993-01-30	1994-08-19	오가 노리오	반도체장치 및 그 제조방법
JP3244370B2 (ja) *	1993-12-20	2002-01-07	三菱電機株式会社	バイポーラトランジスタを有する半導体装置およびその製造方法
US5455189A (en) *	1994-02-28	1995-10-03	National Semiconductor Corporation	Method of forming BICMOS structures
US5422290A (en) *	1994-02-28	1995-06-06	National Semiconductor Corporation	Method of fabricating BiCMOS structures
JP2934738B2 (ja) *	1994-03-18	1999-08-16	セイコーインスツルメンツ株式会社	半導体装置およびその製造方法
US5501991A (en) *	1994-07-13	1996-03-26	Winbond Electronics Corporation	Process for making a bipolar junction transistor with a self-aligned base contact
JP2697631B2 (ja) *	1994-09-26	1998-01-14	日本電気株式会社	半導体装置の製造方法
JP3444002B2 (ja) *	1995-02-14	2003-09-08	ソニー株式会社	半導体装置およびその製造方法
JP3006825B2 (ja) *	1995-03-30	2000-02-07	日本電気株式会社	半導体集積回路装置の製造方法
US5780920A (en) *	1995-10-06	1998-07-14	Micron Technology, Inc.	Method of forming a resistor and integrated circuitry having a resistor construction
JP2776350B2 (ja) *	1995-12-18	1998-07-16	日本電気株式会社	半導体集積回路装置の製造方法
US6245604B1 (en)	1996-01-16	2001-06-12	Micron Technology	Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits
US5923078A (en) *	1996-07-11	1999-07-13	Micron Technology, Inc.	Method of forming a resistor and integrated circuitry having a resistor construction
KR100235628B1 (ko) *	1997-06-25	1999-12-15	김영환	반도체 소자의 제조방법
US6130137A (en) *	1997-10-20	2000-10-10	Micron Technology, Inc.	Method of forming a resistor and integrated circuitry having a resistor construction
JP2000340684A (ja) *	1999-05-31	2000-12-08	Sony Corp	半導体装置の製造方法
US6461925B1 (en) *	2000-03-30	2002-10-08	Motorola, Inc.	Method of manufacturing a heterojunction BiCMOS integrated circuit
JP4003438B2 (ja) *	2001-11-07	2007-11-07	株式会社デンソー	半導体装置の製造方法および半導体装置
US6849495B2 (en) *	2003-02-28	2005-02-01	Infineon Technologies Ag	Selective silicidation scheme for memory devices
US7927948B2 (en)	2005-07-20	2011-04-19	Micron Technology, Inc.	Devices with nanocrystals and methods of formation
JP5585662B2 (ja) *	2010-12-21	2014-09-10	コニカミノルタ株式会社	金属格子の製造方法ならびに該製造方法によって製造された金属格子およびこの金属格子を用いたｘ線撮像装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4016596A (en) *	1975-06-19	1977-04-05	International Business Machines Corporation	High performance integrated bipolar and complementary field effect transistors
US4225877A (en) *	1978-09-05	1980-09-30	Sprague Electric Company	Integrated circuit with C-Mos logic, and a bipolar driver with polysilicon resistors
US4299024A (en) *	1980-02-25	1981-11-10	Harris Corporation	Fabrication of complementary bipolar transistors and CMOS devices with poly gates
US4673965A (en) *	1983-02-22	1987-06-16	General Motors Corporation	Uses for buried contacts in integrated circuits
JPS60120552A (ja) *	1983-12-05	1985-06-28	Hitachi Ltd	バイポ−ラｃｍｉｓデバイスならびにその製造方法
US4665424A (en) *	1984-03-30	1987-05-12	Mitsubishi Denki Kabushiki Kaisha	Semiconductor device
KR880005690A (ko) *	1986-10-06	1988-06-30	넬손 스톤	선택적인 에피켁샬층을 사용한 BiCMOS 제조방법
US4929570A (en) *	1986-10-06	1990-05-29	National Semiconductor Corporation	Selective epitaxy BiCMOS process
US4902640A (en) *	1987-04-17	1990-02-20	Tektronix, Inc.	High speed double polycide bipolar/CMOS integrated circuit process
KR900005353B1 (ko) *	1987-11-03	1990-07-27	삼성전자 주식회사	반도체 장치의 제조방법

1988
- 1988-05-10 JP JP63111421A patent/JPH01282857A/ja active Pending
1989
- 1989-04-06 EP EP89303391A patent/EP0341821B1/de not_active Expired - Lifetime
- 1989-04-06 DE DE68924366T patent/DE68924366T2/de not_active Expired - Fee Related
- 1989-05-08 KR KR1019890006111A patent/KR930008983B1/ko not_active IP Right Cessation
1990
- 1990-03-27 US US07/499,906 patent/US5059549A/en not_active Expired - Lifetime
1997
- 1997-03-13 HK HK30297A patent/HK30297A/xx not_active IP Right Cessation

Also Published As

Publication number	Publication date
HK30297A (en)	1997-03-21
EP0341821A3 (en)	1990-09-26
KR900019023A (ko)	1990-12-22
EP0341821A2 (de)	1989-11-15
DE68924366T2 (de)	1996-04-11
US5059549A (en)	1991-10-22
JPH01282857A (ja)	1989-11-14
KR930008983B1 (ko)	1993-09-17
EP0341821B1 (de)	1995-09-27

Publication	Publication Date	Title
DE69015216D1 (de)	1995-02-02	Verfahren zur Herstellung einer Halbleitervorrichtung.
DE68924366D1 (de)	1995-11-02	Verfahren zur Herstellung einer Halbleitervorrichtung.
DE68929150D1 (de)	2000-03-09	Verfahren zur Herstellung einer Halbleitervorrichtung
DE69032773D1 (de)	1998-12-24	Verfahren zur Herstellung einer Halbleitervorrichtung
DE69023558D1 (de)	1995-12-21	Verfahren zur Herstellung einer Halbleitervorrichtung.
DE3853778D1 (de)	1995-06-14	Verfahren zur Herstellung eines Halbleiterbauelements.
DE69232432D1 (de)	2002-04-04	Verfahren zur Herstellung einer Halbleiteranordnung
DE69231803D1 (de)	2001-05-31	Verfahren zur Herstellung einer Halbleiteranordnung
DE69317800D1 (de)	1998-05-14	Verfahren zur Herstellung einer Halbleiteranordnung
DE69330980D1 (de)	2001-11-29	Verfahren zur Herstellung einer Halbleiteranordnung
DE69421592D1 (de)	1999-12-16	Verfahren zur Herstellung einer Halbleitervorrichtung
DE68907507D1 (de)	1993-08-19	Verfahren zur herstellung einer halbleitervorrichtung.
DE69023951D1 (de)	1996-01-18	Verfahren zur Herstellung von Kontakten an einer Halbleitervorrichtung.
DE3686315D1 (de)	1992-09-10	Verfahren zur herstellung einer halbleiterstruktur.
DE69216752D1 (de)	1997-02-27	Verfahren zur Herstellung einer Halbleiter-Scheibe
DE69323979D1 (de)	1999-04-22	Verfahren zur Herstellung einer Halbleitervorrichtung
DE69004201D1 (de)	1993-12-02	Verfahren zur Herstellung einer SOI-Halbleiteranordnung.
DE69016955D1 (de)	1995-03-23	Verfahren zur Herstellung einer Halbleiteranordnung.
DE69503532D1 (de)	1998-08-27	Verfahren zur Herstellung einer Halbleitervorrichtung
DE69112545D1 (de)	1995-10-05	Verfahren zur Herstellung eines Halbleiterbauelementes.
DE69030709D1 (de)	1997-06-19	Verfahren zur Herstellung einer Halbleiteranordnung
DE3582143D1 (de)	1991-04-18	Verfahren zur herstellung einer halbleitervorrichtung.
DE69028397D1 (de)	1996-10-10	Verfahren zur herstellung einer halbleitervorrichtung
DE69031702D1 (de)	1997-12-18	Verfahren zur Herstellung einer Halbleiteranordnung
DE3779802D1 (de)	1992-07-23	Verfahren zur herstellung einer halbleiteranordnung.

Legal Events

Date	Code	Title	Description
1996-10-24	8364	No opposition during term of opposition
2008-02-14	8339	Ceased/non-payment of the annual fee