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DE69031702D1 - Verfahren zur Herstellung einer Halbleiteranordnung - Google Patents

Verfahren zur Herstellung einer Halbleiteranordnung

Info

Publication number
DE69031702D1
DE69031702D1 DE69031702T DE69031702T DE69031702D1 DE 69031702 D1 DE69031702 D1 DE 69031702D1 DE 69031702 T DE69031702 T DE 69031702T DE 69031702 T DE69031702 T DE 69031702T DE 69031702 D1 DE69031702 D1 DE 69031702D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69031702T
Other languages
English (en)
Other versions
DE69031702T2 (de
Inventor
Tohru Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69031702D1 publication Critical patent/DE69031702D1/de
Application granted granted Critical
Publication of DE69031702T2 publication Critical patent/DE69031702T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/01—Bipolar transistors-ion implantation
DE69031702T 1989-09-11 1990-09-11 Verfahren zur Herstellung einer Halbleiteranordnung Expired - Fee Related DE69031702T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1232904A JPH081930B2 (ja) 1989-09-11 1989-09-11 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69031702D1 true DE69031702D1 (de) 1997-12-18
DE69031702T2 DE69031702T2 (de) 1998-04-02

Family

ID=16946660

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69031702T Expired - Fee Related DE69031702T2 (de) 1989-09-11 1990-09-11 Verfahren zur Herstellung einer Halbleiteranordnung

Country Status (5)

Country Link
US (2) US5460984A (de)
EP (1) EP0417715B1 (de)
JP (1) JPH081930B2 (de)
KR (1) KR940004454B1 (de)
DE (1) DE69031702T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2682425B2 (ja) * 1993-12-24 1997-11-26 日本電気株式会社 半導体装置の製造方法
JPH0878776A (ja) * 1994-09-06 1996-03-22 Fuji Xerox Co Ltd 半導体レーザ装置
US5573963A (en) * 1995-05-03 1996-11-12 Vanguard International Semiconductor Corporation Method of forming self-aligned twin tub CMOS devices
KR0146080B1 (ko) * 1995-07-26 1998-08-01 문정환 반도체 소자의 트윈 웰 형성방법
DE19534784C1 (de) * 1995-09-19 1997-04-24 Siemens Ag Halbleiter-Schaltungselement und Verfahren zu seiner Herstellung
US5573962A (en) * 1995-12-15 1996-11-12 Vanguard International Semiconductor Corporation Low cycle time CMOS process
KR100189739B1 (ko) * 1996-05-02 1999-06-01 구본준 반도체 기판에 삼중웰을 형성하는 방법
US5776816A (en) * 1996-10-28 1998-07-07 Holtek Microelectronics, Inc. Nitride double etching for twin well align
CN1067800C (zh) * 1996-11-14 2001-06-27 联华电子股份有限公司 集成电路的制造方法
US6017787A (en) * 1996-12-31 2000-01-25 Lucent Technologies Inc. Integrated circuit with twin tub
DE19752848C2 (de) * 1997-11-28 2003-12-24 Infineon Technologies Ag Elektrisch entkoppelter Feldeffekt-Transistor in Dreifach-Wanne und Verwendung desselben
KR100263909B1 (ko) * 1998-06-15 2000-09-01 윤종용 반도체 집적회로의 다중 웰 형성방법
FR2826507B1 (fr) * 2001-06-21 2004-07-02 St Microelectronics Sa Procede de traitement de zones complementaires de la surface d'un substrat et produit semi-conducteur obtenu par ce procede
JP6216142B2 (ja) * 2012-05-28 2017-10-18 キヤノン株式会社 半導体装置の製造方法
CN106653599B (zh) * 2015-11-02 2021-03-16 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3212162A (en) * 1962-01-05 1965-10-19 Fairchild Camera Instr Co Fabricating semiconductor devices
JPS5737877A (en) * 1980-08-20 1982-03-02 Seiko Epson Corp Semiconductor device
DE3149185A1 (de) * 1981-12-11 1983-06-23 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung benachbarter mit dotierstoffionen implantierter wannen bei der herstellung von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
US4567644A (en) * 1982-12-20 1986-02-04 Signetics Corporation Method of making triple diffused ISL structure
JPS60105267A (ja) * 1983-11-14 1985-06-10 Toshiba Corp 半導体装置の製造方法
JPS60138955A (ja) * 1983-12-27 1985-07-23 Toshiba Corp 半導体装置の製造方法
JPS60194558A (ja) * 1984-03-16 1985-10-03 Hitachi Ltd 半導体装置の製造方法
JPH0793282B2 (ja) * 1985-04-15 1995-10-09 株式会社日立製作所 半導体装置の製造方法
WO1987005443A1 (en) * 1986-03-04 1987-09-11 Motorola, Inc. High/low doping profile for twin well process
JPS63207169A (ja) * 1987-02-24 1988-08-26 Toshiba Corp 半導体記憶装置及びその製造方法
US4795716A (en) * 1987-06-19 1989-01-03 General Electric Company Method of making a power IC structure with enhancement and/or CMOS logic
US5260226A (en) * 1987-07-10 1993-11-09 Kabushiki Kaisha Toshiba Semiconductor device having different impurity concentration wells
US4983534A (en) * 1988-01-05 1991-01-08 Nec Corporation Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
KR940004454B1 (ko) 1994-05-25
US5460984A (en) 1995-10-24
EP0417715A1 (de) 1991-03-20
US6011292A (en) 2000-01-04
JPH081930B2 (ja) 1996-01-10
DE69031702T2 (de) 1998-04-02
JPH0397261A (ja) 1991-04-23
KR910007132A (ko) 1991-04-30
EP0417715B1 (de) 1997-11-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee