CN2798311Y - Substrate structure for image sensor chip packaging - Google Patents

Abstract

The utility model discloses a substrate structure for packaging an image sensing chip, which comprises a bottom plate, a plurality of first electrodes and a plurality of second electrodes, wherein the bottom plate is provided with an upper surface and a lower surface; forming a plurality of flange layers on the upper surface of the base plate, wherein the flange layers are of a frame-shaped structure and form a plurality of grooves with the base plate; providing an adhesive tape adhered to the lower surface of the base plate for adhering and fixing the base plate; cutting each flange layer to form a single substrate.

Description

Substrate structure for image sensor chip packaging

technical field

The utility model relates to a substrate structure for image sensing chip packaging, in particular to a substrate structure for image sensing chip packaging which is more convenient to manufacture and can effectively improve the pass rate.

Background technique

Please refer to FIG. 1 , which is a cross-sectional view of a known image sensor package structure, which includes a substrate 10 with a first surface 12 and a second surface 14, the first surface 12 is formed with a first contact 15, the second The second contact point 16 is formed on the two surfaces 14; a flange layer 18 is provided with an upper surface 20 and a lower surface 22, and the lower surface 22 is adhered and fixed on the first surface 12 of the substrate 10 to form an accommodating chamber with the substrate 10 24; an image sensing chip 26 is disposed in the accommodation chamber 24 formed by the substrate 10 and the flange layer 18, and is fixed on the first surface 12 of the substrate 10; a plurality of wires 28, which have a first terminal 30 and a second terminal 32, the first terminal 30 is electrically connected to the image sensor chip 26, the second terminal 32 is electrically connected to the signal input terminal 15 of the substrate 10; and a light-transmitting layer 34 is glued on the flange layer 18 20 of the upper surface.

However, in the actual manufacturing process, the combination of the substrate 10 and the flange layer 18 is a single piece, so it must be cut into a single piece. During cutting, impurities or moisture are easy to flow from each adjacent first contact. 15 room infiltration, which affects its cleanliness.

In view of this, the designer, in the spirit of excellence, innovation and breakthrough, devoted himself to the research and development of image sensor packaging, and developed the substrate structure for image sensor chip packaging of the utility model, making it more efficient in manufacturing. For convenience and to improve its pass rate.

Utility model content

The main purpose of the utility model is to provide a substrate structure for image sensor chip packaging, which has the advantages of reducing pollution and improving the yield of manufacturing.

For this reason, the utility model proposes a substrate structure for image sensing chip packaging, which includes: a bottom plate, which is provided with an upper surface and a lower surface, the upper surface is formed with a plurality of first electrodes, the A plurality of second electrodes are formed on the lower surface, and green paint is coated between each first electrode, so that the bottom plate forms a flat surface; a flange layer, which is a frame structure, is laminated on the bottom plate The upper surface forms a groove with the bottom plate for accommodating the image sensing chip.

The above-mentioned first electrodes are electrically connected to the corresponding second electrodes.

To sum up, because the utility model is coated with green paint between each of the first electrodes of the bottom plate, during the cutting process, the cutting water will not flow into the groove from between each of the first electrodes, thus Can improve the cleanliness of the product.

Description of drawings

FIG. 1 is a cross-sectional view of a conventional image sensor package structure.

FIG. 2 is a top view of the base plate used for image sensing chip packaging of the present invention.

FIG. 3 is a cross-sectional view of a substrate used for image sensing chip packaging of the present invention.

FIG. 4 is a first schematic diagram of the substrate manufacturing method for image sensor chip packaging of the present invention.

FIG. 5 is a second schematic diagram of the substrate manufacturing method for image sensor chip packaging of the present invention.

Explanation of reference numbers:

public part

Substrate 10 First Surface 12 Second Surface 14

First Contact 15 Second Surface 14 Second Contact 16

Flange layer 18 upper surface 20 lower surface 22

Storage room 24 image sensor chip 26 wire 28

First endpoint 30 Second endpoint 32 Transparent layer 34

The utility model part

Bottom plate 40 Flange layer 42 Upper surface 44

Lower surface 46 first electrode 48 second electrode 50

Green paint 52 groove 54 tape 56

Detailed ways

Please refer to FIG. 2 and FIG. 3 , which are substrate structures used for image sensor chip packaging of the present invention, which include a bottom plate 40 and a flange layer 42:

The bottom plate 40 is provided with an upper surface 44 and a lower surface 46, the upper surface 44 is formed with a plurality of first electrodes 48, and the lower surface 46 is formed with a plurality of second electrodes 50, and the second electrodes 50 are correspondingly electrically connected to the first One electrode 48, green paint 52 is coated between each first electrode 48, so that the peripheral edge of the bottom plate 40 forms a flat surface.

The flange layer 42 is a frame structure, laminated on the upper surface 44 of the bottom plate 40 , and forms a groove 54 with the bottom plate 40 for accommodating the image sensor chip.

Please refer to FIG. 4 and FIG. 5 together, which are schematic diagrams of the substrate manufacturing method used for image sensor chip packaging of the present invention. A bottom plate 40 is provided, which is provided with an upper surface 44 and a lower surface 46. The upper surface 44 is formed with multiple layers. A first electrode, a plurality of second electrodes 50 are formed on the lower surface 46, and a green paint 52 is coated between each first electrode 48, so that the bottom plate 40 forms a flat surface around it.

A plurality of flange layers 42 are formed on the upper surface 44 of the base plate 40 . The flange layer 42 is a frame structure and forms a plurality of grooves 54 with the base plate 40 .

An adhesive tape 56 is provided to adhere to the lower surface 46 of the base plate 40 for adhering and fixing the base plate 40 .

Each flange layer 42 is cut to form a single substrate.

Because green paint 52 is coated between each first electrode 48 of base plate 40, therefore, in the process of cutting, cutting water can not flow in the groove 54 by each first electrode 48, and can improve the product quality. cleanliness.

The specific embodiments proposed in the detailed description of the preferred embodiments are only for the sake of easy description of the technical content of the present utility model, and the present utility model is not limited to the embodiments in a narrow sense. Various changes are implemented and all belong to the patent scope of the present utility model.

Claims (2)

1. a base plate structure that is used for the image sensing chip encapsulation is characterized in that, includes:

One bottom plate, it is provided with a upper surface and a lower surface, and this upper surface is formed with a plurality of first electrodes, and this lower surface is formed with a plurality of second electrodes, is coated with green lacquer between this each first electrode, and this bottom plate forms flat surface;

One flange layer, it is a frame type structure, and is superimposed in the upper surface of this bottom plate, and is formed with a groove in order to ccontaining this image sensing chip with this bottom plate.

2. the base plate structure that is used for the image sensing chip encapsulation as claimed in claim 1 is characterized in that this first electrode is electrically connected to corresponding second electrode.

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