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CN2598136Y - Chip stacking structure - Google Patents

Chip stacking structure Download PDF

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Publication number
CN2598136Y
CN2598136Y CNU022941754U CN02294175U CN2598136Y CN 2598136 Y CN2598136 Y CN 2598136Y CN U022941754 U CNU022941754 U CN U022941754U CN 02294175 U CN02294175 U CN 02294175U CN 2598136 Y CN2598136 Y CN 2598136Y
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CN
China
Prior art keywords
substrate
chip
wires
groove
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNU022941754U
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Chinese (zh)
Inventor
辛宗宪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kingpak Technology Inc
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Kingpak Technology Inc
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Filing date
Publication date
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Priority to CNU022941754U priority Critical patent/CN2598136Y/en
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Publication of CN2598136Y publication Critical patent/CN2598136Y/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The utility model discloses the wafer piles up the structure including: a substrate having a first surface and a second surface, wherein a recess is formed at the center of the first surface and a plurality of signal input terminals are formed at the periphery of the first surface; a lower wafer is adhered in the groove from the first surface of the substrate; a plurality of wires for electrically connecting the lower chip to the signal input terminal of the substrate; an adhesive layer coated on the lower chip; an upper wafer is adhered and fixed on the upper surface of the lower wafer by the adhesive layer; and a sealant layer disposed on the first surface of the substrate for covering the upper and lower chips and the plurality of wires. For example, when the upper layer chip is stacked on the lower layer chip, because the upper layer chip is accommodated in the groove of the substrate, when the wire bonding operation of the plurality of wires is performed, the radian formed by the plurality of wires is small, the breakage is not easy to occur, and the generated glue overflow is filled in the groove of the substrate, so that the electric contact can be avoided.

Description

The wafer stacking structure
Technical field
The utility model relates to a kind of wafer stacking structure, is meant that especially a kind of being convenient to effectively pile up integrated circuit, wafer stacking structure more easily on making.
Background technology
In the field of science and technology, every sci-tech product all with light, thin, short and small be its demand, therefore, be unreasonablely to think more for a short time for the volume of integrated circuit, more can meet the demand of product.Even and the integrated circuit volume was littler in the past, also can only be electrically connected on the circuit board to block form, and on limited board area, and the ccontaining quantity of integrated circuit can't be promoted effectively, be with, desire to make product to reach more light, thin, short and small demand, its where the shoe pinches will be arranged.
Therefore, several integrated circuit are given superimposed use, can reach light, thin, short and small demand, yet, when several integrated circuit were superimposed, the upper strata integrated circuit will be pressed onto the lead of lower floor's integrated circuit, so that will have influence on the signal transmission of lower floor's integrated circuit.
Be with, known a kind of wafer stacking structure sees also Fig. 1, it includes a substrate 10, a lower chip 12, a upper chip 14, a plurality of lead 16 and a separator 18.Lower chip 12 is to be located on the substrate 10, upper chip 14 is superimposed in lower chip 12 tops by separator 18, make lower chip 12 and upper chip 14 form a suitable spacing 20, in this way, a plurality of leads can be electrically connected on lower chip 12 edges, make upper chip 14 superimposed on lower chip 12 time, be unlikely a plurality of leads 16 of crushing.
Yet this kind structure must be made separator 18 earlier on making, it is adhered on the lower chip 12 again, then upper chip 14 is adhered on the separator 18 again, be with, its fabrication schedule is comparatively complicated, production cost is higher.And plural wires 16 is when playing the lead operation, because lead 16 must be connected on lower chip 12 and the upper chip 14 by substrate 10, its formed radian is bigger, causes the breakdown of lead 16 easily, and it is comparatively difficult on making, and yield is lower.And, when lower chip 12 is adhered on the substrate 10, often causes and overflow glue and weld pad is covered, and have influence on the electrical connection of lead 16.
Supervise in this, the inventor be this in the spirit of keeping on improving, innovate breakthrough, and create the utility model wafer stacking structure, can effectively improve the wafer stacking processing procedure, it is more convenient that it is made, and reduce production costs.
Summary of the invention
Main purpose of the present utility model is: a kind of wafer stacking structure is provided, and it has is convenient to effect that wafer is piled up, to reach the purpose that improves speed of production.
Another purpose of the present utility model is: a kind of wafer stacking structure is provided, and its glue of can avoiding overflowing produces, and influence is electrically connected.
Another purpose of the present utility model is: a kind of wafer stacking structure is provided, and it has the effect that reduces the lead breakdown, improves the purpose of producing yield and cost to reach.
Be with, in order to achieve the above object, of the present utility model being characterised in that includes:
One substrate, it is provided with a first surface and a second surface, and this first surface central part is formed with a groove and periphery is formed with the plurality of signals input;
One lower chip is to be located in this groove by the first surface of this substrate is sticking; Plural wires, it is provided with one first end points and one second end points, and this first end points is to be electrically connected on this lower chip, and second end points is the signal input end that is electrically connected on the first surface of this substrate; One adhesive-layer is to coat on this lower chip; One upper chip is the upper surface that is fixed in this lower chip by this adhesive-layer adhesion, also is electrically connected to the signal input end of this substrate by this plural wires; And an adhesive layer, it is to be located on the first surface of this substrate, in order to should upper and lower layer wafer and plural wires envelope.
The signal output end of this substrate is formed with ball grid array Metal Ball (BGA).
In this way, when upper chip is stacked on the lower chip, because it is to be placed in the groove of substrate, therefore, when carrying out the routing operation of plural wires, the formed radian of this plural wires is less, is difficult for having the situation of breakdown, and the excessive glue that is produced will be filled in the groove of this substrate, can avoid having influence on electrical contact.
Description of drawings
Fig. 1 is the cutaway view of known wafer stacking structure.
Fig. 2 is the cutaway view of the utility model wafer stacking structure.
Fig. 3 is first schematic diagram of the utility model wafer stacking structure.
Fig. 4 is second schematic diagram of the utility model wafer stacking structure.
Substrate 10 lower chip 12
Upper chip 14 plural wires 16
Separator 18 spacings 20
Substrate 30 lower chip 32
Plural wires 34 adhesive-layers 36
Upper chip 38 adhesive layers 40
First surface 42 second surfaces 44
Groove 46 signal input ends 48
Signal output end 49 lower chip 32
Lower surface 50 ball grid array Metal Ball 51
Upper surface 52 a plurality of weld pads 54
First end points, 56 second end points 58
Lower surface 60 upper surfaces 62
Embodiment
See also Fig. 2, be the cutaway view of the utility model wafer stacking structure, it includes a substrate 30, a lower chip 32, plural wires 34, an adhesive-layer 36, a upper chip 38 and adhesive layer 40:
Substrate 30, it is provided with a first surface 42 and a second surface 44, first surface 42 central parts are formed with a groove 46 and periphery is formed with plurality of signals input 48, second surface 44 is formed with a signal output end 49, in order to be electrically connected on the circuit board (figure does not show), signal output end 49 is formed with ball grid array Metal Ball (BGA) 51.
Lower chip 32, it is provided with an a lower surface 50 and a upper surface 52, and lower surface 50 is that upper surface 52 has a plurality of weld pads 54 by first surface 42 sticking being located in the groove 46 of substrate 30.
Plural wires 34, it is provided with one first end points 56 and one second end points 58, first end points 56 is to be electrically connected on the weld pad 54 of lower chip 32, and second end points 58 is the signal input ends 48 that are electrically connected on the first surface 42 of substrate 30, is passed on the substrate 30 in order to the signal with lower chip 32.
Adhesive-layer 36, it is to coat on the upper surface 52 of lower chip 32, in order to plural wires 34 is enveloped.
Upper chip 38, it has an a lower surface 60 and a upper surface 62, lower surface 60 is to be fixed on the upper surface 52 of lower chip 32 by adhesive-layer 36 adhesions, and its upper surface 62 also is formed with a plurality of weld pads 54, also is electrically connected on the signal input end 48 of substrate 30 by plural wires 34.And
Adhesive layer 40, it is to be located on the first surface 42 of substrate 30, in order to upper and lower layer wafer 38,32 and plural wires 34 are enveloped.
See also Fig. 3, be first schematic diagram in the manufacturing of the utility model wafer stacking structure, substrate 30 at first is provided, its first surface 42 central parts are formed with groove 46, and periphery is formed with plurality of signals input 48, its second surface 44 is formed with plurality of signals output 49, and signal output end 49 is provided with ball grid array Metal Ball (BGA) 51.Then lower chip 32 is placed in the groove 46 of substrate 30, and be adhered on the substrate 30, plural wires 34 is electrically connected the signal input end 48 of the weld pad 54 of lower chip 32 to the first surface 42 of substrate 30.
See also Fig. 4, adhesive-layer 36 is coated on the upper surface 52 of lower chip 32, lower chip 32 and plural wires 34 are enveloped, make when upper chip 38 is stacked in lower chip 32, unlikely crushing plural wires 34, and the excessive glue of adhesive-layer 36 will drop down onto in the groove 46, and the unlikely signal input end 48 that pollutes can make its signal transmission effect preferable.
Tectonic association as above, the utility model wafer stacking structure has following advantage:
1. the excessive glue of upper chip 38 and lower chip 32 is dropped down onto in the groove 36, the unlikely signal input end 48 that pollutes.
2. upper chip 38 is stacked on the lower chip 32 by adhesive-layer 36, and adhesive-layer 36 can be protected lead 34 simultaneously, makes upper chip 38 unlikely crushing leads 34.
3. because lower chip 32 and upper chip 38 are to be positioned at groove 36, make that the routing radian of lead 34 is less, therefore, can effectively avoid the situation of lead 34 breakdown.
The specific embodiment that is proposed in the detailed description of preferred embodiment only is in order to be easy to illustrate technology contents of the present utility model, be not with the utility model narrow sense be limited to embodiment, all many variations that situation is done enforcement according to spirit of the present utility model and claim all belongs to scope of the present utility model.

Claims (2)

1.一种晶片堆叠构造，其特征在于：包括有；1. A wafer stack structure, characterized in that: comprising; 一基板，其设有一第一表面及一第二表面，该第一表面中央部位形成有一凹槽及周缘形成有复数个讯号输入端，该第二表面形成有一讯号输出端；A substrate, which is provided with a first surface and a second surface, a groove is formed in the center of the first surface and a plurality of signal input terminals are formed on the periphery, and a signal output terminal is formed on the second surface; 一下层晶片，其设有一下表面及一上表面，该下表面是由该基板的第一表面粘设于该凹槽内，该上表面具有复数个焊垫；The lower chip has a lower surface and an upper surface, the lower surface is glued into the groove by the first surface of the substrate, and the upper surface has a plurality of welding pads; 复数条导线，其设有一第一端点及一第二端点，该第一端点是电连接于该下层积体电路的焊垫，第二端点是电连接于该基板的第一表面的讯号输入端；A plurality of wires, which are provided with a first terminal and a second terminal, the first terminal is electrically connected to the pad of the underlying integrated circuit, and the second terminal is electrically connected to the signal on the first surface of the substrate input terminal; 一粘胶层，是涂布于该下层晶片的上表面；An adhesive layer is coated on the upper surface of the lower wafer; 一上层晶片，其具有一下表面及一上表面，该下表面是由该粘胶层粘着固定于该下层晶片的上表面，该上表面形成有复数个焊垫，也由该复数条导线电连接至该基板的讯号输入端；及An upper chip, which has a lower surface and an upper surface, the lower surface is adhered and fixed on the upper surface of the lower chip by the adhesive layer, a plurality of welding pads are formed on the upper surface, and are also electrically connected by the plurality of wires to the signal input of the substrate; and 一封胶层，其是设于该基板的第一表面上，将该上、下层积体电路及复数条导线包覆住。The sealant layer is arranged on the first surface of the substrate, covering the upper and lower laminated circuits and a plurality of wires. 2.如权利要求1所述的晶片堆叠构造，其特征在于：该基板的讯号输出端形成有球栅阵列金属球(BGA)。2. The chip stack structure as claimed in claim 1, wherein a ball grid array (BGA) is formed on the signal output end of the substrate.
CNU022941754U 2002-12-27 2002-12-27 Chip stacking structure Expired - Lifetime CN2598136Y (en)

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Application Number Priority Date Filing Date Title
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100530629C (en) * 2007-02-05 2009-08-19 力成科技股份有限公司 Multi-chip stacked substrate and multi-chip stacked package structure using the same
CN104617077A (en) * 2015-01-26 2015-05-13 华为技术有限公司 Package substrate and integrated circuit chip
CN110945660A (en) * 2019-11-12 2020-03-31 深圳市汇顶科技股份有限公司 Stacked chip, manufacturing method, image sensor and electronic device
WO2021146860A1 (en) * 2020-01-20 2021-07-29 深圳市汇顶科技股份有限公司 Stacked chip, manufacturing method, image sensor, and electronic device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100530629C (en) * 2007-02-05 2009-08-19 力成科技股份有限公司 Multi-chip stacked substrate and multi-chip stacked package structure using the same
CN104617077A (en) * 2015-01-26 2015-05-13 华为技术有限公司 Package substrate and integrated circuit chip
CN110945660A (en) * 2019-11-12 2020-03-31 深圳市汇顶科技股份有限公司 Stacked chip, manufacturing method, image sensor and electronic device
WO2021092777A1 (en) * 2019-11-12 2021-05-20 深圳市汇顶科技股份有限公司 Stacked chip, manufacturing method, image sensor, and electronic device
CN110945660B (en) * 2019-11-12 2024-01-23 深圳市汇顶科技股份有限公司 Stacked chip, manufacturing method, image sensor and electronic device
WO2021146860A1 (en) * 2020-01-20 2021-07-29 深圳市汇顶科技股份有限公司 Stacked chip, manufacturing method, image sensor, and electronic device

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C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CX01 Expiry of patent term

Expiration termination date: 20121227

Granted publication date: 20040107