CN1943004A - 表面贴装多通道光耦合器 - Google Patents
表面贴装多通道光耦合器 Download PDFInfo
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Abstract
公布了一种光耦合器封装部件。该光耦合器封装部件包括一个基片和多个光耦合器,该基片包括引线框和塑封料,每一个光耦合器包括:(i)光发射器;(ii)光接收器;(iii)置于光发射器和光接收器之间的透光材料,其中光发射器和光接收器电耦合到引线框。
Description
发明背景
光耦合器包含至少一个光发射器,该光发射器通过透光介质光耦合到光接收器。这种结构准许将信息从一个包含光发射器的电路传递到另一个包含光接收器的电路。在这两个电路之间保持高度电隔离。因为信息是横跨绝缘空隙以光的形式来传递的,所以该传递是单向的。例如,光接收器不能限制包含光发射器的电路的操作。该特征是重要的,例如因为发射器可能由使用微处理器或逻辑门的低电压电路来驱动,而同时输出光接收器可能是高电压DC或AC负载电路的一部分。这种光隔离也防止由相对恶劣的输出电路对输入电路所造成的损坏。
常见的光耦合器封装形式是双列直插式封装或DIP。这种封装广泛用于安装集成电路,并且也用于常规的光耦合器。通常制造的各种版本的光耦合器DIP封装部件具有4、6、8或16个引脚。
图1示出了常规的光耦合器DIP封装部件10的横截面。所示的光耦合器10包括引线框24,引线框24包括引线24(a)、24(b)(即引脚)。光发射器12安装在一个引线24(a)上。光接收器14安装在另一个引线24(b)上。光接收器14在接收到光发射器12所产生的光之后就产生了电信号。光发射器12通过其底面电耦合到引线24(a),并且通过导线11耦合到另一个引线(未示出)。相似的是,光接收器14通过底面电耦合到24(b),并且通过导线13耦合到另一个引线(未示出)。本领域的技术人员将会认识到,光发射器12用两个电连接即阳极和阴极来操作。这些连接由导线11和引线24(a)来提供。相似的是,光接收器14用两个电连接(通常是发射极和集电极)来操作。这些连接由导线13和引线24(b)来提供。光耦合器封装部件10还包括透光介质16。塑封料18包住引线框24、光发射器12、光接收器14和透光介质16。
对于图1所示的光耦合器封装部件10,可以做出大量的改进。例如,光耦合器封装部件10需要昂贵且费时的注塑成型工艺。在注塑成型工艺中,塑封料18包住光耦合器封装部件10的其它部分。除了注塑成型工艺本身以外,使用成型材料去除工艺(例如,胶渣去除工艺)来去除多余的塑封料,由此增加了形成光耦合器封装部件的时间和成本。另外,产生不同“形状因子”的模制品(例如,4、6或8引脚封装部件)所需的工具也需要相当大的投资。相应地,如果可以省去注塑成型工艺,则与生产光耦合器封装部件相关联的时间和成本可以减少许多。
对光耦合器封装部件10,也可以做出其它改进。光耦合器封装部件10也容易因热循环而出故障。例如,当塑封料18和透光介质16被加热或冷却时,它们的热膨胀特性差异使它们以不同的比率膨胀或收缩。塑封料18和透光介质16有可能分离,从而导致结构性较弱的封装部件。温度变化也会在引线框24从塑封料18中出来的那些点处产生应力(例如,在点“A”处)。该应力可能会使引线框24断裂或性能变差。同时,导线11、13有时候可能会穿透透光介质16和塑封料18。透光介质16和塑封料18的热膨胀特性差异可能导致导线11和13中产生应力并使它们断裂。
同时也期望减小常规光耦合器封装部件的高度。图1所示的光耦合器封装部件10相对太高。例如,典型的DIP封装部件的净高度约为3.5到4.0毫米。期望减小光耦合器封装部件的高度,这样它便可以具有较矮的外形。如此,可以生产出更小的电子元件。
同时期望增加上述封装部件的功能并减小与制造光耦合器封装部件相关联的成本。
本发明的多个实施例单独地或共同地来解决这些和其它问题。
发明内容
本发明的多个实施例涉及光耦合器封装部件及其制造方法。
本发明的一个实施例涉及一种光耦合器封装部件,它包括:(a)基片,该基片包括引线框和塑封料;(b)光发射器;(c)光接收器,其中光发射器和光接收器电耦合到该引线框;以及(d)透光介质,它被置于光发射器和光接收器之间。
本发明的另一个实施例涉及一种用于形成光耦合器封装部件的方法,该方法包括:(a)形成包括引线框和塑封料的基片;(b)将光发射器和光接收器附着到该基片上;以及(c)在该光发射器和光接收器之间沉积透光材料。
本发明的另一个实施例涉及一种光耦合器封装部件,它包括:(a)基片;(b)至少两个光发射器;(c)至少两个光接收器;以及(d)在相邻的光发射器和光接收器之间的透光介质,其中光发射器和光接收器位于该基片上。
在下文中进一步详细描述这些和其它实施例。
附图说明
图1示出了现有技术的光耦合器封装部件。
图2从底部透视角度示出了根据本发明一实施例的基片。
图3示出了图4的基片,该基片示出了内部引线框配置。
图4示出了图5所示基片的底部平面图。
图5示出了图4所示基片沿A-A线的侧面横截面图。
图6是该基片的另一张底部平面图,它示出了不同的光耦合器象限。
图7从底部透视角度示出了根据本发明一实施例的光耦合器封装部件。
图8从顶部透视角度示出了根据本发明一实施例的光耦合器封装部件。
图9是从底部透视角度看到的光耦合器封装部件的底部透视图,并且其中示出了光发射器和光接收器。
图10是一种光耦合器封装部件的底部平面图,它示出了光接收器和光发射器。
图11示出了一种光耦合器组件,它包括安装在基片上的光耦合器封装部件。
具体实施方式
在本发明的实施例中,一个或多个光耦合器位于单个基片上,该基片由引线框和塑封料构成。例如,在单个基片上可以有四个光耦合器排成四元阵列。每一个光耦合器可以包括光发射器(例如,发光二极管)和光接收器(例如,光电二极管)。光接收器和光发射器之间的间隔可以大约介于0.3毫米到0.5毫米之间。每一个光耦合器都可以用透光耦合凝胶来固定,并且可以用不透光的高反射环氧基聚合物来包住。可以将光耦合器的功能端分组,并将它们引向该封装部件的四周,这样便形成了球形栅格阵列布局。光接收器、光发射器和引线键合点可排列成使得它们将对应于引线框的各端。
诸如控制芯片等逻辑器件也可以位于该基于引线框的基片上,并且也可以位于光耦合器封装部件中。此外,包括MOSFET(金属氧化物半导体场效应晶体管)(比如,带有或不带有槽栅的功率MOSFET)的芯片可以位于该基片上或该封装部件中。这种芯片或器件可以位于该基片上,并且可以电耦合到诸如光发射器和光接收器等组件。
在一些实施例中,光耦合器封装部件很薄,并且具有至少两个光耦合器(例如,四个光耦合器)。有利的是,与各自带有一个光耦合器的四个分立的光耦合器封装部件相比,单个的光耦合器封装部件可以提供相同的或改进的性能。如下文所示,该封装部件中的外围焊接球布局允许更简单的板设计,因为导电轨迹的线路已经集成到光耦合器封装部件中了。这也节省了附着有光耦合器封装部件的板上的空间。
图2-3示出了预备模制的引线框基片1,它被用于光耦合器封装部件中。它包括引线框2和塑封料3。引线框2可以包括芯片附着区域,两个或多个包括光接收器和光发射器的芯片被置于该芯片附着区域。诸如控制芯片等附加的芯片也可以被安装在引线框上。两个或多个引线可以从该芯片附着区域中延伸出来,并且可以形成引线框的各个接线端。“引线框”包括可能已经处理过(例如,通过蚀刻)或没有处理过的引线框结构。在其它情况下,可以使用其它类型的基片。
参照图4-5,引线框2是基片1的骨架结构。它具有复杂的半蚀刻图案2a、非蚀刻图案2b以及通孔或完全蚀刻图案2c,从而定义了基片1的功能焊点和锁定区域(以锁住塑封料3)。
引线框2可以包括任何合适的金属,并且可以具有任何合适的厚度。例如,高机械强度的铜合金是较佳的。引线框2可以在蚀刻或非蚀刻区域中具有约0.2毫米(8密耳)或更小的厚度。对于本领域的那些技术人员而言,许多蚀刻工艺都是已知的。引线框2也可以包括诸如Ni、Pd、Au或Ag等的镀层。
基片1的塑封料3形成了基片1的主体。它填充了引线框1的通孔2c和半蚀刻区域2a。在本示例中,基片1的非蚀刻区域2b并未用塑封料3来覆盖。
塑封料3可以包括聚合的和/或复合的材料,这些材料可能需要或可能不需要封胶后烘烤(post mold curing)。它可能包含环氧树脂、硬化剂、弹性体、非磷阻燃剂、润滑油、二氧化硅填充剂等。它可以具有均衡的粒子大小,以保证完全填充引线框2的半蚀刻区域。它也可以包含足够量的碳黑色素,以便有更好的激光标记对比度。构成塑封料3组成材料的均衡的材料也可以被用于防止基片扭曲变形。
在一些实施例中,可以通过使用狭带粘贴的方法来形成基片1。例如,可以将狭带附着到引线框2的非蚀刻焊点2b上,这样塑封料3(或成型坏料或成型毛边)并不占据基片1的功能焊点。为了增加基片1的机械强度,使引线框2未帖狭带的一侧注塑成型约0.1毫米。在其它实施例中,不存在注塑成型,并且塑封料3仅位于引线框2的空隙之内。基片1的厚度可以根据封装部件20的机械和物理要求而变化。
如图所示,基片1中的塑封料3定义了功能焊点。这些功能焊点是引线框2的非蚀刻区域2b。
在2002年8月30日提交的申请号为10/233,248的美国专利中,可以发现形成各种细节的附加基片,该专利整体引用在此作为参考。
参照图6,光耦合器封装部件可以被分成带有四个光耦合器(即光耦合器I-IV)的四个象限。光耦合器I占据象限I(101)。光耦合器II占据象限II(102)。光耦合器III占据象限III(103)。光耦合器IV占据象限IV(104)。
参照图6-7,基片1的功能焊点可以按下述来标记:
(a)光耦合器I 21的四个内部装配焊点是阴极I(或二极管芯片附着焊点I)4a、阳极I(或二极管焊接焊点I)5a、集电极I(或光电晶体管芯片附着焊点I)6a和发射器I(或光电晶体管焊接焊点I)7a;
(b)光耦合器II 22的四个内部装配焊点是阴极II(或二极管芯片附着焊点I)4b、阳极II(或二极管焊接焊点II)5b、集电极II(或光电晶体管芯片附着焊点II)6b和发射极II(或光电晶体管焊接焊点II)7b;
(c)光耦合器III 23的四个内部装配焊点是阴极III 4c、阳极III 5c、集电极III 6c和发射器III 7c;以及
(d)光耦合器IV 24的四个内部装配焊点是阴极IV 4d、阳极IV 5d、集电极IV 6d和发射极IV 7d。
基片1的非蚀刻功能焊点连接到焊盘以便于外围焊接球形附着。这些被分组并引出引线,从而构成具有共用端点焊盘的对称的封装基片1。这些外围的球形附着焊点被标记如下:
(e)光耦合器I和IV的阴极或二极管芯片附着焊点(4a、4d)被短接并且被连接到共用的阴极端点焊盘8a,并且位于象限I和IV的外边界处;
(f)光耦合器II和III的阴极或二极管芯片附着焊接焊点(4b、4c)被短接并且连接到共用的阴极端点焊盘8b,并且位于象限II和III的外边界处;
(g)所有光耦合器的阳极端点焊盘9a、9b、9c、9d都独立地位于各象限的外围角落处;
(h)各光耦合器的集电极端点焊盘10a、10b、10c、10d都独立地且横向地位于与阳极焊盘直接相反的位置;
(i)所有光耦合器的发射极或光电晶体管焊接焊点7a、7b、7c、7d都被短接并且朝着该基片的中心水平外围引线,从而产生用于发射极焊接球的两个对称的外围焊盘11。在所有的光耦合器中,阳极-阴极焊点与发射极-集电极焊点保持约0.5毫米的间隙。这将保证每一个光耦合器具有高电压击穿。
图7示出了包含四个光耦合器的光耦合器封装部件20,这四个光耦合器包括团形顶半球形21、22、23、24。团形顶部材料并不接触球形附着外围端点焊盘8a-8b、9a-9d、10a-10d(如图6所示)。
光耦合器封装部件20包括附着于基片1上的外部的外围焊接球25。外围球25附着到端点焊盘8a-8b、9a-9d、10a-10d、11上。这些球25充当光耦合器封装部件20到印刷电路板(PCB)31的紧密连接机构(参看图11)。焊接球25最好包括高熔点的无铅合金。
如图7所示,在所示的示例中,光耦合器封装部件20具有12个等间隔的外围焊接球25。封装部件外围球引出结构可能会根据特定的封装引脚引出要求和芯片而变化(基于内部装配焊点短接和接线端引线的相同概念)。尽管详细描述了焊接球,但是可以使用诸如铜柱等其它导电结构(例如,预先形成的或电镀的)。这些导电结构的高度大于光学封装部件中光接收器和光发射器的高度,这样便可以安装触发器。
参照图9和10,当正向电流加在光耦合器上时,LED芯片26产生光子,从而芯片26中的P-N结发出光。可以使用高度约9密耳或更低的LED芯片。
光电晶体管芯片27检测由LED芯片26发出的光并将它转换为电子,从而在光耦合器输出处产生了电流。光检测发生在其集电极-基极结处。可以使用高度约为8密耳的光电晶体管芯片。
参照图6、9和10,芯片附着材料(未示出)将各LED芯片26的背面接合到其指定的芯片附着焊点4a、4b、4c、4d。相似的是,它将各光电晶体管芯片27的背面接合到其指定的芯片附着焊点6a、6b、6c、6d。芯片附着材料可以是任何导电接合材料。这些示例包括填充有银的环氧树脂类、软的焊料等。在一些实施例中,可以使用芯片附着嵌条,并且可以控制它最大约为芯片高度的50%,从而使LED芯片26的侧面发出的光达到最多。
接合导线28将LED芯片26的阳极焊点连接到二极管焊接焊点5a、5b、5c、5d,从而使封装部件20的二极管组件的电路完整。相似的是,它们将光电晶体管芯片27连接到它们指定的焊接焊点7a、7b、7c、7d。接合导线28可以包括任何合适的可延展金属-Au、Cu、Al或这些金属的掺杂体、这些金属的合金等。推荐从基片起约14密耳的导线环。
通过使用透光且无瑕的凝胶材料29,将导线接合LED芯片和光电晶体管芯片组件耦合起来。耦合凝胶29的光学透明性允许LED26结中发出的光朝着光电晶体管27的感光结有效地转移。耦合凝胶29覆盖整个导线接合芯片组件,并且形成一个接近半球形的圆顶以使发出的光达到最大程度的透射。
用白色反射式团状顶部材料30来覆盖每一个导线接合LED和光电晶体管组件的透光半球形圆顶29,从而使一个光耦合器内部封装结构完整。团状顶部30(或反光材料)是一种能使所发出的光保持在该圆顶的限制范围之内的反光材料。该团状顶部涂层与圆顶形状一致,并且可以完全覆盖无瑕的耦合凝胶29(或透光材料)。它透光粘合来使该圆顶密封。该团状顶部材料30可以具有约0.2毫米的最小厚度。
光耦合器封装部件可以根据下面的步骤来制造。
首先,可以执行引线框成型过程。通过使用上述贴狭带的引线框,来执行引线框成型工艺。可以将一片狭带附着于引线框的非蚀刻焊点上,这样塑封料就不会占据接下来形成的基片的功能焊点。使引线框未贴狭带的侧面注塑成型,从而为基片增加机械强度。
第二,可以执行芯片附着过程。例如,通过使用带有导电性填充物和焊料的粘合剂,可以附着LED和光电晶体管芯片。根据所使用的粘合剂的类型,芯片附着固化可能需要或者可能不需要。
第三,可以执行导线接合过程以便在基片中芯片及其相应的焊点之间形成导电路径。例如,在一些实施例中,可以执行热声波(thermosonic)或超声波导线接合过程。
第四,可以执行圆顶涂覆和固化过程。可以使用任何合适的液体分配过程以便分配无瑕的耦合凝胶,从而形成透光的半球形圆顶。可以需要固化以改善耦合凝胶的物理特性。合适的圆顶涂覆材料包括硅树脂基材料,该材料可从Dow Corning和General Electric那里获得,尽管任何合适的厂商都可以使用。
第五,可以执行团块封顶和固化过程。可以使用任何合适的液体分配过程来进行不透明的团块封顶。根据所用材料的类型,可能需要或可能不需要固化。合适的反射式涂覆材料包括带有反射性色素的环氧基涂层,该反射性色素基于诸如氧化钛或其它金属氧化物等材料。它们可以从Epotek和Hysol处买到,尽管任何合适的厂商都可以使用。
第六,可以执行焊接沉积过程(例如,针对图中的焊接球25)。可以使用焊接球附着、熔解、球定位或球射击、球喷射和其它过程,以便将诸如焊料等导电性结构附着到基片上。在其它实施例中,导电性的柱(例如,铜柱)可以被置于该基片上,或可以被电镀到该基片上。
第七,可以执行焊料回流过程(如果使用了焊料)。在一些实施例中,可以使用对流或传导或辐射焊料回流过程。
第八,可以执行切割过程。切割过程包括刀片锯切、水喷射锯切、激光锯切等。切割过程将所以形成的基片彼此分开。
第九,可以执行电学测试。可以使用高电压测试和参数测试,以便将带有电学缺陷的任何封装部件剔除。
第十,可以执行封装部件标记过程。可以使用激光或焊点标记或其它过程来提供封装标识和定向。
在形成封装部件之后,可以如图11所示将它翻转过来并安装到印刷电路板上。可以使用常用的表面装配技术。
注意到,上述多个过程可以按上述顺序来执行,或者可以按不同的顺序来执行。
注意到,本发明并不限于上述较佳的实施例,并且很明显,在本发明的精神和范围之内,本领域的技术人员可以执行各种变化和修改。此外,本发明的任何一个或多个实施例都可以在不背离本发明的精神和范围的情况下而与本发明的一个或多个实施例相结合。
所有上述美国临时和非临时专利申请及出版物以其整体引用在此作为参考。它们都不被视为现有技术。
Claims (20)
1.一种光耦合器封装部件,包括:
(a)基片,所述基片包括引线框和塑封料;
(b)光发射器;
(c)光接收器,其中所述光发射器和所述光接收器电耦合到所述引线框;以及
(d)透光介质,所述透光介质被置于所述光发射器和所述光接收器之间。
2.如权利要求1所述的光耦合器封装部件,还包括多个耦合到所述引线框的导电结构,其中所述导电结构所具有的高度大于所述光接收器和所述光发射器的高度。
3.如权利要求2所述的光耦合器封装部件,其特征在于,所述导电结构是焊接结构。
4.如权利要求1所述的光耦合器封装部件,还包括用于将所述光接收器电耦合到所述引线框、并将所述光发射器电耦合到所述引线框的接合导线。
5.如权利要求1所述的光耦合器封装部件,其特征在于,所述引线框包括蚀刻部分和非蚀刻部分,并且其中所述蚀刻部分被所述塑封料所覆盖而所述非蚀刻部分没有被所述塑封料所覆盖。
6.如权利要求1所述的光耦合器封装部件,其特征在于,所述引线框包括铜。
7.如权利要求1所述的光耦合器封装部件,其特征在于,多个光耦合器位于所述基片上。
8.如权利要求所述的光耦合器封装部件,其特征在于,所述引线框在第一侧包括蚀刻部分和非蚀刻部分,并且其中所述蚀刻部分被所述塑封料所覆盖而所述非蚀刻部分没有被所述塑封料所覆盖,并且其中所述塑封料完全地覆盖了所述引线框的第二侧。
9.一种用于形成光耦合器封装部件的方法,所述方法包括:
(a)形成包括引线框和塑封料的基片;
(b)将光发射器和光接收器连接到所述基片上;以及
(c)在所述光发射器和所述光接收器之间沉积透光材料。
10.如权利要求9所述的方法,还包括:
在所述基片上形成多个导电结构,其中所述导电结构所具有的高度大于所述光发射器和所述光接收器的高度。
11.如权利要求9所述的方法,其特征在于,所述方法包括:在步骤(a)之前,蚀刻所述引线框。
12.如权利要求9所述的方法,其特征在于,所述引线框包括铜。
13.如权利要求9所述的方法,还包括将导线从所述光发射器和所述光接收器连接到所述引线框。
14.如权利要求9所述的方法,还包括在所述透光材料上沉积不透光的材料。
15.如权利要求9所述的方法,还包括将至少四个光发射器和至少四个光接收器安装到所述基片上。
16.一种光耦合器封装部件,它包括:
(a)基片;以及
(b)至少两个光发射器;
(c)至少两个光接收器;
(d)在相邻的光发射器和光接收器之间的透光介质;以及
(e)在所述透光介质上的反光材料,
其中所述光发射器和所述光接收器位于所述基片上。
17.如权利要求16所述的光耦合器封装部件,其特征在于,所述基片包括引线框,所述引线框包括蚀刻部分。
18.如权利要求16所述的光耦合器封装部件,其特征在于,所述基片包括引线框,所述引线框包括铜和塑封料。
19.如权利要求16所述的光耦合器封装部件,还包括所述基片上的包括MOSFET的芯片。
20.如权利要求1所述的光耦合器封装部件,还包括所述基片上的包括MOSFET的芯片。
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- 2005-02-17 DE DE112005000717T patent/DE112005000717T5/de not_active Withdrawn
- 2005-02-17 CN CN200580012042A patent/CN100590779C/zh not_active Expired - Fee Related
- 2005-02-17 CN CN2010100029444A patent/CN101893742B/zh not_active Expired - Fee Related
- 2005-02-17 WO PCT/US2005/005133 patent/WO2005102156A2/en active Application Filing
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Cited By (2)
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CN101657748B (zh) * | 2007-04-13 | 2013-01-16 | 费查尔德半导体有限公司 | 光耦合器封装 |
CN113540058A (zh) * | 2021-06-03 | 2021-10-22 | 华润微集成电路(无锡)有限公司 | 一种高耐压光耦封装产品及制作方法 |
Also Published As
Publication number | Publication date |
---|---|
WO2005102156A3 (en) | 2006-01-26 |
CN100590779C (zh) | 2010-02-17 |
TWI452715B (zh) | 2014-09-11 |
US7196313B2 (en) | 2007-03-27 |
US20050218300A1 (en) | 2005-10-06 |
JP2007531310A (ja) | 2007-11-01 |
WO2005102156A2 (en) | 2005-11-03 |
CN101893742B (zh) | 2013-12-18 |
CN101893742A (zh) | 2010-11-24 |
TW200605391A (en) | 2006-02-01 |
MY139480A (en) | 2009-10-30 |
DE112005000717T5 (de) | 2008-07-03 |
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