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CN1849052A - 电磁干扰屏蔽封装体及其制程 - Google Patents

电磁干扰屏蔽封装体及其制程 Download PDF

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CN1849052A
CN1849052A CNA2005100340377A CN200510034037A CN1849052A CN 1849052 A CN1849052 A CN 1849052A CN A2005100340377 A CNA2005100340377 A CN A2005100340377A CN 200510034037 A CN200510034037 A CN 200510034037A CN 1849052 A CN1849052 A CN 1849052A
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electronic component
crown cap
electromagnetic interference
substrate
packaging body
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孔小花
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Priority to CNA2005100340377A priority Critical patent/CN1849052A/zh
Priority to US11/322,870 priority patent/US7480153B2/en
Publication of CN1849052A publication Critical patent/CN1849052A/zh
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
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Abstract

一种电磁干扰(Electromagnetic Interference，EMI)屏蔽封装体包括一基板，其上设置有多个电子元件以及多个焊垫，所述电子元件包括需屏蔽的电子元件以及不需屏蔽的电子元件，所述焊垫设置于需屏蔽电子元件周围；一金属盖，该金属盖具有一底部和与其垂直的侧壁，该侧壁设置有多个焊垫，该金属盖放置在基板上，使得该金属盖的焊垫粘着基板上相对应的焊垫，且该金属盖遮盖上述需屏蔽电子元件；以及用于包覆上述电子元件、金属盖、电子元件与基板之间缝隙的塑封胶体。

Description

电磁干扰屏蔽封装体及其制程
【技术领域】
本发明涉及一种电子封装体及其制程，尤其涉及一种电磁干扰(Electromagnetic Interference，EMI)屏蔽封装体及其制程。
【背景技术】
在电子封装制程中，尤其是射频元件的电子封装中，其可靠性工作通常会受到电磁干扰的不利影响，这就需要设置电磁干扰屏蔽以有效抵制和消除不利影响。图1所示为传统电磁干扰屏蔽封装体1的剖视图，其中电子元件11a、11b与芯片12通过锡膏粘着在基板10上，芯片12通过金线13与基板10电气连接。由于电子元件11b与芯片12亦受电磁干扰影响，为了使其正常工作，则需要将其屏蔽。而电子元件11a，如：天线，不需要或不能被屏蔽。另，考虑到金线13的脆弱，所以通过点胶方式将胶体14覆盖在芯片12与金线13上，起到保护作用。完成点胶制程后，将金属盖15通过锡膏与基板10粘着在一起形成电磁干扰屏蔽封装体1。
图2所示为图1中传统电磁干扰屏蔽封装体1的俯视图，其中该金属盖15仅遮盖电子元件11b与芯片12，而电子元件11a裸露于空气中，该种外置金属盖15结构的电磁干扰屏蔽封装体1会导致电子元件11a易被氧化腐蚀，既而影响到其可靠性；其次，屏蔽封装体1采用锡膏作为粘合剂，由于其遇高温亦融化，粘着在基板10上的电子元件遇高温会引起其他不良影响，如：短路，则在客户端使用时对温度有所限制；再次，利用点胶方式去保护芯片12，制程复杂，速度较慢，综合成本较高。
为了解决上述问题，需要提供一种可靠性高，且综合成本较低的电磁干扰屏蔽封装体。
【发明内容】
本发明的主要目的在于提供一种可靠性高、体积小、制程简单、综合成本低的电磁干扰(Electromagnetic Interference，EMI)屏蔽封装体。
本发明的另一目的在于提供一种可靠性高、体积小、制程简单、综合成本低的电磁干扰屏蔽封装体的制程。
为了达到上述目的，本发明提供的电磁干扰屏蔽封装体包括：一基板，其上设置有多个电子元件以及多个焊垫，所述电子元件包括需屏蔽的电子元件以及不需屏蔽的电子元件，所述焊垫设置于需屏蔽电子元件周围；一金属盖，该金属盖具有一底部和与其垂直的侧壁，该侧壁设置有多个焊垫，该金属盖放置在基板上，使得该金属盖的焊垫粘着基板上相对应的焊垫，且该金属盖遮盖上述被屏蔽电子元件；以及用于包覆上述电子元件、金属盖、电子元件与基板之间缝隙的塑封胶体。
本发明提供的电磁干扰屏蔽封装体制程包括以下步骤：提供一基板，其上设置有多个电子元件以及多个焊垫，所述电子元件包括需屏蔽的电子元件以及不需屏蔽的电子元件，所述焊垫设置于需屏蔽电子元件周围；提供一金属盖，该金属盖具有一底部和与其垂直的侧壁，该侧壁上设置有多个焊垫；将该金属盖放置在基板上，使得该金属盖的焊垫粘着基板上相对应的焊垫，且盖金属盖遮盖上述被屏蔽电子元件；将塑封胶灌满上述电子元件、金属盖、电子元件与基板之间的缝隙并硬化该塑封胶，使其形成一塑封胶体。
与现有技术相比，本发明具有以下优点：采用将金属盖内置于塑封胶体中的屏蔽封装结构，不仅提高了产品的可靠性，而且缩短了制成时间，节约了综合成本。
【附图说明】
图1是习知电磁干扰屏蔽封装体的剖视图；
图2是习知电磁干扰屏蔽封装体的俯视图；
图3是本发明电磁干扰屏蔽封装体基板剖视图；
图4是本发明基板上金属盖后的剖视图；
图5是本发明基板上金属盖后的俯视图；
图6本发明金属盖的立体图；
图7本发明电磁干扰屏蔽封装体的剖视图。
【具体实施方式】
图3所示为本发明电磁干扰(Electromagnetic Interference，EMI)屏蔽封装体之基板10的剖视图。电子元件11a、11b以及芯片12通过粘合剂17与焊垫16粘着在一起，焊垫16设置于基板10上。在本发明的实施方式中，该粘合剂17可以是锡膏，亦可以是银胶。芯片12利用打线方式通过金线13与基板10电气连接。在本发明的其它实施方式中，芯片12可以通过其它方式与基板10电气连接，例如：覆晶(Flip Chip，FC)接合方式。在本实施方式中，电子元件11b与芯片12易受外界EMI影响，故需要一可屏蔽电磁干扰讯号的遮蔽体来保护其免受电磁干扰影响。而电子元件11a，如：天线，不需要或不能被屏蔽，须将其裸露于外。
图4所示为本发明中基板10上金属盖15后的剖视图，图5所示为本发明中基板10上金属盖15后的俯视图，同时参阅图6所示为金属盖15的立体图。金属盖15包括一底部152，该底部152上设置有多个孔150。四个与底部152垂直的侧壁151，侧壁151上设置多个焊垫16′，其与基板10上电子元件11b和芯片12周围焊垫16相对应。金属盖15与基板10通过焊垫16′与16相连接。为了保证金属盖15可以遮蔽电子元件11b和芯片12不受影响，侧壁151的高度应大于该二者的最大高度。
图7所示为本发明电磁干扰屏蔽封装体1的剖视图，在完成金属盖15与基板10粘着的制程后，将塑封胶18灌满整个屏蔽封装体1，用于包覆基板10上所有元件、金属盖15以及元件与基板10之间的缝隙。为了使塑封胶18可以充分较快地灌满金属盖15下所有敏感元件周围且漏磁最少，金属盖15上的孔150的孔径D≤1/20*λmin，其中λmin＝光速/电磁干扰波的最大频率。且根据多孔薄型屏蔽层效率计算公式SE＝20lg(f/σ)-10lgn可以计算出开孔数量n，其中SE为所需要的屏蔽效率，f为电磁干扰波的最大频率，σ为金属盖15所用材料的导电率，n为开孔数量。
在本发明的实施方式中，为了防止金属盖15内部的基板10与塑封胶18产生分层，则需在上金属盖15前后均加入电浆清洗制程，有效地去除基板10表面残留的有机物。塑封胶18将基板10上所有元件包覆在内，则该屏蔽封装体1既利用金属盖15保护电子元件11b与芯片12不受电磁干扰讯号辐射，又利用塑封胶18保护电子元件11a，防止其受空气氧化腐蚀。且在本发明的实施方式中，由于塑封胶18的熔点高于粘合剂17的熔点，故屏蔽封装体1在一定的温度下，电子元件11a、11b以及芯片12与基板10的粘合剂17会融化，而电子元件11a、11b以及芯片12周围的塑封胶18处于固态，则基板10上的元件不会因为温度的增加而引起其它不良影响。又本发明的实施方式中，采用压模塑封制程简单方便，节约了时间，降低了综合成本。

Claims (12)

1.一种电磁干扰(Electromagnetic Interference，EMI)屏蔽封装体包括一基板，其上设置有第一类电子元件、第二类电子元件和多个焊垫；一金属盖，该金属盖具有一底部和与其垂直的侧壁，该侧壁上设置有多个焊垫；该金属盖放置在基板上，使得该金属盖的焊垫粘着基板上相对应的焊垫，且金属盖遮盖上述第一类电子元件；其特征在于该屏蔽封装体还包括有：包覆上述第一类电子元件、第二类电子元件、金属盖、第一类电子元件以及第二类电子元件与基板之间缝隙的塑封胶体。
2.如权利要求1所述电磁干扰屏蔽封装体，其特征在于第一类电子元件为需屏蔽的电子元件。
3.如权利要求1所述电磁干扰屏蔽封装体，其特征在于第二类电子元件为无需屏蔽的电子元件。
4.如权利要求1所述电磁干扰屏蔽封装体，其特征在于金属盖上开有多个孔。
5.如权利要求1所述电磁干扰屏蔽封装体，其特征在于金属盖侧壁的高度大于第一类电子元件的最大高度。
6.一种电磁干扰屏蔽封装体制程，其特征在于包括如下步骤：
(a)提供一基板，其上设置有第一类电子元件、第二类电子元件以及多个焊垫，该焊垫设置于第一类电子元件周围；
(b)提供一金属盖，该金属盖具有一底部和与其垂直的侧壁，该侧壁上设置有多个焊垫；
(c)将该金属盖放置在基板上，使得该金属盖的焊垫粘着基板上相对应的焊垫，且该金属盖遮盖上述第一类电子元件；
(d)将塑封胶浇盖于上述第一类电子元件、第二类电子元件、金属盖之上并硬化该塑封胶，使其形成一塑封胶体。
7.如权利要求6所述电磁干扰屏蔽封装体制程，其特征在于第一类电子元件为需屏蔽的电子元件。
8.如权利要求6所述电磁干扰屏蔽封装体制程，其特征在于第二类电子元件为无需屏蔽的电子元件。
9.如权利要求6所述电磁干扰屏蔽封装体制程，其特征在于金属盖上开有多个孔。
10.如权利要求6所述电磁干扰屏蔽封装体制程，其特征在于金属盖侧壁的高度大于第一类电子元件的最大高度。
11.如权利要求9所述电磁干扰屏蔽封装体制程，其特征在于步骤(d)包括有将塑封胶灌满第一类电子元件以及第二类电子元件与基板之间的缝隙的步骤。
12.如权利要求6所述电磁干扰屏蔽封装体制程，其特征在于包括有电浆清洗基板步骤。
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