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CN1531090A - 半导体装置、电子设备及它们的制造方法，以及电子仪器 - Google Patents

半导体装置、电子设备及它们的制造方法，以及电子仪器 Download PDF

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Publication number
CN1531090A
CN1531090A CNA2004100397309A CN200410039730A CN1531090A CN 1531090 A CN1531090 A CN 1531090A CN A2004100397309 A CNA2004100397309 A CN A2004100397309A CN 200410039730 A CN200410039730 A CN 200410039730A CN 1531090 A CN1531090 A CN 1531090A
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China
Prior art keywords
carrier substrate
semiconductor chip
semiconductor
semiconductor device
addition
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CNA2004100397309A
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CN100342538C (zh
Inventor
青栁哲理
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Seiko Epson Corp
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Seiko Epson Corp
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Publication of CN100342538C publication Critical patent/CN100342538C/zh
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Abstract

可在抑制载体基板的挠曲的同时，实现不同种类芯片的3维安装结构。在通过ACF接合双面安装半导体芯片23a、23b的半导体组件PK11上，层叠引线接合连接堆叠结构的半导体芯片33a、33b的半导体组件PK12。

Description

半导体装置、电子设备及它们的制造方法，以及电子仪器
技术领域
本发明涉及一种半导体装置、电子设备、电子仪器、半导体装置的制造方法和电子设备的制造方法，尤其适用于半导体组件(封装)等的层叠结构。
背景技术
在现有的半导体装置中，为了实现半导体芯片安装时的空间节省，例如有专利文献1中公开的那样经载体基板进行3维安装半导体芯片的方法。
专利文献1：特开平10-284683号公报
但是，在经载体基板进行3维安装半导体芯片的方法中，由于载体基板表面的线性膨胀系数不同，所以载体基板的挠曲大。
发明内容
因此，本发明的目的在于提供一种在抑制载体基板的挠曲的同时、可实现不同种类芯片的3维安装结构的半导体装置、电子设备、电子仪器、半导体装置的制造方法和电子设备的制造方法。
为了解决上述问题，根据本发明之一形态的半导体装置，其特征在于，具备：第1载体基板；面朝下安装在所述第1载体基板上的第1半导体芯片；面朝下安装在所述第1载体基板背面的第2半导体芯片；第2载体基板；装载在所述第2载体基板上的第3半导体芯片；和突出电极，以连接所述第2载体基板与所述第1载体基板，使所述第2载体基板保持在所述第1半导体芯片上。
由此，可在第1载体基板的表里设置材料物性相等的半导体芯片，可降低第1载体基板的表里线膨胀系数的差异。因此，可在抑制第1载体基板挠曲的同时，在第1载体基板上层叠第2载体基板，可在确保第1载体基板与第2载体基板的连接可靠性的同时，实现不同种类芯片的3维安装结构。
根据本发明之一形态的半导体装置，其特征在于，将所述第2载体基板固定在第1载体基板上，以跨在所述第1半导体芯片上。
由此，可重叠配置第1半导体芯片与第3半导体芯片，使安装多个半导体芯片时的安装面积降低，可实现半导体芯片安装时的空间节省。
另外，根据本发明之一形态的半导体装置，其特征在于，具备密封所述第3半导体芯片的密封件。
由此，可保护第3半导体芯片不被腐蚀或破坏等，可使第3半导体芯片的可靠性提高。
另外，根据本发明之一形态的半导体装置，其特征在于，所述密封件是模制树脂。
由此，可使包含第2载体基板的不同种类组件层叠在第1载体基板上，即使在半导体芯片的种类不同的情况下，也可实现半导体芯片的3维安装结构。
另外，根据本发明之一形态的半导体装置，其特征在于，所述密封件的侧壁与所述第2载体基板的侧壁位置一致。
由此，可在抑制在第1载体基板上层叠第2载体基板时的高度增大的同时，用密封第3半导体芯片的密封件来增强第2载体基板的单面整体，并可以不进行密封件的单元分割就可密封第3半导体芯片，使装载在第2载体基板上的第3半导体芯片的装载面积增大。
另外，根据本发明之一形态的半导体装置，其特征在于，所述第1半导体芯片和所述第2半导体芯片，通过压接接合连接于所述第1载体基板上。
由此，可实现将第1半导体芯片和第2半导体芯片连接在第1载体基板上时的低温化，可降低实际使用时的第1载体基板的挠曲。
另外，根据本发明之一形态的半导体装置，其特征在于，包含所述第1载体基板的半导体装置与包含所述第2载体基板的半导体装置在相等温度下的弹性系数不同。
由此，可由一个载体基板来抑制在另一载体基板中产生的挠曲，可使第1载体基板与第2载体基板之间的连接可靠性提高。
另外，根据本发明之一形态的半导体装置，其特征在于，装载所述第1半导体芯片和所述第2半导体芯片的第1载体基板是倒装片安装的球状栅格阵列，装载所述第3半导体芯片的第2载体基板是模制密封的球状栅格阵列或芯片尺寸组件。
由此，可抑制3维安装结构的高度增大，使不同种类的组件层叠，即使在半导体芯片的种类不同的情况下，也可实现半导体芯片安装时的空间节省。
另外，根据本发明之一形态的半导体装置，其特征在于，所述第3半导体芯片包含层叠多个芯片的结构。
由此，可在第1半导体芯片上层叠多个种类或尺寸不同的第3半导体芯片，可具有各种功能，同时，可实现半导体芯片安装时的空间节省。
另外，根据本发明之一形态的半导体装置，其特征在于，所述第3半导体芯片包含将多个芯片并列配置在第2载体基板上的结构。
由此，可在抑制第3半导体芯片层叠时的高度增大的同时，将多个第3半导体芯片配置在第1半导体芯片上，在抑制3维安装时的连接可靠性恶化的同时，实现半导体芯片安装时的空间节省。
另外，根据本发明之一形态的半导体装置，其特征在于，具备第1载体基板；面朝下安装在所述第1载体基板表面和背面的至少一方的面上的第1半导体芯片；第2载体基板；装载在所述第2载体基板上的第2半导体芯片；装载在所述第2载体基板的背面的第3半导体芯片；和连接所述第2载体基板与所述第1载体基板的突出电极。
由此，可在第2载体基板的表里设置材料物性相等的半导体芯片，可降低第2载体基板的表里线膨胀系数的差异。因此，可在抑制第2载体基板挠曲的同时，在第1载体基板上层叠第2载体基板，可在确保第1载体基板与第2载体基板的连接可靠性的同时，实现不同种类芯片的3维安装结构。
另外，根据本发明之一形态的半导体装置，其特征在于，具备载体基板；面朝下安装在所述载体基板上的第1半导体芯片；面朝下安装在所述第1载体基板背面的第2半导体芯片；在电极衬垫的形成面上形成再配置配线层的第3半导体芯片；和突出电极，以连接所述第3半导体芯片与所述载体基板，使所述第3半导体芯片保持在所述第1半导体芯片上。
由此，即使在半导体芯片的种类或尺寸不同的情况下，也不会使载体基板插在第1半导体芯片与第3半导体芯片之间，可在第1半导体芯片上倒装片安装第3半导体芯片，同时，可在第1载体基板的背面分别设置材料物性相等的第1和第2半导体芯片，可降低第1载体基板的表里线膨胀系数的差异。
因此，可在抑制第1载体基板的挠曲的同时，在第1载体基板上层叠第3半导体芯片，在确保第3半导体芯片与第1载体基板的连接可靠性的同时，实现半导体芯片安装时的空间节省。
另外，根据本发明之一形态的电子设备，其特征在于，具备第1载体基板；装载在所述第1载体基板上的第1电子零件；装载在所述第1载体基板的背面的第2电子零件；第2载体基板；装载在所述第2载体基板上的第3电子零件；突出电极，以连接所述第2载体基板与所述第1载体基板，使所述第2载体基板保持在所述第1电子零件上；和密封所述第3电子零件的密封件。
由此，可在抑制第1载体基板的挠曲的同时，在第1电子零件上层叠包装不同的第3电子零件，可在确保不同组件间的连接可靠性的同时，实现不同种类部件的3维安装结构。
另外，根据本发明之一形态的电子仪器，其特征在于，具备第1载体基板；装载在所述第1载体基板上的第1半导体芯片；装载在所述第1载体基板背面的第2半导体芯片；第2载体基板；装载在所述第2载体基板上的第3半导体芯片；突出电极，以连接所述第2载体基板与所述第1载体基板，使所述第2载体基板保持在所述第1半导体芯片上；密封所述第3半导体芯片的密封件；和安装所述第1载体基板的母基板。
由此，可在抑制第1载体基板的挠曲的同时，在第1半导体芯片上层叠包装不同的第3半导体芯片，可在确保不同种类组件间的连接可靠性的同时，实现不同种类芯片的3维安装结构。
另外，根据本发明之一形态的半导体装置的制造方法，其特征在于，具备如下工序：即，将第1半导体芯片面朝下安装在第1载体基板上的工序；将第2半导体芯片面朝下安装在所述第1载体基板的背面的工序；将第3半导体芯片安装在第2载体基板上的工序；在所述第2载体基板中形成突出电极的工序；用密封树脂密封安装在所述第2载体基板上的第3半导体芯片的工序；和经所述突出电极来连接所述第2载体基板与所述第1载体基板，使所述第2载体基板保持在所述第1半导体芯片上的工序。
由此，可在第1载体基板的背面分别设置第1和第2半导体芯片的状态下，在第1载体基板上层叠第2载体基板。因此，可在抑制第1载体基板的挠曲的同时，在第1半导体芯片上层叠包装不同的第3半导体芯片，可在确保不同组件间的连接可靠性的同时，实现不同种类芯片的3维安装结构。
另外，根据本发明之一形态的半导体装置的制造方法，其特征在于，由所述密封树脂密封所述第3半导体芯片的工序具备：由密封树脂一体模制成形安装在所述第2载体基板上的多个第3半导体芯片的工序；和对每个所述第3半导体芯片切断通过所述密封树脂模制成形的所述第2载体基板的工序。
由此，可对各个第3半导体芯片单元分割密封树脂，用密封树脂来密封第3半导体芯片，同时，可用密封树脂来增强第2载体基板的单面整体。
因此，即使在第3半导体芯片的种类或尺寸不同的情况下，也可通用模制成形时的模具，可提高密封树脂工序的效率，同时，因为不需单元分割用的空间，所以可使装载在第2载体基板上的第3半导体芯片的装载面积增大。
另外，根据本发明之一形态的电子设备的制造方法，其特征在于，具备如下工序：即，将第1电子零件面朝下安装在第1载体基板上的工序；将第2电子零件面朝下安装在所述第1载体基板的背面的工序；将第3电子零件安装在第2载体基板上的工序；在所述第2载体基板中形成突出电极的工序；用密封树脂密封安装在所述第2载体基板上的第3电子零件的工序；和经所述突出电极来连接所述第2载体基板与所述第1载体基板，使所述第2载体基板保持在所述第1电子零件上的工序。
由此，可在第1载体基板的表背面分别设置第1和第2电子零件的状态下，在第1载体基板上层叠第2载体基板。因此，可在抑制第1载体基板的挠曲的同时，在第1电子零件上层叠包装不同的第3电子零件，可在确保不同种类组件间的连接可靠性的同时，实现不同种类部件的3维安装结构。
附图说明
图1是表示根据实施方式1的半导体装置的结构的截面图。
图2是表示根据实施方式2的半导体装置的结构的截面图。
图3是表示根据实施方式3的半导体装置的结构的截面图。
图4是表示根据实施方式4的半导体装置的制造方法的截面图。
图5是表示根据实施方式4的半导体装置的制造方法的截面图。
图6是表示根据实施方式5的半导体装置的制造方法的截面图。
图7是表示根据实施方式6的半导体装置的结构的截面图。
图8是表示根据实施方式7的半导体装置的结构的截面图。
图中，
21、31、41、51、61、61a～61c、71、81、101、111、201、321、331--载体基板，22a、22c、32a、32c、42a、42c、52a、52c、72a、72b、82、102a、102c、112a、112c、202a、202c、322a、322c、332a、332c-岸面，22b、32b、42b、52b、102b、112b、202b、322b、332b-内部配线，23a、23b、33a、33b、43a、43b、53a、53b、62a～62c、73a、73b、103a、103b、113a～113c、203a、203b、211、323、333a～333c-半导体芯片，24a、24b、26、36、44a、44b、46、55a、56、65a～65c、74a、74b、77、83、104a、104b、121、123、204a、204b、206、218、324、326、334c、336-突出电极，25a、25b、45a、45b、54a、75a、75b、105a、105b、205a、205b、325、335c-各向异性导电片，34a、34b、54b、334a、334b-粘接层，35a、35b、55b、63a～63c、335a、335b-导电性引线，37、57、64、64a～64c、84、120a、120b、122、337-密封树酯，76-焊剂，78-隔板，114a～114c、212-电极衬垫，115a～115c、117a～117c、213-绝缘膜，116a～116c-贯通孔，118a～118c-导电膜，119a～119c-贯通电极，214-应力缓和层，215-再配置配线，216-焊料抗蚀剂膜层，217-开口部，PK11、PK12、PK21、PK22、PK31、PK32、PK41、PK42、PK51、PK52、PK61、PK62-半导体组件
具体实施方式
下面，参照附图来说明根据本发明实施方式的半导体装置、电子设备和其制造方法。
图1是表示根据本发明实施方式1的半导体装置的结构的截面图。在该实施方式1中，在通过ACF接合双面安装半导体芯片(或半导体压模)23a、23b的半导体组件PK11上，层叠引线接合连接堆叠结构的半导体芯片(或半导体压模)33a、33b的半导体组件PK12。
图1中，在半导体组件PK11中设置载体基板21，在载体基板21的两个面中分别形成岸面22a、22c，同时，在载体基板21内形成内部配线22b。另外，在载体基板21的背面中分别倒装片安装半导体芯片23a、23b，在半导体芯片23a、23b中分别设置用于倒装片安装的突出电极24a、24b。另外，分别设置在半导体芯片23a、23b中的突出电极24a、24b分别经各向异性导电片25a、25b分别ACF((An isotropic ConductiveFilm)接合在岸面22c、22a上。另外，在设置在载体基板21背面的岸面22a上，设置用于将载体基板21安装在母基板上的突出电极26。
这里，通过在载体基板21的背面分别装载半导体芯片23a、23b，可降低载体基板21的背面的线膨胀系数的差异，降低载体基板21的挠曲。另外，通过用ACF接合将半导体芯片23a、23b安装在载体基板21上，不需引线接合或模制密封用的空间，可实现3维安装时的空间节省，同时，可实现将半导体芯片23接合在载体基板21上时的低温化，可降低实际使用时的载体基板21的挠曲。
另外，最好装载在载体基板21背面的半导体芯片23a、23b的厚度和尺寸相等，但半导体芯片23a、23b的厚度或尺寸也可不同。
另一方面，在半导体组件PK12中设置载体基板31，在载体基板31的两个面中分别形成岸面32a、32c，同时，在载体基板31内形成内部配线32b。另外，在载体基板31上经粘接层34a面朝上安装半导体芯片33a，半导体芯片33经导电性引线35a引线接合连接于岸面32c上。并且，在半导体芯片33a上，避开导电性引线35a，面朝上安装半导体芯片33b，半导体芯片33b经粘接层34b固定在半导体芯片33a上，同时，经导电性引线35b引线接合连接于岸面32c上。
另外，在设置在载体基板31背面的岸面32a上，设置将载体基板31安装在载体基板21上的突出电极36，使载体基板31保持在半导体芯片23a上。这里，避开半导体芯片23a的装载区域来配置突出电极36，例如可将突出电极36配置在载体基板31背面的周围。另外，通过使突出电极36与设置在载体基板21上的岸面22c接合，可将载体基板31安装在载体基板21上。
由此，可在抑制载体基板21的挠曲的同时，在半导体芯片23a、23b上层叠包装不同的半导体芯片33a、33b。因此，在可确保载体基板21、31间的连接可靠性的同时，层叠不同种类组件PK11、PK12，可实现不同种类的半导体芯片23a、23b、33a、33b的3维安装结构。
另外，用密封树脂37来密封半导体芯片33a、33b，密封树脂37例如可通过使用环氧树脂等热固化性树脂的模制成形等来形成。
这里，通过模制成形在半导体芯片33a、33b的安装面侧的载体基板31的单面整体中形成密封树脂37，即使在载体基板31上安装各种半导体芯片33a、33b的情况下，也可能用模制成形时的模具，提高密封树脂工序的效率，同时，因为不需要单元分割密封树脂37的空间，所以可使装载在载体基板31上的半导体芯片33a、33b的装载面积增大。
另外，作为载体基板21、31，例如可使用双面基板、多层配线基板、内建基板、带状基板或薄膜基板等，作为载体基板21、31的材质，例如可使用聚酰亚胺树脂、玻璃环氧树脂、BT树脂、芳族聚酰胺与环氧树脂的合成、或陶瓷等。另外，作为突出电极24a、24b、26、36，例如可使用由Au突块、焊锡材料等覆盖的Cu突块或Ni突块、或焊锡球等。这里，作为突出电极26、36，例如由于使用焊锡球，通过使用能用的BGA，可层叠不同种类组件PK11、PK12彼此，可能采用生产线。另外，作为导电性引线35a、35b，例如可使用Au引线或Al引线等。另外，在上述实施方式中，说明了为了将载体基板31安装在载体基板21上，而在载体基板31的岸面32a上设置突出电极36的方法，但也可将突出电极36设置在载体基板21的岸面22c上。
另外，在上述实施方式中，说明了通过ACF接合将半导体芯片23安装在载体基板11上的方法，但例如也可使用NCF(Nonconductive Film)接合、ACP(An isotropic Conductive Paste)接合、NCP(NonconductivePaste)接合等其它粘接剂接合，或使用焊锡接合或合金接合等金属接合。并且，在上述实施方式中，举例说明了在载体基板11的表背面上仅分别安装1个半导体芯片23a、23b的方法，但也可在载体基板21的表背面上分别安装多个半导体芯片。
图2是表示根据实施方式2的半导体装置的结构的截面图。在实施方式2中，在通过ACF接合双面安装半导体芯片43a、43b的半导体组件PK21上，层叠分别倒装片安装和引线接合连接堆叠结构的半导体芯片53a、53b的半导体组件PK22。
图2中，在半导体组件PK21中设置载体基板41，在载体基板41的两个面中分别形成岸面42a、42c，同时，在载体基板41内形成内部配线42b。另外，在载体基板41的表背面中分别倒装片安装半导体芯片43a、43b，在半导体芯片43a、43b中分别设置用于倒装片安装的突出电极44a、44b。另外，分别设置在半导体芯片43a、43b中的突出电极44a、44b分别经各向异性导电片45a、45b分别ACF接合在岸面42c、42a上。另外，在设置在载体基板41背面的岸面42a上，设置用于将载体基板41安装在母基板上的突出电极46。
这里，通过在载体基板41的表背面分别装载半导体芯片43a、43b，可降低载体基板41的表背面的线膨胀系数的差异，降低载体基板41的挠曲。另外，通过用ACF接合将半导体芯片43a、43b安装在载体基板41上，不需引线接合或模制密封用的空间，可实现3维安装时的空间节省，同时，可实现将半导体芯片43a、43b接合在载体基板41上时的低温化，可降低实际使用时的载体基板41的挠曲。
另一方面，在半导体组件PK22中设置载体基板51，在载体基板51的两个面分别形成岸面52a、52c，同时，在载体基板51内形成内部配线52b。另外，在载体基板51上面朝上安装半导体芯片53a，在半导体芯片53a上设置用于倒装片安装的突出电极55a。另外，设置在半导体芯片53a上的突出电极55a经各向异性导电片54aACF接合在岸面52c上。并且，在半导体芯片53a上，面朝上安装半导体芯片53b，半导体芯片53b经粘接层54b固定在半导体芯片53a上，同时，经导电性引线55b引线接合连接于岸面52c上。
这里，通过在面朝下安装的半导体芯片53a上面朝上安装半导体芯片53b，可不插入载体基板地在半导体芯片53a上层叠尺寸与半导体芯片53a相等或比其大的半导体芯片53b，可缩小安装面积。
另外，在设置在载体基板51背面的岸面52a上，设置将载体基板51安装在载体基板41上的突出电极56，使载体基板51保持在半导体芯片43a上。这里，避开半导体芯片43a的装载区域来配置突出电极56，例如可将突出电极56配置在载体基板51背面的周围。另外，通过使突出电极56与设置在载体基板41上的岸面42c接合，可将载体基板51安装在载体基板41上。
由此，可在抑制载体基板41的挠曲的同时，在半导体芯片43上层叠包装不同的半导体芯片53a、53b。因此，在可确保载体基板41、51间的连接可靠性的同时，层叠不同种类组件PK11、PK12，可实现不同种类的半导体芯片43a、43b、53a、53b的3维安装结构。
另外，作为突出电极46、56，例如可使用焊锡球。由此，通过使用能用的BGA，可层叠不同种类组件PK11、PK12彼此，可能采用生产线。
另外，用密封树脂57来密封半导体芯片53a、53b，密封树脂57例如可通过使用环氧树脂等热固化性树脂的模制成形等来形成。
这里，通过模制成形在半导体芯片53a、53b的安装面侧的载体基板51的单面整体中形成密封树脂57，即使在载体基板51上安装各种半导体芯片53a、53b的情况下，也可能用模制成形时的模具，提高密封树脂工序的效率，同时，因为不需要单元分割密封树脂57的空间，所以可使装载在载体基板51上的半导体芯片53a、53b的装载面积增大。
图3是表示根据实施方式3的半导体装置的结构的截面图。在实施方式3中，在由密封树脂64一体模制成形多个半导体芯片62a～62c之后，通过切断成每个半导体芯片62a～62c，在分别安装半导体芯片62a～62c的载体基板61a～61c的单面整体中分别形成密封树脂64a～64c。
图3(a)中，在载体基板61中设置装载多个半导体芯片62a～62c的装载区域。另外，将多个半导体芯片62a～62c安装在载体基板61上，分别经导电性引线63a～63c引线接合连接在载体基板61上。另外，除引线接合连接半导体芯片62a～62c的方法外，也可将半导体芯片62a～62c倒装片安装在载体基板61上，或将半导体芯片62a～62c的层叠结构安装在载体基板61上。
接着，如图3(b)所示，由密封树脂64一体模制成形安装在载体基板61上的多个半导体芯片62a～62c。这里，通过由密封树脂64一体模制成形多个半导体芯片62a～62c，即使在载体基板61上安装各种半导体芯片62a～62c的情况下，也可通用模制成形时的模具，可提高密封树脂工序的效率，同时，因为不需要单元分割密封树脂64的空间，所以可使装载在载体基板61上的半导体芯片62a～62c的装载面积增大。
接着，如图3(c)所示，在各载体基板61a～61c的背面形成焊锡球等突出电极65a～65c。另外，如图3(d)所示，通过每个各半导体芯片62a～62c切断载体基板61和密封树脂64，向分别由密封树脂64a～64c密封的载体基板61a～61c分割半导体芯片62a～62c。
这里，通过一体切断载体基板61及密封树脂64，可在半导体芯片62a～62c的安装面侧的载体基板61a～61c的单面整体中分别形成密封树脂64a～64c。因此，可抑制制造工序的复杂化，同时，可使突出电极65a～65c的配置区域的刚性提高，可使载体基板61a～61c的挠曲降低。另外，也可在切断成各个片后形成突出电极65a～65c。
图4、图5是表示根据实施方式4的半导体装置的制造方法的截面图。另外，该实施方式4是在通过ACF接合双面安装半导体芯片73a、73b的半导体组件PK31上层叠由密封树脂84密封的半导体组件PK32的。
图4(a)中，设置载体基板71，在载体基板71的两个面上分别形成岸面72a、72b。另外，在载体基板71的背面分别粘贴各向异性导电片75a、75b，使隔板78粘贴在各向异性导电片75b上。另外，隔板78例如最好由PET等构成。
接着，如图4(b)所示，边进行半导体芯片73a的定位，边将半导体芯片73a压在各向异性导电片75a上。另外，当对半导体芯片73a施压时，如图4(c)所示，剥离各向异性导电片75b上的隔板78。另外，如图(d)所示，边进行半导体芯片73b的定位，边在各向异性导电片75b上压着半导体芯片73b。
另外，一旦将半导体芯片73a、73b分别压着在各向异性导电片75a、75b上，则边加热临时压着半导体芯片73a、73b的载体基板71，边从上下施加负荷。另外，如图4(e)所示，分别经突出电极74a、74b使半导体芯片73a、73b，ACF接合在载体基板71上，制造双面安装半导体芯片73a、73b的半导体组件PK31。
接着，在图5(a)中，在半导体组件PK32中设置载体基板81，在载体基板81的背面形成岸面82，在岸面82上设置焊锡球等的突出电极83。另外，在载体基板81上安装半导体芯片，用密封树脂84来密封安装半导体芯片的载体基板81的单面整体。另外，也可在载体基板81上安装引线接合连接的半导体芯片，或倒装片安装半导体芯片，或安装半导体芯片的层叠结构。
另外，在半导体组件PK31上层叠半导体组件PK32的情况下，在载体基板71的岸面72b上提供焊剂76。另外，也可在载体基板71的岸面72b上提供焊锡膏来代替焊剂76。
接着，如图5(b)所示，在半导体组件PK31上安装半导体组件PK32，通过进行回流处理，使突出电极83接合在岸面72b上。
接着，如图5(c)所示，在设置在载体基板71的背面的岸面72a上，形成将载体基板71安装在母基板上的突出电极77。
图6是表示根据实施方式5的半导体装置的制造方法的截面图。另外，该实施方式5，在将半导体芯片103a、103b倒装片安装在两个面上的载体基板101上，使3维安装堆叠结构的半导体芯片113a～113c。
图6中，在半导体组件PK41中设置载体基板101，在载体基板101的两个面中分别形成岸面102a、102c，同时，在载体基板101内形成内部配线102b。另外，在载体基板101的两个面中分别倒装片安装半导体芯片103a、103b，在半导体芯片103a、103b中分别设置用于倒装片安装的突出电极104a、104b。
另外，分别设置在半导体芯片103a、103b中的突出电极104a、104b分别经各向异性导电片105a、105b分别ACF接合在岸面102c、102a上。另外，在半导体芯片103a、103b安装在载体基板101上的情况下，作使用ACF接合的方法外，还可使用NCF接合等其它粘接剂接合，或使用焊锡接合或合金接合等金属接合。另外，在设置在载体基板101背面的岸面102a上，设置将载体基板101安装在母基板上的突出电极106。这里，通过在载体基板101的背面分别装载半导体芯片103a、103b，可降低载体基板101背面的线膨胀系数的差异，可降低载体基板101的挠曲。
另一方面，在半导体组件PK42中设置载体基板111，在载体基板111的两个面中分别形成岸面112a、112c，同时，在载体基板111内形成内部配线112b。
另外，在半导体芯片113a～113c中分别设置电极衬垫114a～114c，各电极衬垫114a～114c露出，分别设置绝缘膜115a～115c。另外，在半导体芯片113a～113c中，例如对应于各电极衬垫114a～114c的位置，分别形成贯通孔116a～116c，在贯通孔116a～116c内，分别经绝缘膜117a～117c和导电膜118a～118c，分别形成贯通电极119a～119c。
另外，形成贯通电极119a～119c的半导体芯片113a～113c分别经贯通电极119a～119c层叠，分别向半导体芯片113a～113c之间的间隙中注入树脂120a、120b。
另外，在形成于半导体芯片113a中的贯通电极119a上，设置倒装片安装半导体芯片113a～113c的层叠结构的突出电极121。另外，在设置在载体基板111上的岸面112c上接合突出电极121的同时，用密封树脂122来密封安装在载体基板111上的半导体芯片113a的表面，将半导体芯片113a～113c的层叠结构安装在载体基板111上。
另外，在设置在载体基板111背面的岸面112a上，设置将载体基板111安装在载体基板101上的突出电极123，使载体基板111保持在半导体芯片103a上。
这里，突出电极123避开半导体芯片103a的装载区域配置，例如可在载体基板111的周围配置突出电极123。另外，通过使突出电极123接合在设置在载体基板101上的岸面102c上，可将载体基板111安装在载体基板101上。
由此，可在抑制载体基板101的挠曲的同时，将半导体芯片111a～111c的层叠结构安装在半导体芯片103a上。
因此，可在确保载体基板101、111之间的连接可靠性的同时，层叠不同种类组件PK41、PK42，可在抑制层叠时的高度增大的同时，实现不同种类半导体芯片103a、103b、113a～113c的3维安装结构。
另外，作为突出电极104a、104b、106、121、123，例如可使用由Au突块、由焊锡材料等覆盖的Cu突块或Ni突块、或焊锡球等。另外，在上述实施方式中，说明了将半导体芯片113a～113c的3层结构安装在载体基板111上的方法，但安装在载体基板111上的半导体芯片的层叠结构也可以是2层或4层以上。
图7是表示根据实施方式6的半导体装置的结构的截面图。另外，本实施方式6是在将半导体芯片203a、203b倒装片安装在两个面上的载体基板201上3维安装W-CSP(晶片等级芯片尺寸组件)。
图7中，在半导体组件PK51中设置载体基板201，在载体基板201的两个面中分别形成岸面202a、202c，同时，在载体基板201内形成内部配线202b。另外，在载体基板201的两个面中分别倒装片安装半导体芯片203a、203b，在半导体芯片203a、203b中分别设置用于倒装片安装的突出电极204a、204b。
另外，分别设置在半导体芯片203a、203b中的突出电极204a、204b分别经各向异性导电片205a、205b分别ACF接合在岸面202c、202a上。另外，在设置在载体基板201背面的岸面202a上，设置将载体基板201安装在母基板上的突出电极206。这里，通过在载体基板201的背面分别装载半导体芯片203a、203b，可降低载体基板201背面的线膨胀系数的差异，可降低载体基板201的挠曲。
另一方面，在半导体组件PK52中设置载体基板211，在半导体芯片211中设置电极衬垫212，同时，电极衬垫212露出，设置绝缘膜213。另外，在半导体芯片211上，露出电极衬垫212，形成应力缓和层214，在电极衬垫212上形成在应力缓和层214上延伸的再配置配线215。另外，在再配置配线215上形成焊料抗蚀剂膜216，在焊料抗蚀剂膜216中形成使再配置配线215在应力缓和层214上露出的开口部217。另外，在经开口部217露出的再配置配线215上，设置将半导体芯片211面朝下安装在载体基板201上的突出电极218，使半导体组件PK52保持在半导体芯片203a上。
这里，突出电极218避开半导体芯片203a的装载区域配置，例如可在半导体芯片211的周围配置突出电极218。另外，通过将突出电极218接合在设置在载体基板201上的岸面202c上，可将半导体组件PK52安装在载体基板201上。
由此，可在抑制载体基板201的挠曲的同时，在将半导体芯片203a、203b倒装片安装在两个面上的载体基板201上层叠W-CSP。因此，即使在半导体芯片203a、203b、211的种类或尺寸不同的情况下，也可不在半导体芯片203、211间插入载体基板，在半导体芯片203上3维安装半导体芯片211，同时，可使载体基板201、211之间的连接可靠性提高，抑制3维安装的半导体芯片203a、203b、211的可靠性恶化，同时，可实现半导体芯片203a、203b、211安装时的空间节省。
另外，在将半导体组件PK52安装在载体基板201上的情况下，例如可使用ACF接合或NCF接合等粘接剂接合，也可使用焊锡接合或合金接合等金属接合。另外，作为突出电极204a、204b、206、218，例如可使用由Au突块、焊锡材料等覆盖的Cu突块或Ni突块、或焊锡球等。另外，在上述实施方式中，举例说明了在倒装片安装在载体基板201上的1个半导体芯片203a上安装半导体组件PK52的方法，但也可在倒装片安装在载体基板201上的多个半导体芯片上安装半导体组件PK52。
图8是表示根据实施方式7的半导体装置的结构的截面图。该实施方式7是在通过ACF接合安装半导体芯片323的半导体组件PK61上，在表面安装堆叠结构的半导体芯片333a、333b的同时，层叠在背面安装半导体芯片333c的半导体组件PK62。
图8中，在半导体组件PK61中设置载体基板321，在载体基板321的两个面中分别形成岸面322a、322c，同时，在载体基板321内形成内部配线322b。另外，在载体基板321的背面倒装片安装半导体芯片323，在半导体芯片，323中设置用于倒装片安装的突出电极324。另外，设置在半导体芯片323中的突出电极324经各向异性导电片325 ACF接合在岸面322a上。另外，在设置在载体基板321背面的岸面322a上，设置将载体基板321安装在母基板上的突出电极326。
这里，通过ACF接合将半导体芯片323安装在载体基板321上，由此不必用于引线接合或模制密封的空间，可实现3维安装时的空间节省，同时，可实现将半导体芯片323安装在载体基板321上时的低温化，可降低实际使用时载体基板321的挠曲。
另一方面，在半导体组件PK62中设置载体基板331，在载体基板331的两个面中分别形成岸面322a、322c，同时，在载体基板331内形成内部配线332b。另外，在载体基板331经粘接层334a面朝上安装半导体芯片333a，半导体芯片333经导电性引线335a引线接合连接在岸面332c上。并且，在半导体芯片333a上，避开导电性引线335a，面朝上安装半导体芯片333b，半导体芯片333b经粘接层334b固定在半导体芯片333a上，同时，经导电性引线335b引线接合连接在岸面332c上。
另外，在载体基板331的背面，倒装片安装半导体芯片333c，在半导体芯片333c中，设置用于倒装片安装的突出电极334c。另外，设置在半导体芯片333c中的突出电极334c经各向异性导电片325c ACF接合在岸面332a上。并且，在设置在载体基板331背面的岸面332a上，设置将载体基板331安装在载体基板321上的突出电极336。另外，通过使突出电极336接合在设置在载体基板321上的岸面322c上，可将载体基板31安装在载体基板321上。
这里，通过在载体基板301的表面装载半导体芯片333a、333b，同时，在载体基板331的背面装载半导体芯片333c，可降低载体基板331背面的线膨胀系数的差异，可降低载体基板331的挠曲。
因此，可在抑制载体基板331的挠曲的同时，在半导体芯片323上层叠包装不同的半导体芯片333a～333c。结果，在确保载体基板321、331之间的连接可靠性的同时，可层叠不同种类组件PK61、PK62，可实现不同种类的半导体芯片323、333a～333c的3维安装结构。
另外，用密封树脂337来密封半导体芯片333a、333b，密封树脂337例如通过使用环氧树脂等热固化性树脂的模制成形等来形成。
另外，在上述实施方式中，说明了在载体基板的两个面中装载半导体芯片的方法，但也可在载体基板的一个面中装载半导体芯片，在载体基板的另一个面中装载伪芯片。由此，作为伪芯片，除半导体类材料外，可使用金属类材料、陶瓷类材料或树脂类材料等，对可装载在载体基板上的材料没有限制，所以可精密控制载体基板的挠曲状态。
另外，上述半导体装置和电子零件例如可适用于液晶显示装置、便携电话、便携信息终端、视频摄像机、数码相机、MD(Mini Disc)播放器等电子仪器中，可实现电子仪器的小型、轻量化，同时，可提高电子仪器的可靠性。
另外，在上述实施方式中，举例说明了安装半导体芯片或半导体组件的方法，但本发明不一定限于安装半导体芯片或半导体组件的方法，例如也可安装弹性表面波(SAW)元件等陶瓷元件、光调制器或光开关等光学元件、磁传感器或生物传感器等各种传感器类等。

Claims (17)

1、一种半导体装置，其特征在于，具备：
第1载体基板；
面朝下安装在所述第1载体基板上的第1半导体芯片；
面朝下安装在所述第1载体基板背面的第2半导体芯片；
第2载体基板；
装载在所述第2载体基板上的第3半导体芯片；和
突出电极，以连接所述第2载体基板与所述第1载体基板，使所述第2载体基板保持在所述第1半导体芯片上。
2、根据权利要求1所述的半导体装置，其特征在于，将所述第2载体基板固定在第1载体基板上，以跨在所述第1半导体芯片上。
3、根据权利要求1或2所述的半导体装置，其特征在于，具备密封所述第3半导体芯片的密封件。
4、根据权利要求3所述的半导体装置，其特征在于，所述密封件是模制树脂。
5、根据权利要求4所述的半导体装置，其特征在于，所述密封件的侧壁与所述第2载体基板的侧壁位置一致。
6、根据权利要求1～5中的任意1项所述的半导体装置，其特征在于，所述第1半导体芯片和所述第2半导体芯片通过压接接合连接于所述第1载体基板上。
7、根据权利要求1～6中的任意1项所述的半导体装置，其特征在于，包含所述第1载体基板的半导体装置与包含所述第2载体基板的半导体装置在相等温度下的弹性系数不同。
8、根据权利要求1～7中的任意1项所述的半导体装置，其特征在于，装载所述第1半导体芯片和所述第2半导体芯片的第1载体基板是倒装片安装的球状栅格阵列，装载所述第3半导体芯片的第2载体基板是模制密封的球状栅格阵列或芯片尺寸组件。
9、根据权利要求1～8中的任意1项所述的半导体装置，其特征在于，所述第3半导体芯片包含层叠多个芯片的结构。
10、根据权利要求1～9中的任意1项所述的半导体装置，其特征在于，所述第3半导体芯片包含将多个芯片并列配置在第2载体基板上的结构。
11、一种半导体装置，其特征在于，具备：
第1载体基板；
面朝下安装在所述第1载体基板表面和背面至少其中的任一方面上的第1半导体芯片；
第2载体基板；
装载在所述第2载体基板上的第2半导体芯片；
装载在所述第2载体基板背面的第3半导体芯片；和
连接所述第2载体基板与所述第1载体基板的突出电极。
12、一种半导体装置，其特征在于，具备：
载体基板；
面朝下安装在所述载体基板上的第1半导体芯片；
面朝下安装在所述第1载体基板的背面的第2半导体芯片；
在电极衬垫的形成面上形成再配置配线层的第3半导体芯片；和
突出电极，以连接所述第3半导体芯片与所述载体基板，使所述第3半导体芯片保持在所述第1半导体芯片上。
13、一种电子设备，其特征在于，具备：
第1载体基板；
装载在所述第1载体基板上的第1电子零件；
装载在所述第1载体基板的背面的第2电子零件；
第2载体基板；
装载在所述第2载体基板上的第3电子零件；
突出电极，以连接所述第2载体基板与所述第1载体基板，使所述第2载体基板保持在所述第1电子零件上；和
密封所述第3电子零件的密封件。
14、一种电子仪器，其特征在于，具备：
第1载体基板；
装载在所述第1载体基板上的第1半导体芯片；
装载在所述第1载体基板的背面的第2半导体芯片；
第2载体基板；
装载在所述第2载体基板上的第3半导体芯片；
突出电极，以连接所述第2载体基板与所述第1载体基板，使所述第2载体基板保持在所述第1半导体芯片上；
密封所述第3半导体芯片的密封件；和
安装所述第1载体基板的母基板。
15、一种半导体装置的制造方法，其特征在于，具备：
将第1半导体芯片面朝下安装在第1载体基板上的工序；
将第2半导体芯片面朝下安装在所述第1载体基板的背面的工序；
将第3半导体芯片安装在第2载体基板上的工序；
在所述第2载体基板上形成突出电极的工序；
用密封树脂密封安装在所述第2载体基板上的第3半导体芯片的工序；和
经所述突出电极来连接所述第2载体基板与所述第1载体基板，使所述第2载体基板保持在所述第1半导体芯片上的工序。
16、根据权利要求15所述的半导体装置的制造方法，其特征在于，
由所述密封树脂密封所述第3半导体芯片的工序具备：
由密封树脂一体模制成形安装在所述第2载体基板上的多个第3半导体芯片的工序；和
对每个所述第3半导体芯片切断通过所述密封树脂模制成形的所述第2载体基板的工序。
17、一种电子设备的制造方法，其特征在于，具备：
将第1电子零件面朝下安装在第1载体基板上的工序；
将第2电子零件面朝下安装在所述第1载体基板的背面的工序；
将第3电子零件安装在第2载体基板上的工序；
在所述第2载体基板上形成突出电极的工序；
用密封树脂密封安装在所述第2载体基板上的第3电子零件的工序；和
经所述突出电极来连接所述第2载体基板与所述第1载体基板，使所述第2载体基板保持在所述第1电子零件上的工序。
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JP3680839B2 (ja) 2005-08-10
US20040222508A1 (en) 2004-11-11

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