[go: up one dir, main page]

CN1459855A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN1459855A
CN1459855A CN03123706A CN03123706A CN1459855A CN 1459855 A CN1459855 A CN 1459855A CN 03123706 A CN03123706 A CN 03123706A CN 03123706 A CN03123706 A CN 03123706A CN 1459855 A CN1459855 A CN 1459855A
Authority
CN
China
Prior art keywords
mentioned
semiconductor chip
wire
lead
electrode pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN03123706A
Other languages
English (en)
Other versions
CN100481414C (zh
Inventor
松泽朝夫
西田隆文
中岛靖之
守田俊章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Publication of CN1459855A publication Critical patent/CN1459855A/zh
Application granted granted Critical
Publication of CN100481414C publication Critical patent/CN100481414C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48647—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905—Shape
    • H01L2224/49051—Connectors having different shapes
    • H01L2224/49052—Different loop heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85203—Thermocompression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明的半导体器件具有在上述半导体芯片的主面沿其一边配置的多个电极焊盘、及在上述布线基板的主面沿上述半导体芯片的一边配置的多个连接部，上述多条引线中的相邻的第1和第2引线中，上述第2引线的弯曲部分的高度比上述第1引线高，上述第2引线的一端部在距离上述半导体芯片的一边比上述第1引线的一端部远的位置与上述电极焊盘连接，上述第2引线的另一端部在距离上述半导体芯片的一边比上述第1引线的另一端部远的位置与上述电极焊盘连接。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件及其制造技术，特别涉及可适用于面朝上键合(bonding)结构的半导体器件及其制造技术的有效技术。
背景技术
作为半导体器件，已知例如被称为BGA(Ball Grid Array：球网格阵列)型的半导体器件。该BGA型半导体器件的结构如下，在被称为内插板(interposer)的布线基板的主面侧搭载半导体芯片，并在位于与布线基板主面相反的背面侧配置多个球状焊锡凸起作为外部连接用端子。
BGA型半导体器件已经开发各种结构的器件并正在产品化，从大的方面可分为面朝上键合结构(引线键合结构)和面朝下键合结构。在面朝上键合结构中，由键合引线将配置在半导体芯片的主面(电路形成面)上的电极焊盘与配置在内插板主面上的电极焊盘(由布线的一部分形成的连接部)电连接。在面朝下键合结构中，对配置在半导体芯片的主面上的电极焊盘与配置在内插板主面上的电极焊盘进行的电连接，由介于这些电极焊盘之间的焊锡凸起进行。
例如在日本特开2001-144214号公报中公开了有关面朝上键合结构的BGA型半导体器件。另外，例如在日本特开平6-34983号公报中公开了有关面朝下键合结构的BGA型半导体器件。
近年来，随着携带电话、携带型个人电脑等电子设备的小型化的发展，装入这些电子设备的BGA型半导体器件也被要求小型化。于是，本发明讨论有关具有能用已有制造设备且可低成本制造的面朝上键合结构的BGA型半导体器件的结果，发现以下问题点。
为了实现BGA型半导体器件的小型化，需要使半导体芯片和内插板的平面尺寸变小。为了减小半导体芯片的平面尺寸，需要减小布置在半导体芯片主面上的电极焊盘的排列节距(pitch)。另外，为了减小内插板的平面尺寸，需要减小布置在内插板主面上的电极焊盘的排列节距。
在使半导体芯片和内插板的电极焊盘的排列节距变小时，邻近的键合引线的间距也变狭小。在邻近的键合引线的间距变狭小时，按照传递塑封法(transfer molding method)形成树脂密封体时，由于因树脂的流动而引起的键合引线的变形也就是引线漂移，容易引起被称为邻近的键合引线之间短路的异常。因此，为了实现面朝上结构的BGA型半导体器件的小型化，需要抑制邻近的键合引线之间的短路。
抑制邻近的键合引线之间短路的方法可以考虑改变邻近的键合引线弯曲部分(loop)高度的方法，但这种情况虽然可有效抑制键合引线在中间部分的短路，但难以控制键合引线在键合引线的一端部侧(半导体芯片的电极焊盘侧)和另一端侧(内插板的电极焊盘侧)的短路。
发明内容
本发明的目的在于提供一种能够抑制邻近的键合引线之间短路的技术。
另外，本发明的另一目的在于提供一种能够抑制邻近的键合引线之间短路、且能够实现使半导体器件小型化的技术。
通过本说明书的记述和附图，能清楚本发明的上述及其他目的和新的特征。
本申请公开的发明中的代表例的概要的简要说明如下所述。
(1)本发明的半导体器件，具有：半导体芯片；布线基板，其在主面上配置了上述半导体芯片；多个电极焊盘，在上述半导体芯片的主面沿其一边配置；多个连接部，在上述布线基板的主面沿上述半导体芯片的一边配置；多条引线，分别与上述半导体芯片的多个电极焊盘和上述布线基板的多个连接部电连接；及树脂密封体，密封上述半导体芯片和上述多条引线；
上述多条引线包含第1引线和第2引线，上述第1引线的一端部与上述多个电极焊盘中的第1电极焊盘连接、且上述一端部相反侧的另一端部与上述多个连接部中的第1连接部连接，上述第2引线的一端部与上述多个电极焊盘中的邻近第1电极焊盘的第2电极焊盘连接、且上述一端部相反侧的另一端部与上述多个连接部中的邻近第1连接部的第2连接部连接；
上述第2引线的一端部被连接在距离上述半导体芯片的一边比上述第1引线的一端部还远的位置；
上述第2引线的另一端部被连接在距离上述半导体芯片的一边比上述第1引线的另一端部还远的位置。
(2)本发明的半导体器件的制造方法，具有以下工序：组装部件准备工序，准备半导体芯片和布线基板，该半导体芯片具有在主面沿该主面的一边配置的多个电极焊盘，该布线基板具有搭载上述半导体芯片的搭载区域、及在上述芯片搭载区域外侧沿着上述半导体芯片的一边配置的多个连接部；粘片工序，在上述布线基板的芯片搭载区域搭载上述半导体芯片；引线键合工序，通过多条引线分别对上述半导体芯片的多个电极焊盘和上述布线基板的多个连接部进行电连接；及塑封工序，通过树脂密封上述半导体芯片及上述多条引线；
上述多条引线包含第1引线和第2引线，上述第1引线的一端部与上述多个电极焊盘中的第1电极焊盘连接、且上述一端部相反侧的另一端部与上述多个连接部中的第1连接部连接，上述第2引线的一端部分与上述多个电极焊盘中的邻近第1电极焊盘的第2电极焊盘连接、且上述一端部相反侧的另一端部与上述多个连接部中的邻近第1连接部的第2连接部连接；
上述第2引线的一端部被连接在距离上述半导体芯片的一边比上述第1引线的一端部还远的位置；
上述第2引线的另一端部被连接在距离上述半导体芯片的一边比上述第1引线的另一端部还远的位置。
附图说明
图1是示出本发明实施例1的半导体器件内部结构的俯视图。
图2是沿图1A-A线的剖面图。
图3是扩大图1局部的俯视图。
图4表示实施例1的半导体器件内部结构的图((a)是沿图3A-A线的剖面图，(b)是沿图3C-C线的剖面图，(C)是重叠了(a)和(b)的状态的剖面图)。
图5是扩大图3局部的俯视图。
图6是示出制造本实施例1的半导体器件中使用的多面处理板的概要结构的俯视图。
图7是在本实施例1的半导体器件的制造中、进行了粘片工序的状态的俯视图。
图8是在本实施例1的半导体器件的制造中、进行了第1引线键合工序的状态的俯视图。
图9是扩大图8局部的俯视图。
图10是在本实施例1的半导体器件的制造中、进行了第2引线键合工序的状态的俯视图。
图11是扩大图10局部的俯视图。
图12是示出制造本实施例1的半导体器件的塑封工序中、将多面处理板定位在成型模具中的状态的俯视图。
图13是示出制造本实施例1的半导体器件的塑封工序中、流入成型模具的腔的内部的树脂的状态的俯视图。
图14是在本实施例1的半导体器件的制造中、进行了塑封工序的状态的俯视图。
图15是在本实施例1的半导体器件的制造中、进行了切断工序的状态的俯视图。
图16是本实施例1的半导体晶片的俯视图。
图17是扩大图16局部的俯视图。
图18是扩大图17局部的俯视图。
图19是在本实施例1的半导体器件的制造中、用于说明特性检测工序的图。
图20是示出半导体芯片的电极焊盘与键合引线的一端部的连接为之字形状进行时的连接部的位置的图。
图21是示出半导体芯片的电极焊盘与键合引线的一端部的连接为一直线状进行时的连接部的位置的图。
图22是示出本发明实施例2的半导体器件的概要结构的主要部分的俯视图。
图23是示出图22的半导体芯片的概要结构的主要部分的俯视图。
图24是示出本发明实施例3的半导体器件内部结构的俯视图。
图25是与图24对应的主要部分的剖视图。
具体实施方式
下面，参照附图详细说明本发明的实施方式。并且，在用于说明发明实施方式的全部图中，具有相同功能的部分附带相同符号，并省略对其进行的反复说明。
(实施例1)
实施例1说明有关在面朝上键合结构的BGA型半导体器件的例子。
图1是示出本发明实施例1的面朝上键合结构的BGA型半导体器件内部结构的俯视图。图2是沿图1A-A线的剖面图。图3是扩大图1局部的俯视图。图4表示实施例1的半导体器件内部结构的图((a)是沿图3A-A线的剖面图，(b)是沿图3C-C线的剖面图，(C)是重叠了(a)和(b)的状态的剖面图)。图5是扩大图3局部的俯视图。
如图1和图2所示，本实施例1的BGA型半导体器件1是如下的封装结构：在位于内插板4的相互相反侧的主面4x和背面4y(互相相对的主面4x和背面4y)中的主面4x侧搭载半导体芯片2，在内插板4的背面4y侧配置多个球状焊锡凸起10作为外部连接用端子。
半导体芯片2的与厚度方向交叉的平面形状为方形，本实施例中例如为5.0mm×5.00mm的正方形。半导体芯片2虽不限于此，但主要是具有半导体基板、在半导体基板的主面上形成的多个晶体管元件、在上述半导体基板的主面上分别重叠了各绝缘层、布线层的多层布线层、覆盖该多层布线层而形成的表面保护膜(最终保护膜)的结构。绝缘层例如由氧化硅膜形成。布线层例如由铝(Al)、或铝合金、或铜(Cu)、或铜合金等金属膜形成。表面保护膜例如由重叠了氧化硅膜或氮化硅膜等无机绝缘膜及有机绝缘膜的多层膜形成。
半导体芯片2具有相互位于相反侧的主面(电路形成面)2x及背面2y，在半导体芯片2的主面2x侧作为集成电路例如形成控制电路。该控制电路主要通过在半导体基板的主面形成的晶体管元件和在多层布线层形成的布线构成。在该背面2y和内插板4的主面4x之间存在粘接材料7的状态下，半导体芯片2粘接固定在内插板4的主面4x上。
在半导体芯片2的主面上配置着由多个电极焊盘3构成的4列焊盘组。沿着半导体芯片2的第1边2x1配置着第1焊盘组的多个电极焊盘3，沿着半导体芯片2的第2边2x2配置着第2焊盘组的多个电极焊盘3，沿着半导体芯片2的第3边2x3配置着第3焊盘组的多个电极焊盘3，沿着半导体芯片2的第4边2x4配置着第3焊盘组的多个电极焊盘3。各焊盘组的多个电极焊盘3在半导体芯片2的多层布线层中的最上层的布线层上形成，且通过在半导体芯片2的表面保护膜上与各电极焊盘3相对应而形成了的键合开口露出。
内插板4的与厚度方向交叉的平面形状为方形，本实施例例如为13.0mm×13.00mm的正方形。内插板4虽然不限于此，但主要为具有芯材、覆盖该芯材的主面而形成的保护膜、覆盖位于与该芯材的主面相反侧的背面(与芯材的主面相对的面)而形成的保护膜的结构。芯材例如为在该主面、背面和内部具有布线的多层布线结构。芯材的各绝缘层例如由在玻璃纤维中浸入环氧树脂系或聚酰胺系树脂的高弹性树脂基板形成。芯材的各布线层例如由主要成分为Cu的金属膜形成。形成芯材主面上的保护膜的目的主要是保护在芯材的最上层的布线层上形成的布线，形成芯材背面上的保护膜的目的主要是保护在芯材的最下层的布线层上形成的布线。芯材主面上和背面上的保护膜例如使用由二液性碱性显像液型阻焊剂油墨或热可硬化性阻焊剂油墨构成的绝缘膜。
在内插板4的主面4x上，在半导体芯片2的周围配置着由多个电极焊盘(引线连接部)5构成的4列焊盘组。第1焊盘组的多个电极焊盘5沿半导体2的第1边2xl配置，第2焊盘组的多个电极焊盘5沿半导体2的第2边2x2配置，第3焊盘组的多个电极焊盘5沿半导体2的第3边2x3配置，第4焊盘组的多个电极焊盘5沿半导体2的第4边2x4配置。各焊盘组的多个电极焊盘5分别由芯材的最上层的布线层上形成的多个布线的一部分构成，且通过在芯材主面上的保护膜上与各电极焊盘5相对应而形成了的开口露出。
在内插板4的背面4y上配置着多个电极焊盘6。该多个电极焊盘6分别由芯材的最下层的布线层上形成的多个布线的一部分构成，且通过在芯材主面上的保护膜上与各电极焊盘6相对应而形成了的开口露出。
构成半导体芯片2的第1焊盘组的多个电极焊盘3和构成内插板4的第1焊盘组的多个电极焊盘5，分别通过构成第1引线组的多根键合引线8进行电连接。构成半导体芯片2的第2焊盘组的多个电极焊盘3和构成内插板4的第2焊盘组的多个电极焊盘5，分别通过构成第2引线组的多根键合引线8进行电连接。构成半导体芯片2的第3焊盘组的多个电极焊盘3和构成内插板4的第3焊盘组的多个电极焊盘5，分别通过构成第3引线组的多根键合引线8进行电连接。构成半导体芯片2的第4焊盘组的多个电极焊盘3和构成内插板4的第4焊盘组的多个电极焊盘5，分别通过构成第4引线组的多根键合引线8进行电连接。键合引线8例如使用金(Au)引线。键合引线8的连接方法例如使用热压接与超声波振动并用的钉头式键合(nail-head bonding)(球焊)法。
各引线组的多个键合引线8例如通过钉头式键合法进行连接，该钉头式键合法以半导体芯片2的电极焊盘3为第1键合点、以内插板4的电极焊盘5为第2键合点。
半导体芯片2、各引线组的多根键合引线8等被在内插板4的主面4x上形成的树脂密封体9密封着。为了实现使应力降低的目的，树脂密封体9例如由添加了酚醛系硬化剂、硅胶和大量填充物(例如二氧化硅)等的环氧树脂系的热可硬化性绝缘树脂形成。形成树脂密封体9的方法例如使用适合大量生产的传递塑封法。
多个焊锡凸起10分别与在内插板4的背面4y形成的多个电极焊盘6固定粘接，进行电和机械的连接。焊锡凸起10使用实质上不含Pb的无Pb组成的焊锡凸起，例如使用Sn-1[wt％]Ag-0.5[wt％]Cu组成的焊锡凸起。
构成半导体芯片2的第1焊盘组的多个电极焊盘3的平面形状为长方形，该长方形的位于互相相反侧的2条长边沿着距离上述半导体芯片2的第1边2x1变远的方向延伸、且位于互相相反侧的2条短边沿着半导体芯片2的第1边2x1延伸。另外，构成半导体芯片2的第2焊盘组的多个电极焊盘3、构成第3焊盘组的多个电极焊盘3和构成第4焊盘组的多个电极焊盘3也与构成第1焊盘组的多个电极焊盘3一样，平面形状是长方形，该长方向的位于互相相反侧的2条长边沿着距离上述半导体芯片2的边(第2边2x2、第3边2x3、第4边2x4)变远的方向延伸、且位于互相相反侧的2条短边沿着半导体芯片2的边(第2边2x2、第3边2x3、第4边2x4)延伸。
构成第1引线组的多根键合引线8包含第1键合引线8a和第2键合引线8b；所述第1键合引线8a如图3和图4(a)所示，一端部8a1与构成上述半导体芯片2的第1焊盘组的多个电极焊盘3中的第1电极焊盘3a连接，且一端部8a1相反侧的另一端部8a2与构成内插板4的第1焊盘组的多个电极焊盘5中的第1电极焊盘5a连接；所述第2键合引线8b如图3和图4(b)所示，一端部8b1与构成上述半导体芯片2的第1焊盘组的多个电极焊盘3中的第1电极焊盘3a连接，一端部8b1相反侧的另一端部8b2与构成内插板4的第1焊盘组的多个电极焊盘5中的第1电极焊盘5a邻近的第2电极焊盘5b连接，且弯曲高度14b比第1键合引线8a的弯曲高度14a(参照图4(a))高。
如图4(a)和图4(b)所示，第2键合引线8b的一端部8b1被连接在距离半导体芯片2的第1边2x1比第1键合引线8a的一端部8a1远的位置。
第2键合引线8b的另一端部8b2被连接在距离半导体芯片2的第1边2x1比第1键合引线8a的另一端部8a2远的位置。
利用如上所述的结构，如图4(c)所示，键合引线8的排列方向上的第1键合引线8a和第2键合引线8b不重合，所以按照传递塑封法形成树脂密封体时，由于因树脂流动而引起的键合引线形状的变形的引线漂移即使在键合引线8上发生，也可以抑制邻近的键合引线间的短路。
仅仅改变弯曲高度的高度也具有抑制邻近的键合引线间短路的效果，但这时键合引线的排列方向上键合引线的重合，在一端侧和另一端侧发生，所以虽然可以抑制键合引线中间部位的短路，但是抑制在一端侧和另一端侧的短路是困难的。与此相对，在本实施例中引线的排列方向上键合引线的重合，在一端侧和另一端侧不发生，所以可以抑制在一端侧和另一端侧的短路。
为了实现BGA型半导体器件1的小型化，需要减小半导体芯片和内插板的平面尺寸。为了减小半导体芯片和内插板的平面尺寸，需要减小在半导体芯片和内插板上布置的电极焊盘的排列节距。半导体芯片的电极焊盘的排列节距变窄时，必须使用引线直径细的键合引线。由于引线直径细的键合引线机械强度低，所以键合引线的一端侧和另一端侧也容易发生引线漂移。另外，半导体芯片和内插板上布置的电极焊盘的排列节距变窄时，邻近的键合引线的间隔也变窄，所以键合引线的一端侧和另一端侧也容易发生引线漂移。因此，为了实现BGA型半导体器件1的小型化，需要抑制键合引线的一端侧和另一端侧的短路。在本实施例中，由于也可以抑制键合引线的一端侧和另一端侧的短路，所以可以实现BGA型半导体器件1的小型化。
构成半导体芯片2的第1焊盘组的多个电极焊盘3如图3所示，是将第1电极焊盘3a和第2电极焊盘3b交替并列反复配置成直线排列，构成内插板的第1焊盘组的多个电极焊盘5如图3所示，是将第1电极焊盘5a和第2电极焊盘5b交替并列反复配置成之字形排列。
如图4(a)和图4(b)所示，半导体芯片2的第1边2x1和第2电极焊盘5b之间的距离11b比半导体芯片2的第1边2x1和第1电极焊盘5a之间的距离11a宽，半导体芯片2的第1边2x1和第2键合引线8b的一端部8b1之间的距离12b比半导体芯片2的第1边2x1和第1键合引线8a的一端部8a1之间的距离12a宽，第2键合引线8b的一端部8b1和另一端部8b2之间的距离13b比第1键合引线8a的一端部8a1和另一端部8a2之间的距离13a宽。
如图5所示，构成半导体芯片2的第1焊盘组的电极焊盘3的宽度3w比构成内插板4的第1焊盘组的电极焊盘5的宽度5w狭窄，构成半导体芯片2的第1焊盘组的电极焊盘3的排列节距3p比构成内插板4的第1焊盘组的电极焊盘5的排列节距5p狭窄。在本实施例中，电极焊盘3的宽度3w例如大致为60μm，电极焊盘3的排列节距3p例如大致为65μm，电极焊盘5的宽度5w例如大致为100μm，电极焊盘5的排列节距5p例如大致为200μm。另外，构成半导体芯片2的第1焊盘组的多个电极焊盘3在键合引线8连接的各键合面具有探针的接触痕迹部26，该接触痕迹部26设在距离半导体芯片2的第1边2x1比第1键合引线8a的一端部8a1还远、且距离半导体芯片2的第1边2x1比第2键合引线8b的一端部8b1还近的位置。
并且，第2至第4引线组的结构也与第1引线组相同，半导体芯片2的第2至第4焊盘组的结构也与半导体芯片2的第1焊盘组相同，内插板4的第2至第4焊盘组的结构也与内插板4的第1焊盘组相同。
树脂密封体9和内插板4的平面尺寸大致相同，树脂密封体9和内插板4的的侧面为同一面。在制造本实施例的BGA型半导体器件1中，采用一同塑封的方式。因此，如后详细说明的那样，使用主面具有多个器件区域(制品形成区域)的多面处理板(多个处理基板)，利用1个树脂密封体(一同用树脂密封体)密封在该多面处理板得各器件区域配置的半导体芯片之后，将多面处理板的多个器件区域与该树脂密封体一起分成一个一个的，由此制造BGA型半导体器件1。
图6是示出制造BGA型半导体器件1所使用的多面处理板的概要结构的俯视图。
如图6所示，多面处理板15的与其厚度方向交叉的平面形状为方形，本实施例中例如为长方形。在多面处理板15的主面(芯片搭载面)设有塑封区域(图未示出)，在该塑封区域中设有多个器件区域16，在各器件区域16中设有芯片搭载区域17。在各芯片搭载区域17搭载半导体芯片2，在塑封区域形成树脂密封体，该树脂密封体一同对各芯片搭载区域17搭载的多个半导体芯片2进行密封。
各器件区域16由规定它们边界的划分区域18划分。另外，各器件区域16的结构和平面形状与图1和图2所示的内插板4一样。
以下，使用图7至图15说明有关BGA型半导体器件1的制造。
图7是进行了粘片工序的状态的俯视图。图8是进行了第1引线键合工序的状态的俯视图。图9是扩大图8局部的俯视图。图10是进行了第2引线键合工序的状态的俯视图。图11是扩大图10局部的俯视图。图12是塑封工序中将多面处理板定位在成型模具中的状态的俯视图。图13是塑封工序中流入成型模具的腔的内部的树脂的状态的俯视图。图14是进行了塑封工序的状态的俯视图。图15是进行了切断工序的状态的俯视图。
首先，准备半导体芯片2和多面处理板15。
接着，在多面处理板15的主面的各芯片搭载区域17涂覆例如由环氧树脂系热可硬化性树脂形成的粘接材料7，然后，在各芯片搭载区域17上隔着粘接材料7搭载半导体芯片，然后，进行热处理使粘接材料7硬化，如图7所示，在各芯片搭载区域17上粘接固定半导体芯片2。
接着，如图8和图9所示，利用多个第1键合引线8a，分别电连接半导体芯片2的多个第1电极焊盘3a和器件形成区域16(内插板4)的多个第1电极焊盘5a。第1键合引线8a的连接通过钉头式键合法进行，该钉头式键合法以半导体芯片2的第1电极焊盘3a为第1键合点，以内插板4的第1电极焊盘5a为第2键合点。
接着，如图10和图11所示，利用多个第2键合引线8b，分别电连接半导体芯片2的多个第2电极焊盘3b和器件形成区域16(内插板4)的多个第2电极焊盘5b。第2键合引线8b的连接通过钉头式键合法进行，该钉头式键合法以半导体芯片2的第2电极焊盘3b为第1键合点，以内插板4的第2电极焊盘5b为第2键合点。半导体芯片2的第2电极焊盘3b和第2键合引线8b的一端部8b1的连接，在距离半导体芯片2的边比半导体芯片2的第1电极焊盘3a和第1键合引线8a的一端部8a1的连接还远的位置进行，且器件形成区域(内插板4)16的第2电极焊盘5b和第2键合引线8b的另一端部8b2的连接，在距离半导体芯片2的边比器件形成区域16的第1电极焊盘5a和第1键合引线8a的另一端部8a2的连接还远的位置进行。第2键合引线8b的弯曲部分的高度比第1键合引线8a高。
在该工序中，第2键合引线8b的一端部8b1被连接在距离半导体芯片2的第1边2x1比第1键合引线8a的一端部8a1还远的位置，第2键合引线8b的另一端部8b2被连接在距离半导体芯片2的第1边2x1比第1键合引线8a的另一端部8a2还远的位置。因此，键合引线8的排列方向上的第1键合引线8a和第2键合引线8b不重合。
另外，弯曲部分的高度比第1键合引线8a还高的第2键合引线8b的连接，在连接了第1键合引线8a之后进行。如上所述，在连接了第1键合引线8a之后，连接弯曲部分的高度比第1键合引线8a还高的第2键合引线8b，由此，与交替连接第1和第2键合引线(8a、8b)的情况相比，引线键合的设置是容易的，所以生产性提高。
并且，第2键合引线8b的长度也比第1键合引线8a长。
接着，如图12所示，在成形模具30的上模30a和下模30b之间对多面处理板15进行定位。
虽不限于此，但成形模具30具有腔31、多个树脂注入口32、多个子浇道、多个主浇道、多个剔料(cull)、连结浇道、多个气孔、多个端口和板收纳区域。腔31、多个树脂注入口32、多个子浇道、多个主浇道、多个剔料、连结浇道和多个气孔设在上模30a上，多个端口和板收纳区域设在下模30b上。腔31从上模30a的对准面向深度方向凹陷，板收纳区域从下模30b的对准面向深度方向凹陷。
腔31和板收纳区域的平面形状形成为与多面处理板15的平面形状相对应的形状。在本实施例中，由于多面处理板15的平面形状为长方形，与此相对应腔31和板收纳区域的平面形状也为长方形。腔31的平面尺寸与塑封区域的平面尺寸大致相同，板收纳区域的平面尺寸与多面处理板15的平面尺寸大致相同。多面处理板15被收纳在下模30b的板收纳区域，且进行与成形模具30的定位。将多面处理板15定位在成形模具30上时，腔31布置在多面处理板15的主面上。
接着，例如将环氧树脂系热可硬化性树脂从成形模具30的端口，通过剔料、主浇道、子浇道和树脂注入口32注入腔31的内部，从而一同对贴装着多面处理板15的主面上的多个半导体芯片2进行树脂密封。通过该工序，如图14所示，仅在多面处理板15的主面侧形成树脂密封体33，一同密封多个半导体芯片2。
在该工序中，由于沿腔31的一长边设置多个树脂注入口32，以便覆盖腔31的内部的整个区域均匀地填充树脂，所以如图13所示，注入腔31内部的树脂33a从腔31的一长边侧朝相反的另一长边侧流动。因此，腔31内部的树脂33a的宏观流动方向34为从腔31的一长边侧朝另一长边侧的方向。
在该工序中，键合引线8的排列沿树脂33a的宏观流动方向34的引线组(换而言之，在与树脂33a的宏观流动方向34垂直的方向拉伸的引线组)中，键合引线8的引线漂移容易发生，但由于在邻近的键合引线中，第2键合引线8b的一端部8b1被连接在距离半导体芯片的第1边2x1比第1键合引线8a的一端部8a1还远的位置，且第2键合引线8b的另一端部8b2被连接在距离半导体芯片的第1边2x1比第1键合引线8a的另一端部8a2还远的位置，所以可以抑制邻近的键合引线间的短路。
接着，在多面处理板15的背面上配置了多个电极焊盘6的各表面上形成球状焊锡凸起10。焊锡凸起10例如通过用球供给法供给球状焊锡材料之后进行热处理而形成。
接着，将多个半导体芯片2一同密封的树脂密封体33粘接在切割薄片26上，然后，如图15所示，将多面处理板15的多个芯片区域16与树脂密封体33一起分割成单体，这些分割利用切割设备进行。通过该工序，可大致完成如图1和图2所示的半导体器件1。
下面，使用图16至图19说明有关半导体芯片2的制造。
图16是本实施例1的半导体晶片的俯视图。图17是扩大图16局部的俯视图。图18是扩大图17局部的俯视图。图19是用于说明特性检测工序的图。
首先，准备由单晶硅形成的半导体晶片20，然后，在半导体晶片20的主面，进行形成场效应晶体管等半导体元件、布线层、绝缘膜等的晶片前处理工序，如图16所示，在半导体芯片20的主面上，成行列状地形成集成电路例如具有控制电路的多个芯片形成区域21。多个芯片形成区域21分别由规定它们边界的划分区域22划分，被配置成相互隔离的状态。通过在半导体晶片20的主面上主要形成半导体元件、多层布线层、电极焊盘3、表面保护膜和开口等，而形成多个芯片形成区域22。
然后，使用探针卡进行探针检测。探针检测首先进行半导体晶片20与探针卡的位置对准，然后如图19所示，使探针卡的探针25的前端部25a与半导体晶片20的芯片形成区域21的多个电极焊盘3接触。然后，通过与探针卡的探针25进行电连接的检测设备检测芯片形成区域21的电路电特性。对每个芯片形成区域21都进行该工序。由此来对芯片形成区域21判别良品、不良品、工作频率等电特性的等级。
在该工序中，如图17和图18所示，在电极焊盘3的连接面上形成因探针25的接触而造成的伤，即接触痕迹部26。由于该接触痕迹部26使电极焊盘3与键合引线8的一端部的接合性劣化，所以需要尽量使与键合引线8的一端部连接的区域不形成接触痕迹部26。
在本实施例中，电极焊盘3的平面形状为长方形，该长方形的位于互相相反侧的2条长边沿着距离上述半导体芯片2的一边变远的方向延伸，且位于互相相反侧的2条短边沿着上述半导体芯片2的边延伸。因此，通过使电极焊盘3的长边方向的长度不小于沿电极焊盘3与键合引线8的一端部的连接区域的电极焊盘3的长边方向的长度的2倍，可以在距离半导体芯片2的边比第1键合引线8a的一端部还远、且距离半导体芯片2的边比第2键合引线8b的一端部还近的位置设置接触痕迹部26，所以可以不在与键合引线8的一端部连接的区域形成接触痕迹部26。另外，由于可以使探针25的前端部25a不是之字排列，且不在与键合引线8的一端部连接的区域形成接触痕迹部26，所以可以使用现有的探针卡进行探针检测。
然后，使用切割装置对半导体芯片20的划分区域22进行切割，按照各芯片形成区域分割半导体晶片20。由此形成半导体芯片2。
图20是示出半导体芯片2的电极焊盘3与键合引线8的一端部的连接为之字形状进行时的连接部的位置的图。
图21是示出半导体芯片2的电极焊盘3与键合引线8的一端部的连接为一直线状进行时的连接部的位置的图。
如图20所示，与第1电极焊盘3a连接的第1键合引线8a的一端部8a1和与第1电极焊盘3a邻近的电极焊盘3b连接的第2键合引线8b的一端部8b1之间的距离8p，当半导体芯片2的电极焊盘3与键合引线8的一端部的连接为之字状时，比半导体芯片2的电极焊盘3与键合引线8的一端部的连接为一直线状时还宽。电极焊盘的排列节距相同时，图21中的劈刀(capillary)的前端部分28与相邻的键合引线8的一端部接触，图22中的劈刀的前端部分28与相邻的键合引线的一端部不接触。
因此，电极焊盘3的间隔不扩大，可以控制引线键合时因劈刀干涉而引起的引线变形。
另外，由于电极焊盘3的排列节距不扩大，距离8p可扩大，所以可以使相当于它的部分、即电极焊盘3的排列节距3p狭窄。其结果，半导体芯片2的平面尺寸可以变小，所以可以实现BGA型半导体器件1的小型化。
(实施例2)
图22是示出本发明实施例2的BGA型半导体器件的概要结构的主要部分的俯视图。图23是示出图22的半导体芯片的概要结构的主要部分的俯视图。
如图22和图23所示，本事实例2的BGA半导体器件la与上述实施例1的结构基本相同，以下的结构不同。
即，在半导体芯片2的主面沿它的边配置多个电极焊盘3，电极焊盘3被排列成第1电极焊盘3a与第2电极焊盘3b交替往返配置成之字状，该第2电极焊盘3b与该第1电极焊盘3a邻近、且距离半导体芯片2的边比第1电极焊盘3a还远。
使用如上所述的半导体芯片2时，也可以得到与上述实施例1相同的效果。
并且，由于本实施例的情况需要将探针25的前端部25a配置成之字状，所以使用现有的探针卡是困难的。
(实施例3)
图24是示出本发明实施例3的BGA型半导体器件内部结构的俯视图。图25是与图24对应的主要部分的剖视图。
如图24和图25所示，本实施例3的BGA半导体器件1b与上述实施例1的结构虽然基本相同，但被树脂密封体9密封的半导体芯片为多层结构这点不同。
在第1半导体芯片2a上通过介于中间的粘接层7叠层第2半导体芯片2b，第1半导体芯片2a的电极焊盘3a与第2半导体芯片2b的电极焊盘3b与实施例1和2同样为之字排列。
由于极力减小树脂密封体9的厚度，上述第2半导体芯片2b例如可以薄型化至0.1mm左右或以下。如上所述使半导体芯片变薄时，由于上侧和下侧的半导体芯片的电极焊盘接近，所以如果与实施例1和2一样配置电极焊盘，则能够防止引线接触。
因此，可以提供薄型且电可靠性高的半导体封装。
以上，根据上述实施例具体说明了本发明人进行的发明，但本发明不限于上述实施例，当然可以在不超出其宗旨的范围内进行各种改变。
发明的效果
如下简单说明采用本申请公开的发明中的代表例可得到的效果，。
如果采用本发明，则可以抑制邻近的键合引线间的短路。
如果采用本发明，则可以实现半导体器件的小型化。

Claims (29)

1.一种半导体器件，具有：
半导体芯片；
布线基板，在主面上配置了上述半导体芯片；
多个电极焊盘，在上述半导体芯片的主面沿其一边配置；
多个连接部，在上述布线基板的主面沿上述半导体芯片的一边配置；
多条引线，分别与上述半导体芯片的多个电极焊盘和上述布线基板的多个连接部电连接；及
树脂密封体，密封上述半导体芯片和上述多条引线；
其特征在于：
上述多条引线包含第1引线和第2引线，上述第1引线的一端部与上述多个电极焊盘中的第1电极焊盘连接、且上述一端部相反侧的另一端部与上述多个连接部中的第1连接部连接，上述第2引线的一端部与上述多个电极焊盘中的邻近第1电极焊盘的第2电极焊盘连接、且上述一端部相反侧的另一端部与上述多个连接部中的邻近第1连接部的第2连接部连接；
上述第2引线的一端部被连接在距离上述半导体芯片的一边比上述第1引线的一端部还远的位置；
上述第2引线的另一端部被连接在距离上述半导体芯片的一边比上述第1引线的另一端部还远的位置。
2.如权利要求1所述的半导体器件，其特征在于：上述多个电极焊盘的平面形状为长方形，该长方形的位于互相相反侧的2条长边沿着距离上述半导体芯片的一边变远的方向延伸。
3.如权利要求1所述的半导体器件，其特征在于：上述多个电极焊盘为上述第1电极焊盘和第2电极焊盘交替并列反复配置的直线排列。
4.如权利要求1所述的半导体器件，其特征在于：
上述多个电极焊盘的平面形状为正方形，
上述第2电极焊盘配置在距离上述半导体芯片的一边比上述第1电极焊盘远的位置。
5.如权利要求4所述的半导体器件，其特征在于：上述多个电极焊盘为上述第1电极焊盘和上述第2电极焊盘交替并列反复配置的之字形排列。
6.如权利要求1所述的半导体器件，其特征在于：上述第2连接部配置在距离上述半导体芯片的一边比上述第1连接部远的位置。
7.如权利要求6所述的半导体器件，其特征在于：上述多个连接部为上述第1连接部和上述第2连接部交替并列反复配置的之字形排列。
8.如权利要求1所述的半导体器件，其特征在于：上述多个电极焊盘的排列节距比上述多个连接部的排列节距窄。
9.如权利要求1所述的半导体器件，其特征在于：上述第1引线比上述第2引线短。
10.如权利要求1所述的半导体器件，其特征在于：通过以上述电极焊盘为第1键合点、上述连接部为第2键合点的钉头式键合法，连接上述多条引线。
11.如权利要求1所述的半导体器件，其特征在于：上述树脂密封体通过传递塑封法形成。
12.如权利要求1所述的半导体器件，其特征在于：
上述多个电极焊盘的平面形状为长方形，该长方形的位于互相相反侧的2条长边沿着距离上述半导体芯片的一边变远的方向延伸；
上述多个电极焊盘在上述引线连接的键合面上有探针的接触痕迹部；
上述接触痕迹部设置在距离半导体芯片的一边比上述第1引线的一端部远、且距离半导体芯片的一边比上述第2引线的一端部近的位置。
13.如权利要求12所述的半导体器件，其特征在于：上述多个电极焊盘的各长边的长度，不小于沿上述电极焊盘和上述引线的一端部的连接区域的上述电极焊盘的长边方向的长度的2倍。
14.一种半导体器件，具有：
半导体芯片；
布线基板，在主面上配置了上述半导体芯片；
第1和第2电极焊盘，在上述半导体芯片的主面沿其一边配置且相邻；
第1和第2连接部，在上述布线基板的主面沿上述半导体芯片的一边配置且相邻；
第1引线，一端部与上述半导体芯片的第1电极焊盘连接、另一端部与上述布线基板的第1连接部连接；
第2引线，一端部与上述半导体芯片的第2电极焊盘连接、另一端部与上述布线基板的第2连接部连接；
树脂密封体，密封上述半导体芯片、上述第1引线和第2引线；
其特征在于：
上述半导体芯片的第2电极焊盘和上述第2引线一端部的连接位置，比上述半导体芯片的第1电极焊盘和上述第1引线一端部的连接位置距离上述半导体芯片的一边还远；
上述布线基板的第1连接部和上述第1引线一端部的连接位置，比上述布线基板的第2连接部和上述第2引线一端部的连接位置距离上述半导体芯片的一边还远。
15.如权利要求14所述的半导体器件，其特征在于：
上述第1和第2电极焊盘的平面形状为长方形，该长方形的位于互相相反侧的2条长边沿着距离上述半导体芯片的一边变远的方向延伸。
16.如权利要求14所述的半导体器件，其特征在于：
上述第1和第2电极焊盘的平面形状为正方形；
上述第2电极焊盘配置在距离上述半导体芯片的一边比上述第1电极焊盘还远的位置。
17.如权利要求15所述的半导体器件，其特征在于：
上述第2连接部配置在距离上述半导体芯片的一边比上述第1连接部还远的位置。
18.一种半导体器件的制造方法，具有以下工序：
组装部件准备工序，准备半导体芯片和布线基板，该半导体芯片具有在主面沿该主面的一边配置的多个电极焊盘，该布线基板具有搭载上述半导体芯片的搭载区域、及在上述芯片搭载区域外侧沿着上述半导体芯片的一边配置的多个连接部；
粘片工序，在上述布线基板的芯片搭载区域搭载上述半导体芯片；
引线键合工序，通过多条引线分别对上述半导体芯片的多个电极焊盘和上述布线基板的多个连接部进行电连接；及
塑封工序，通过树脂密封上述半导体芯片及上述多条引线；
其特征在于：
上述多条引线包含第1引线和第2引线，上述第1引线的一端部与上述多个电极焊盘中的第1电极焊盘连接、且上述一端部相反侧的另一端部与上述多个连接部中的第1连接部连接，上述第2引线的一端部分与上述多个电极焊盘中的邻近第1电极焊盘的第2电极焊盘连接、且上述一端部相反侧的另一端部与上述多个连接部中的邻近第1连接部的第2连接部连接；
上述第2引线的一端部被连接在距离上述半导体芯片的一边比上述第1引线的一端部还远的位置；
上述第2引线的另一端部被连接在距离上述半导体芯片的一边比上述第1引线的另一端部还远的位置。
19.如权利要求18所述的半导体器件的制造方法，其特征在于：上述引线键合工序，上述第1引线的连接比上述第2引线的连接先进行。
20.如权利要求18所述的半导体器件的制造方法，其特征在于：
上述多个电极焊盘的平面形状为长方形，该长方形的位于互相相反侧的2条长边沿着距离上述半导体芯片的一边变远的方向延伸。
21.如权利要求20所述的半导体器件的制造方法，其特征在于：上述多个电极焊盘为上述第1电极焊盘和第2电极焊盘交替并列反复配置的直线排列。
22.如权利要求18所述的半导体器件的制造方法，其特征在于：
上述多个电极焊盘的平面形状为正方形，
上述第2电极焊盘配置在距离上述半导体芯片的一边比上述第1电极焊盘还远的位置。
23.如权利要求22所述的半导体器件的制造方法，其特征在于：上述多个电极焊盘为上述第1电极焊盘和上述第2电极焊盘交替并列反复配置的之字形排列。
24.如权利要求18所述的半导体器件的制造方法，其特征在于：上述第2连接部配置在距离上述半导体芯片的一边比上述第1连接部还远的位置。
25.如权利要求24所述的半导体器件的制造方法，其特征在于：上述多个连接部为上述第1连接部和上述第2连接部交替并列反复配置的之字形排列。
26.如权利要求18所述的半导体器件的制造方法，其特征在于：上述多个电极焊盘的排列节距比上述多个连接部的排列节距还窄。
27.如权利要求18所述的半导体器件的制造方法，其特征在于：上述第1引线比上述第2引线短。
28.如权利要求18所述的半导体器件的制造方法，其特征在于：上述引线键合工序，使用以上述电极焊盘为第1键合点、上述连接部为第2键合点的钉头式键合法进行。
29.如权利要求18所述的半导体器件的制造方法，其特征在于：上述塑封工序使用传递塑封法进行。
CNB031237061A 2002-05-21 2003-05-20 半导体器件及其制造方法 Expired - Fee Related CN100481414C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002146321 2002-05-21
JP2002146321A JP2003338519A (ja) 2002-05-21 2002-05-21 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
CN1459855A true CN1459855A (zh) 2003-12-03
CN100481414C CN100481414C (zh) 2009-04-22

Family

ID=29545121

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB031237061A Expired - Fee Related CN100481414C (zh) 2002-05-21 2003-05-20 半导体器件及其制造方法

Country Status (5)

Country Link
US (2) US6900551B2 (zh)
JP (1) JP2003338519A (zh)
KR (1) KR20040014167A (zh)
CN (1) CN100481414C (zh)
TW (1) TWI297184B (zh)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100345291C (zh) * 2003-12-12 2007-10-24 精工爱普生株式会社 半导体装置和电子器件及其制造方法
CN100419982C (zh) * 2004-05-31 2008-09-17 松下电器产业株式会社 半导体装置
US7476969B2 (en) 2005-07-29 2009-01-13 Omron Corporation Semiconductor packages for surface mounting and method of producing same
CN101071810B (zh) * 2006-05-12 2010-12-22 瑞萨电子株式会社 半导体器件
CN102280425A (zh) * 2010-06-11 2011-12-14 卡西欧计算机株式会社 具备键合引线的半导体器件及其制造方法
CN102456812A (zh) * 2010-10-28 2012-05-16 展晶科技(深圳)有限公司 发光二极管封装结构
CN108140577A (zh) * 2016-02-23 2018-06-08 瑞萨电子株式会社 半导体器件及其制造方法
CN108630630A (zh) * 2017-03-21 2018-10-09 瑞萨电子株式会社 半导体装置的制造方法和半导体装置
CN109075148A (zh) * 2016-09-26 2018-12-21 株式会社Powdec 半导体封装体、模块及电气设备

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005166794A (ja) * 2003-12-01 2005-06-23 Ricoh Co Ltd 部品パッケージとプリント配線基板および電子機器
KR100603932B1 (ko) 2005-01-31 2006-07-24 삼성전자주식회사 칩-온-보오드 기판을 갖는 반도체 장치
WO2006090196A1 (en) * 2005-02-23 2006-08-31 Infineon Technologies Ag Rectangular bond pad and method of wire bonding the same with an elongated ball bond
JP2007103423A (ja) * 2005-09-30 2007-04-19 Renesas Technology Corp 半導体装置及びその製造方法
JP5148825B2 (ja) * 2005-10-14 2013-02-20 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
DE102006015222B4 (de) * 2006-03-30 2018-01-04 Robert Bosch Gmbh QFN-Gehäuse mit optimierter Anschlussflächengeometrie
US7777353B2 (en) * 2006-08-15 2010-08-17 Yamaha Corporation Semiconductor device and wire bonding method therefor
WO2008081630A1 (ja) * 2006-12-29 2008-07-10 Sanyo Electric Co., Ltd. 半導体装置およびその製造方法
TWI357647B (en) * 2007-02-01 2012-02-01 Siliconware Precision Industries Co Ltd Semiconductor substrate structure
TWI333689B (en) * 2007-02-13 2010-11-21 Advanced Semiconductor Eng Semiconductor package
US8922028B2 (en) * 2007-02-13 2014-12-30 Advanced Semiconductor Engineering, Inc. Semiconductor package
US8227917B2 (en) * 2007-10-08 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad design for fine pitch wire bonding
US20090108436A1 (en) * 2007-10-31 2009-04-30 Toshio Fujii Semiconductor package
JP5001903B2 (ja) * 2008-05-28 2012-08-15 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
JP5518381B2 (ja) * 2008-07-10 2014-06-11 株式会社半導体エネルギー研究所 カラーセンサ及び当該カラーセンサを具備する電子機器
WO2010070824A1 (ja) * 2008-12-19 2010-06-24 株式会社アドバンテスト 半導体装置、半導体装置の製造方法およびスイッチ回路
JP5595694B2 (ja) * 2009-01-15 2014-09-24 パナソニック株式会社 半導体装置
JP2011003764A (ja) * 2009-06-19 2011-01-06 Renesas Electronics Corp 半導体装置及びその製造方法
JP5467959B2 (ja) 2010-07-21 2014-04-09 ルネサスエレクトロニクス株式会社 半導体装置
JP2012195459A (ja) * 2011-03-16 2012-10-11 Sharp Corp ワイヤーボンディング方法、及び、半導体装置
JP5294351B2 (ja) * 2011-04-01 2013-09-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5968713B2 (ja) * 2012-07-30 2016-08-10 ルネサスエレクトロニクス株式会社 半導体装置
CN104765169B (zh) * 2015-02-04 2018-01-05 深圳市华星光电技术有限公司 一种阵列基板的检测线路及阵列基板
US20160307873A1 (en) * 2015-04-16 2016-10-20 Mediatek Inc. Bonding pad arrangment design for semiconductor package
JP2018107296A (ja) * 2016-12-27 2018-07-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN108574158B (zh) * 2017-03-14 2020-10-09 群创光电股份有限公司 显示装置及其制造方法
JP2022118876A (ja) 2021-02-03 2022-08-16 キオクシア株式会社 半導体装置
US12033903B1 (en) * 2021-12-09 2024-07-09 Amazon Technologies, Inc. High-density microbump and probe pad arrangement for semiconductor components

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0770553B2 (ja) * 1988-09-26 1995-07-31 日本電気株式会社 半導体集積回路装置の製造方法
JP3723232B2 (ja) * 1992-03-10 2005-12-07 シリコン システムズ インコーポレーテッド プローブ針調整ツール及びプローブ針調整法
JPH0634983A (ja) 1992-07-17 1994-02-10 Sharp Corp 貼合わせ装置
US6025640A (en) * 1997-07-16 2000-02-15 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device
JP3000975B2 (ja) * 1997-10-20 2000-01-17 富士通株式会社 半導体素子の実装構造
US6008532A (en) * 1997-10-23 1999-12-28 Lsi Logic Corporation Integrated circuit package having bond fingers with alternate bonding areas
US6157085A (en) * 1998-04-07 2000-12-05 Citizen Watch Co., Ltd. Semiconductor device for preventing exfoliation from occurring between a semiconductor chip and a resin substrate
US6373143B1 (en) * 1998-09-24 2002-04-16 International Business Machines Corporation Integrated circuit having wirebond pads suitable for probing
TW410446B (en) * 1999-01-21 2000-11-01 Siliconware Precision Industries Co Ltd BGA semiconductor package
US6348742B1 (en) * 1999-01-25 2002-02-19 Clear Logic, Inc. Sacrificial bond pads for laser configured integrated circuits
JP3718360B2 (ja) * 1999-02-09 2005-11-24 ローム株式会社 半導体装置
JP3437477B2 (ja) * 1999-02-10 2003-08-18 シャープ株式会社 配線基板および半導体装置
US6251694B1 (en) * 1999-05-26 2001-06-26 United Microelectronics Corp. Method of testing and packaging a semiconductor chip
US6285077B1 (en) * 1999-08-19 2001-09-04 Lsi Logic Corporation Multiple layer tape ball grid array package
JP2001144214A (ja) 1999-11-17 2001-05-25 Canon Inc 半導体装置およびその接合構造
JP4071914B2 (ja) * 2000-02-25 2008-04-02 沖電気工業株式会社 半導体素子及びこれを用いた半導体装置
US6291898B1 (en) * 2000-03-27 2001-09-18 Advanced Semiconductor Engineering, Inc. Ball grid array package
US6429532B1 (en) * 2000-05-09 2002-08-06 United Microelectronics Corp. Pad design
JP2001338955A (ja) * 2000-05-29 2001-12-07 Texas Instr Japan Ltd 半導体装置及びその製造方法
US6541844B2 (en) * 2000-07-17 2003-04-01 Rohm Co., Ltd. Semiconductor device having substrate with die-bonding area and wire-bonding areas
JP2002043356A (ja) * 2000-07-31 2002-02-08 Nec Corp 半導体ウェーハ、半導体装置及びその製造方法
US6539341B1 (en) * 2000-11-06 2003-03-25 3Com Corporation Method and apparatus for log information management and reporting
US6538336B1 (en) * 2000-11-14 2003-03-25 Rambus Inc. Wirebond assembly for high-speed integrated circuits
US6417576B1 (en) * 2001-06-18 2002-07-09 Amkor Technology, Inc. Method and apparatus for attaching multiple metal components to integrated circuit modules
SG117395A1 (en) * 2001-08-29 2005-12-29 Micron Technology Inc Wire bonded microelectronic device assemblies and methods of manufacturing same
US6476506B1 (en) * 2001-09-28 2002-11-05 Motorola, Inc. Packaged semiconductor with multiple rows of bond pads and method therefor
TW510034B (en) * 2001-11-15 2002-11-11 Siliconware Precision Industries Co Ltd Ball grid array semiconductor package
US6621140B1 (en) * 2002-02-25 2003-09-16 Rf Micro Devices, Inc. Leadframe inductors
US6844631B2 (en) * 2002-03-13 2005-01-18 Freescale Semiconductor, Inc. Semiconductor device having a bond pad and method therefor
TW531776B (en) * 2002-03-21 2003-05-11 Nanya Technology Corp Metal pad structure suitable for connection pad and inspection pad

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100345291C (zh) * 2003-12-12 2007-10-24 精工爱普生株式会社 半导体装置和电子器件及其制造方法
CN100419982C (zh) * 2004-05-31 2008-09-17 松下电器产业株式会社 半导体装置
US7476969B2 (en) 2005-07-29 2009-01-13 Omron Corporation Semiconductor packages for surface mounting and method of producing same
CN101071810B (zh) * 2006-05-12 2010-12-22 瑞萨电子株式会社 半导体器件
CN102280425A (zh) * 2010-06-11 2011-12-14 卡西欧计算机株式会社 具备键合引线的半导体器件及其制造方法
CN102280425B (zh) * 2010-06-11 2014-05-28 卡西欧计算机株式会社 具备键合引线的半导体器件及其制造方法
CN102456812A (zh) * 2010-10-28 2012-05-16 展晶科技(深圳)有限公司 发光二极管封装结构
CN102456812B (zh) * 2010-10-28 2015-08-12 展晶科技(深圳)有限公司 发光二极管封装结构
CN108140577A (zh) * 2016-02-23 2018-06-08 瑞萨电子株式会社 半导体器件及其制造方法
CN109075148A (zh) * 2016-09-26 2018-12-21 株式会社Powdec 半导体封装体、模块及电气设备
CN108630630A (zh) * 2017-03-21 2018-10-09 瑞萨电子株式会社 半导体装置的制造方法和半导体装置
CN108630630B (zh) * 2017-03-21 2023-05-12 瑞萨电子株式会社 半导体装置的制造方法和半导体装置

Also Published As

Publication number Publication date
TWI297184B (en) 2008-05-21
CN100481414C (zh) 2009-04-22
TW200405491A (en) 2004-04-01
KR20040014167A (ko) 2004-02-14
US20030218245A1 (en) 2003-11-27
JP2003338519A (ja) 2003-11-28
US6900551B2 (en) 2005-05-31
US20050121805A1 (en) 2005-06-09

Similar Documents

Publication Publication Date Title
CN1459855A (zh) 半导体器件及其制造方法
CN1259024C (zh) 用于指纹识别的半导体装置
CN1151554C (zh) 半导体器件、其制造方法以及组合型半导体器件
CN1219322C (zh) 树脂密封型半导体装置及其制造方法
CN1265455C (zh) 半导体器件及其制造方法
US6060729A (en) Light-emitting device
KR101469770B1 (ko) 전력 소자 패키지 및 그 제조 방법
CN1149664C (zh) 带自动键合用带状载体、集成电路
CN1283004C (zh) 半导体装置及其制造方法、线路基板及电子机器
CN1531090A (zh) 半导体装置、电子设备及它们的制造方法，以及电子仪器
CN1516898A (zh) 半导体装置及其制造方法
CN1262784A (zh) 半导体装置及其制造方法、电路基板和电子装置
CN1338779A (zh) 半导体器件
CN1396653A (zh) 半导体装置
CN1622328A (zh) 半导体器件及其制造方法
CN1445851A (zh) 轻薄叠层封装半导体器件及其制造工艺
CN1665023A (zh) 树脂密封半导体器件和引线框架、及其制造方法
CN1490870A (zh) 引线框及其制造方法，以及用该引线框制造的半导体器件
CN1815733A (zh) 半导体装置及其制造方法
CN1494227A (zh) 用作电子标签的输入装置
CN1659698A (zh) 包括半导体器件的四方扁平无引线封装
CN1577841A (zh) 芯片层叠型半导体装置及其制造方法
US8530252B2 (en) Method for manufacturing light emitting diode
CN1641832A (zh) 半导体器件及其制造方法
CN1835222A (zh) 半导体器件及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090422

Termination date: 20140520