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CN1282242C - 芯片比例封装及其制造方法 - Google Patents

芯片比例封装及其制造方法 Download PDF

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Publication number
CN1282242C
CN1282242C CNB031010091A CN03101009A CN1282242C CN 1282242 C CN1282242 C CN 1282242C CN B031010091 A CNB031010091 A CN B031010091A CN 03101009 A CN03101009 A CN 03101009A CN 1282242 C CN1282242 C CN 1282242C
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Prior art keywords
chip scale
scale packages
chip
wafer
electrode surface
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Expired - Fee Related
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CNB031010091A
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CN1445844A (zh
Inventor
尹畯晧
崔龙七
裴锡洙
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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Abstract

本发明公开了一种芯片比例封装和制造芯片比例封装的方法。芯片比例封装包括在芯片的上表面和下表面上形成的具有指定深度的导电层、在导电层的相同侧面上形成的并连接到印刷电路板的相应连接焊盘上的电极面。在整个封装尺寸上使芯片比例封装小型化。另外，制造芯片比例封装的方法不需要引线接合步骤或通孔形成步骤，从而简化了芯片比例封装的制造过程并提高了芯片比例封装的可靠性。

Description

芯片比例封装及其制造方法
技术领域
本发明涉及芯片比例封装，更具体地说，涉及通过在芯片的两个表面上形成导电层以及通过在导电层的侧面上形成电极面以实现小型化和更容易制造的芯片比例封装，以及制造芯片比例封装的方法。
背景技术
通常，封装半导体设备诸如二极管然后将这些封装设备安装在印刷电路板上。在结构上，该封装容易将半导体设备的端子连接到印刷电路板的相应信号图案上并用来保护半导体设备免受外应力，从而提高封装的可靠性。
为满足近来半导体产品小型化的趋势，也已经将半导体芯片封装小型化。因此，已经引入芯片比例封装(也称为“芯片尺寸封装”)。
图1是常规芯片比例封装的示意性剖视图。图1的芯片比例封装10的结构采用陶瓷衬底，并且是具有两个端子的二极管封装。
参考图1，在陶瓷衬底1上形成两个通孔，即第一通孔2a和第二通孔2b。用导电材料填充第一和第二通孔2a和2b以便将衬底1的上表面电连接到衬底1的下表面。然后，分别在第一和第二通孔2a和2b的上表面上形成第一和第二上导电连接盘(conductive land)3a和3b。分别在第一和第二通孔2a和2b的下表面上形成第一和第二下导电连接盘4a和4b。将第二上导电连接盘3b直接连接到形成在二极管5的下表面上的端子，即，印刷电路板上的二极管5的安装面，以及将第一上导电连接盘3a通过导线7连接到形成在二极管5的上表面上的另一端子。在包括在二极管5的陶瓷衬底1的上表面形成使用常规树以便保护二极管5免受外应力。从而完成制造封装10。
图2是常规芯片比例封装装置的剖视图，其中将芯片比例封装安装在印刷电路板上。
如图2所示，通过回流焊接将制造的二极管封装10安装在印刷电路板20上。即，通过在印刷电路板20的相应信号图案上排列封装10的下导电连接盘4a和4b，然后用焊料15将下导电连接盘4a和4b连接到印刷电路板20的信号图案上，将二极管封装10安装在印刷电路板20上。
如图1和2所示，由于二极管通常具有在其两个相对面的每一个上的端子，这些端子必须通过导线内连接。然而，这些导线需要芯片的上表面上的很大空间，从而增加了封装的整个高度。另外，由于必须在陶瓷衬底上形成与二极管的端子数量相应的至少两个通孔，另外要求与通孔的总直径一样大的区域。因此，为了不使在通孔的上表面和下表面上形成的导电连接盘相互连接，必须用最小间隔使导电连接盘彼此分开。因此，衬底具有大尺寸以便满足上述条件，并且衬底的尺寸在小型化封装方面强加了限制。
另外，由上述封装采用的陶瓷衬底价格很高，从而增加封装的生产成本。因此，常规制造封装的过程要求引线接合步骤以及模塑步骤以及芯片焊接步骤，从而变得非常复杂。
因此，需要一种能小型化封装的尺寸以及简化其制造过程的封装技术。
发明概述
因此，鉴于上述问题创造了本发明，以及本发明的一个目的是通过在具有端子的芯片的上表面和下表面上形成导电层以及通过在导电层的侧面上形成电极面，来提供小型化和更容易制造的一种芯片比例封装，从而提高封装的可靠性。
本发明的另一目的是根据芯片比例封装的结构，提供一种具有创新安装方法的芯片封装装置。
本发明的另一目的提供一种制造芯片比例封装的方法。
根据本发明的一个方面，通过这样一种芯片比例封装来实现上述和其他目的，即，所述芯片比例封装具有第一端子的第一表面、具有第二端子的第二表面，第二表面与第一表面相对的芯片、分别在芯片的第一和第二表面上形成第一和第二导电层以及电极面，每个电极面形成在第一和第二导电层的侧面上。
根据本发明的另一方面，提供包括芯片比例封装和印刷电路板的芯片比例封装装置。芯片比例封装包括芯片，所述芯片具有第一端子的第一表面，具有第二端子的第二表面并且第二表面与第一表面相对的芯片，分别在芯片的第一和第二表面上形成第一和第二导电层以及电极面，每个电极面形成在第一和第二导电层的侧面上。印刷电路板包括用于连接到芯片比例封装的电极面的连接焊盘，以及连接到连接焊盘的电路图案。
根据本发明的另一方面，提供一种制造芯片比例封装的方法，包括下述步骤：(i)准备包括多个芯片的晶片，芯片包括分别在其上表面和下表面上的端子；(ii)形成导电层，每个导电层形成在晶片的上表面和下表面上；以及(iii)将晶片切成封装单元，每个封装单元包括芯片以及形成电极面，每个电极面形成在两个导电层的侧面上。
附图说明
通过下述结合附图的详细描述将更容易理解本发明的上述和其他目的、特征和其他优点，其中：
图1是常规芯片比例封装的示意性剖视图；
图2是常规芯片比例封装装置的剖视图，其中将芯片比例封装安装在印刷电路板上；
图3是根据本发明的优选实施例的芯片比例封装的透视图；
图4是芯片比例封装装置的透视图，其中根据本发明的优选实施例，将芯片比例封装安装在印刷电路板上；以及
图5a至5f是根据本发明的优选实施例，描述制造芯片比例封装的方法的每个步骤的剖视图。
具体实施方式
现在，将参考附图来详细地描述本发明的优选实施例。
图3是根据本发明的优选实施例的芯片比例封装的透视图。
参考图3，芯片比例封装30包括芯片35、形成在芯片35的上表面上的上导电层31a、形成在芯片35的下表面上的下导电层31b、形成在上导电层31a的一个侧面上的第一电极面33a以及形成在下导电层31b的一个侧面上的第二电极面33b。在这里，具有第一电极面33a的上导电层31a的侧面与具有第二电极面33b的下导电层31b的侧面在导电层31a和31b的相同的侧面上。芯片35包括在上表面上形成的上端子(未示出)以及在下表面上形成的下端子(未示出)。例如，芯片35是二极管。
将在芯片35的上表面上形成的上导电层31a连接到上端子(未示出)，以及将在芯片35的下表面上形成的下导电层31b连接到下端子(未示出)。上导电层和下导电层31a和31b可是由铜(Cu)制造成的金属层，但并不局限于此。上导电层和下导电层31a和31b必须具有指定深度，这根据印刷电路板上形成的连接焊盘间的间隔而定。即，由于在上导电层和下导电层31a和31b上形成的电极面33a和33b位于印刷电路板的相应连接焊盘上，因此上导电层和下导电层31a和31b要求具有足够的厚度。
可用常规电镀过程以预定深度形成上导电层和下导电层31a和31b。然而，使用电镀过程形成的上导电层和下导电层31a和31b需要长时间并产生较高的生产成本。因此，优选地，首先通过电镀形成电镀层。然后在电镀层上堆叠至少一层铜层，从而容易形成具有想要的深度的导电层。
另外，在上导电层31a的一个侧面上形成第一电极面33a，在下导电层31b的一个侧面上形成第二电极面33b。具有第一电极面33a的上导电层31a的侧面与具有第二电极面33b的下导电层31b的侧面均在上导电层和下导电层31a和31b的相同侧面上。将第一和第二电极面33a和33b电地和机械地连接到印刷电路板的相应连接焊盘上。因此，优选地，第一和第二电极面33a和33b是包括金(Au)的金属层以便以后进行焊接。
在上述芯片比例封装30中，将在芯片35的上表面和下表面上形成的上端子和下端子(未示出)通过上导电层和下导电层31a和31b分别连接到第一和第二电极面33a和33b。因此，具有第一和第二电极面33a和33b的侧面是印刷电路板上的安装面。即，将图3的芯片比例封装30旋转90度，然后将旋转后的芯片比例封装30安装在印刷电路板上，以便将第一和第二电极面33a和33b连接到印刷电路板的相应连接焊盘上。
为防止暴露在外的上导电层和下导电层31a和31b氧化，在除用于第一和第二电极面33a和33b外的上导电层和下导电层31a和31b上形成钝化层37。优选地，钝化层37是通过涂上绝缘树脂形成的绝缘薄膜。如果必要的话，可进一步在芯片35的外露侧面上形成钝化层37。
图4是芯片比例封装装置70的透视图，其中根据本发明的优选实施例将芯片比例封装40安装在印刷电路板51上。
如图4所示，芯片封装装置70包括芯片比例封装40和用于安装芯片比例封装40的印刷电路板51。芯片比例封装40包括芯片45、形成在芯片45的上表面上的上导电层41a、形成在芯片45的下表面上的下导电层41b、形成在上导电层41a的一个侧面上的第一电极面43a以及形成在下导电层41b的一个侧面上的第二电极面43b。在这里，具有第一电极面43a的上导电层41a的侧面与具有第二电极面43b的下导电层41b的侧面在上导电层和下导电层41a和41b的相同侧面上。第一和第二电极面43a和43b是印刷电路板51上的芯片比例封装40的安装面。通过上导电层和下导电层41a和41b分别将第一和第二电极面43a和43b连接到芯片45的上端子和下端子(未示出)上。通过将芯片比例封装40的第一和第二电极面43a和43b布置在印刷电路板51的相应连接焊盘53a和53b上以及通过在第一和第二电极面43a和43b和连接焊盘53a和53b间进行焊接，将芯片比例封装40安装在印刷电路板51上，从而完成图4的芯片封装装置70的制造。
通过连接到连接焊盘53a和53b的芯片比例封装40的第一和第二电极面43a和43b，将在印刷电路板51上形成的指定电路(未示出)连接到芯片45的每个端子上。如上所述，根据印刷电路板51的连接焊盘53a和53b间的间隔，第一和第二导电层41a和41b具有指定深度。
另外，本发明提供一种制造芯片比例封装的方法。图5a至5f是根据本发明的优选实施例，描述制造芯片比例封装的每个步骤的剖视图。
首先，如图5a所示，准备包括多个芯片的晶片125。在每个芯片的上表面和下表面上形成端子。在这里，按晶片125的上表面的虚线划分每个芯片。图5a表示晶片125的部分剖视图。然而，对本领域的技术人员来说具有多个芯片的晶片125的整个结构将是显而易见的。
芯片包括分别在其上表面和下表面上的上端子101a和101b。另外，在晶片125上形成具有多个窗口的掩膜图案118，从而暴露晶片125的端子区域。掩膜图案118的窗口与晶片125的端子区域相应。
如图5b所示，分别在晶片125的上表面和下表面上形成上导电层121a和121b。然后，分别在第一和下导电层121a和121上形成钝化层127a和127b。
分别将上导电层121a和121b连接到上端子和下端子101a和101b上。可通过电镀步骤形成上导电层和下导电层121a和121b。然而，优选地，通过形成电镀层，然后通过将至少一层铜层堆叠在电镀层上形成上导电层121a和121b，从而具有与印刷电路板的连接焊盘间的间隔相应的深度。
钝化层127a和127b防止上导电层和下导电层121a和121氧化，从而提高封装的可靠性。优选地，上导电层和下导电层121a和121b是通过涂上绝缘树脂形成的绝缘层。在仅使用根据芯片比例封装的使用条件自然形成的氧化层足以保护晶片125免受外应力的情况下，可省略钝化层127a和127b。另外，可不同应用形成钝化层127a和127b的步骤。即，将在以后描述的如图5f所示，在切割步骤后，可共同在导电层的上、下和侧面上形成钝化。然而，考虑到切割步骤期间导电层的氧化或将晶片的一个表面连接到胶带上，最好在该步骤形成钝化层127a和127b。
如图5C所示，首次切割晶片以便形成芯片比例封装的一个侧面。优选地，沿划线将晶片切割成两行。在包括两个芯片比例封装的首次切割的晶片130′中，仅将每个芯片比例封装的一个侧面暴露在外。
如图5d所示，分别在切割晶片130′的上导电层和下导电层121a和121b的侧面上形成第一和第二电极面133a和133b。通过第一和第二导电层121a和121b，将第一和第二电极面133a和133b连接到芯片的每个端子上。通过使用金(Au)的电镀过程，形成第一和第二电极面133a和133b。因此，不在用硅制成的芯片的侧面上以及用绝缘树脂制成的钝化层上形成电极面，而是在用金属制成的第一和第二导电层121a和121b的侧面上形成电极面。即，有选择地地晶片上形成第一和第二电极面133a和133b。
在形成第一和第二电极面133a和133b后，如图5e所示，然后再次切割第一切割晶片130′，从而形成多个芯片比例封装单元130″。然后，如图5f所示，在第一和第二导电层121a和121b的侧面上形成钝化层137，从而完成芯片比例封装140的制造。如图3所示。用与在图5b中所示的钝化层127a和127b相同的方式形成如图5f所示的钝化层137。即，同样通过涂上绝缘树脂来形成图5f中所示的钝化层137。
制作图5a至5f所示的芯片比例封装的方法是本发明的优选实施例。因此，在本发明的精神和范围内可不同地改变制作芯片比例封装的方法。具体来说，根据切割步骤可大大地改变图5c至5f所示的步骤。即，在首次切割晶片以便形成除了芯片比例封装的指定侧面的其它侧面后，分别在形成于通过切割步骤所获得的侧面上的导电层侧面上形成钝化层。然后，再次切割首次切割后的晶片，从而形成芯片比例封装单元。分别在形成于通过再次切割步骤所获得的侧面上的导电层侧面上形成电极面。然而，如上所述，在切割步骤前，将晶片附加和固定到胶带上。在该情况下，由于将较大尺寸晶片附加在胶带上，更稳定地进行制造过程。因此，优选地，将大面积的首次切割的晶片固定到胶带上。因此，如图5c至5f所示的上述步骤更可取。
根据制造本发明的芯片比例封装的方法，将晶片切割成多个具有一个芯片的芯片比例封装，以及在芯片比例封装的一个侧面上的两个导电层的一个侧面上形成电极面并在导电层的另一侧面上形成钝化层。因此，可按不同的顺序和方式改变用于形成芯片比例封装的侧面的每个切割步骤和用于形成钝化层和电极面的步骤。这些改变和改进均在本发明的精神和范围内。
从上面的描述可以看出，通过在芯片的上表面和下表面上形成导电层，每个芯片具有端子，以及通过在导电层的相同侧面上形成电极面，本发明提供一种小型化和更容易制造的芯片比例封装，从而提高封装的可靠性。另外，本发明提供一种用于制造芯片比例封装的方法，其中省略常规的引线接合步骤或通孔形成步骤，从而简化制造过程和减小制造成本。
尽管为了说明目的已经公开了本发明的优选实施例，但是本领域的技术人员将意识到在不脱离由附加权利要求公开的本发明的范围和精神的情况下，可能做出不同的改变、添加和代替。

Claims (6)

1.一种制造芯片比例封装的方法，所述方法包括如下步骤：
(i)准备包括多个芯片的晶片，所述芯片包括分别在其上表面和下表面上的端子；
(ii)形成导电层，每个导电层形成在晶片的上表面和下表面上；
(iii)形成钝化层的步骤，每个钝化层形成在第一和第二导电面的除具有电极面的侧面外的表面上；
(iv)在导电层的每个指定侧面上形成电极面后，将晶片切成封装单元，每个封装单元包括芯片，
其中步骤(iv)包括下列子步骤：
首次切割晶片，以便形成芯片比例封装的一个侧面；
在第一和第二导电层的侧面形成电极面，所述侧面形成在通过首次切割晶片获得的芯片比例封装的侧面上；
再次将晶片切割成封装单元；以及
在第一和第二导电层的侧面上形成钝化层，所述形成钝化层的侧面形成在通过再次切割晶片获得的芯片比例封装的侧面上。
2.如权利要求1所述的制造芯片比例封装的方法，其中步骤(iv)进一步包括形成钝化层的步骤，每个钝化层在第一和第二导电层的除具有电极面的侧面之外的外露表面上形成。
3.如权利要求2所述的制造芯片比例封装的方法，其中所述钝化层是用通过涂上绝缘树脂形成的绝缘薄膜制成。
4.如权利要求1所述的制造芯片比例封装的方法，其中首次切割晶片步骤是切割晶片以便将晶片的划线切割成两行的步骤。
5.一种制造芯片比例封装的方法，所述方法包括如下步骤：
(i)准备包括多个芯片的晶片，所述芯片包括分别在其上表面和下表面上的端子；
(ii)形成导电层，每个导电层形成在晶片的上表面和下表面上；以及
(iii)在导电层的每个指定侧面上形成电极面后，将晶片切成封装单元，每个封装单元包括芯片，
其中步骤(iii)包括下列子步骤：
首次切割晶片以便形成芯片比例封装的一个侧面；
在第一和第二导电层的侧面上形成钝化层，所述形成钝化层的侧面形成在通过首次切割晶片获得的芯片比例封装的侧面上；
再次将晶片切割成封装单元；以及
在第一和第二导电层的侧面上形成电极面，所述形成电极面的侧面形成在再次切割晶片获得的侧面上。
6.如权利要求5所述的制造芯片比例封装的方法，其中在首次切割步骤中，将晶片切割成两个封装单元。
CNB031010091A 2002-03-18 2003-01-06 芯片比例封装及其制造方法 Expired - Fee Related CN1282242C (zh)

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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1735807A (zh) * 2003-12-19 2006-02-15 成都夸常医学工业有限公司 芯片检测方法及相关装置
KR100816762B1 (ko) * 2007-01-02 2008-03-25 삼성전자주식회사 반도체 패키지 및 이를 탑재하기 위한 모듈 인쇄회로기판
JP2008252058A (ja) * 2007-03-08 2008-10-16 Toshiba Corp 半導体装置及びその製造方法
CN101685836B (zh) * 2008-09-26 2012-05-30 宏齐科技股份有限公司 晶片级直立式的二极管封装结构的制作方法
US8053885B2 (en) * 2009-01-12 2011-11-08 Harvatek Corporation Wafer level vertical diode package structure and method for making the same
CN102117789B (zh) * 2010-01-04 2013-12-04 三星半导体(中国)研究开发有限公司 半导体芯片封装结构及封装方法
TWI501363B (zh) * 2014-01-10 2015-09-21 Sfi Electronics Technology Inc 一種小型化表面黏著型二極體封裝元件及其製法
CN103956250B (zh) * 2014-05-13 2017-01-25 华为技术有限公司 表贴型平面磁性元件及模块
US10679965B2 (en) * 2015-02-04 2020-06-09 Zowie Technology Corporation Semiconductor package structure with preferred heat dissipating efficacy without formation of short circuit
TWI651830B (zh) * 2015-02-17 2019-02-21 立昌先進科技股份有限公司 多功能小型化表面黏著型電子元件及其製法
US9728935B2 (en) * 2015-06-05 2017-08-08 Lumentum Operations Llc Chip-scale package and semiconductor device assembly
KR20180094345A (ko) 2017-02-15 2018-08-23 주식회사 모다이노칩 칩 패키지

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4021839A (en) * 1975-10-16 1977-05-03 Rca Corporation Diode package
JPS60198759A (ja) * 1984-03-22 1985-10-08 Toshiba Corp リ−ドレス半導体素子
US5403729A (en) 1992-05-27 1995-04-04 Micro Technology Partners Fabricating a semiconductor with an insulative coating
JPH0927591A (ja) * 1995-07-10 1997-01-28 Hitachi Ltd 半導体装置およびその製造方法ならびに実装方法
JP3405494B2 (ja) * 1995-08-28 2003-05-12 株式会社日立製作所 チップ型ダイオードモジュール
US5994167A (en) * 1997-05-21 1999-11-30 Zowie Technology Corporation Method of making a fiberglass reinforced resin plate
JPH11111742A (ja) * 1997-09-30 1999-04-23 Hitachi Ltd 半導体装置およびその製造方法
KR100269540B1 (ko) 1998-08-28 2000-10-16 윤종용 웨이퍼 상태에서의 칩 스케일 패키지 제조 방법
JP3312121B2 (ja) * 1998-12-09 2002-08-05 シャープ株式会社 チップ部品型の発光ダイオードの製造方法
TW408411B (en) * 1999-03-31 2000-10-11 Huang Jr Gung Semiconductor chip scale package
US6271060B1 (en) * 1999-09-13 2001-08-07 Vishay Intertechnology, Inc. Process of fabricating a chip scale surface mount package for semiconductor device
DE19944256C2 (de) * 1999-09-15 2002-12-12 Ernst Markart Teststreifen und Meßgerät zu seiner Vermessung

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