CN1160781C - 分立半导体器件及其制造方法 - Google Patents
分立半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN1160781C CN1160781C CNB981024785A CN98102478A CN1160781C CN 1160781 C CN1160781 C CN 1160781C CN B981024785 A CNB981024785 A CN B981024785A CN 98102478 A CN98102478 A CN 98102478A CN 1160781 C CN1160781 C CN 1160781C
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- discrete semiconductor
- semiconductor device
- resin
- semiconductor elements
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Abstract
本发明涉及分立半导体器件,特别是涉及小信号用的分立半导体器件,提供安装面积小的高频特性好的散热效率良好的分立半导体元件及其制造方法。在小片连接垫片和引线连接垫片上安装分立半导体元件,利用把所述的安装面包封树脂的分立半导体器件,把所述的小片连接垫片和引线连接垫片直接连接到母板上。
Description
技术领域
本发明涉及分立半导体器件,特别是涉及高频特性和散热性优良的用于小信号的分立半导体器件。
背景技术
以前的分立半导体器件,通常如图25所示,利用DIP(双列直插式组件)进行安装。图25(a)是树脂封装型DIP俯视图,图25(b)是树脂封装型DIP侧视图。图中各标号分别表示为,2是表示封装树脂,8是表示分立半导体元件,9是表示连接分立半导体元件8电极和内部引线39的连线,38是表示固定分立半导体元件8的岛状区,39是表示内部引线,40是表示外部引线。
这样的树脂模制型DIP。如图26所示,在引线框架41的岛状区38通过垫片连接来固定分立半导体元件8,利用金引线9连接分立半导体元件8电极和内部引线后,利用独立的金属模进行树脂封装各分立半导体元件8,最后从引线框架41切割分离引线制造分立半导体器件(图27)。
在把上述分立半导体器件安装到模板的情况,由于利用从封壳侧面伸出外面的外引线40连接母板,存在安装面积变大的问题。
还存在这样的问题,连接分立半导体元件和母板接线变长,因此分立半导体元件的高频区域损耗变大,不能得到良好的高频特性。
而且,还存在下述问题,因为利用热传导小的封装树脂进行封装分立半导体元件,散热效率低,不能装载输出大的分立半导体元件。
对此,如特开平8-236665号公报所示,IC芯片不用引线,提出一种方法,利用设置在安装IC芯片的树脂封装型半导体器件背面的凸点来安装母板的方法。
可是,和利用小功率元件的IC相比,由于在分立半导体元件利用了如大功率的MOS器件那样的高输出的元件,只从凸点传热,所以半导体器件散热不良。还有,在利用高频元件的情况,为了改善高频特性,需要把高频元件的电极和安装这样的高频元件的母板的距离限定在短距离的范围。
而且,对于以前的树脂封装型分立半导体器件的制造工序,分别把封装树脂注入到对于每个半导体器件利用各自金属模的这样的金属模中,用这样的方法,如果改变半导体器件的外形尺寸和形状,每次必须制作新的金属模,则难于缩短半导体器件的开发时间和降低开发费用。
还有,在利用引线框架的情况,因为不要改变引线部分以外的框架周边部分,所以难于降低制造成本。
发明内容
因此,本发明的目的是解决分立半导体元件的上述问题,提供安装面积小的高频特性优良的散热效率好的分立半导体元件及其制造方法。
所以,发明者专心致力研究的结果,把分立半导体元件安装在小片连接的垫片和引线连接的垫片上,利用把这样的安装面包封的分立半导体器件,能把这样的小片连接的垫片和引线连接的垫片的背面直接连接到母板上,发现能达到上述目的,从而完成本发明。
本发明的一种分立半导体器件,包括:限定多个开口的绝缘薄片;小片连接垫片和引线连接垫片,在该绝缘薄片的背面上以一定间隔重叠相应的开口,所述引线连接垫片具有一内表面和一外表面,分立半导体元件,固定在所述小片连接垫片的相应的内表面上,所述分立半导体元件包括电连接到所述引线连接垫片的相应内表面的电极,和包封树脂,设置在要包封所述的分立半导体元件的所述的小片连接垫片和所述的引线连接垫片的一面上。
即,本发明是涉及下述构成的分立半导体器件,包括按所定距离设置的的小片连接的垫片和引线连接的垫片,固定在所述小片连接的垫片上并且具有和所述引线连接垫片电连接的电极的分立半导体元件,在包封所述分立半导体元件的所述小片连接的垫片和引线连接的垫片的单面设置包封树脂。
这样的分立半导体器件,在分立半导体器件的一面不包封树脂,利用这样的不包封树脂背面的小片连接的垫片和引线连接的垫片,直接和母板连接。
因而,第一,和以前的利用引线安装的情况进行比较,由于在分立半导体器件的背面具有接触部则能使安装面积小。还有由于背面的小片连接的垫片和引线连接的垫片及母板利用焊锡直接连接,和利用凸点结构相比则能使安装高度减小。
第二,在小片连接的垫片上直接固定分立半导体元件,由于在母板上直接连接小片连接的垫片,和通过引线散热的以前的结构相比能大幅度地提高分立半导体元件的散热效率。因此能利用大功率MOS器件等发热量的元件。
第三,由于小片连接的垫片和引线连接的垫片,直接和母板连接,能缩短分立半导体器件和母板的连接距离,能提高在高频段利用分立半导体器件情况的高频特性。
还有,本发明分立半导体器件,其特征是,所述小片连接的垫片和引线连接的垫片是这样的结构,除以一定间距在绝缘薄层的背面的所定位置固定导电的金属板,把该金属板上的所述绝缘薄层开口构成单面安装的基板,为了包封所述分立半导体元件把所述包封树脂设置在所述单面安装基板的单面上。
通过在绝缘层上形成小片连接垫片和引线连接垫片,易于同时制作多个半导体器件。
还有,本发明分立半导体器件,其特征是,所述小片连接的垫片和引线连接的垫片是,作为支持体切断在导电金属板上形成所述包封树脂的所述金属板,以所留的所定的间隔固定小片连接的垫片和引线连接的垫片,为了包封所述分立半导体元件把所述包封树脂设置在小片连接的垫片和引线连接的垫片的单面上。
因此,通过把留所定间隔形成的金属板作为小片连接的垫片和引线连接的垫片,能制造分立半导体器件,串联和并联共有引线连接垫片结构的多个半导体元件。
上述分立半导体器件能在其背面具有电极,并且和所述的引线连接垫片电连接。
象这样,由于在导电的引线连接垫片上直接固定具有背面电极的分立半导体元件,则能提高散热效率,同时缩短布线长度。
还有,所述的半导体元件最好是二极管或晶体管,并且,所述的金属板最好由导电的热导率高的铜构成。
还有,本发明利用整体的包封树脂进行树脂包封多个上述分立半导体元件,构成分立半导体器件。
多个上述分立半导体元件,共同利用所述的小片连接的垫片和/或引线连接的垫片,利用整体的所述的封装树脂对其进行封装。
由此,串联和并联分立半导体元件,并且把串联和并联分立半导体元件树脂封装成一个整体结构,得到分立半导体器件。
还有,本发明涉分立半导体器件的制造方法,其特征是包括下列工序,在绝缘薄片的背面一定位置分别固定导电的金属板,同时把该金属板上的所述的绝缘薄片开口,形成多组小片连接垫片和引线连接垫片,安装所述分立半导体元件,该安装工序把分立半导体元件的背面分别固定在所述的小片连接垫片上,电连接各分立半导体元件的电极和所述的引线连接垫片,用树脂包封所述的绝缘薄片的安装面,用整体包封树脂包封在所述的绝缘薄片的内表面上安装的所述多个分立半导体元件,和在所述的分立半导体元件的四周切断所述的包封树脂,以便将所述包封树脂分割成分立半导体器件。
利用这样的方法,因为能利用一金属模由整体的包封树脂进行树脂包封绝缘薄片上的多个分立半导体元件,然后把它切断形成各分立半导体器件,所以象以前的方法那样,对每个分立半导体器件不需要利用树脂封装的金属模。
因而,在变化安装的分立半导体元件的尺寸和形状的情况下,只改变包封树脂的切断位置,不伴随金属模的变更,而能变更封装树脂的外形。
由此,能缩短分立半导体器件的开发时间,降低开发费用,特别是关于需要进行多品种少量生产的分立半导体器件,其效果更好。
还有,不象利用引线框架那样情况,不制造引线框架,能使成本降低。
所述的安装工序可以包括,在所述的小片连接垫片上固定分立半导体元件背面电极,电连接所述的小片连接垫片和上述电极的工序。
所述的分割工序也可以是分割成分立半导体器件的工序,把多个所述的分立半导体元件作为一个整体,在其周围切断所述的封装树脂,用所述的整体封装树脂进行树脂封装多个所述的分立半导体元件。
利用这样的工序,能容易地制造用包封树脂把多个分立半导体元件包封成一个整体的结构。
还有,本发明涉及分立半导体器件的制造方法,其特征是包括下列工序,安装多个分立半导体元件,所述安装工序包括:把所述多个分立半导体元件的背面固定在导电金属板上,电连接各分立半导体元件的电极到所述金属板的指定位置,用整体包封树脂包封所述金属板的安装面,从背面切割所述金属板,使所述的金属板成为按间隔设置的小片连接垫片和引线连接垫片,在所述的分立半导体元件的四周切断所述的包封树脂,分割各分立半导体器件。
这样的方法,即使在变化安装的分立半导体元件尺寸和形状的情况下,由于只改变切断包封树脂的位置,加之能在不伴随封装树脂用的金属模变更情况下来改变包封树脂的外形,也能容易得到具有串联并连分立半导体元件,并且用树脂包封分立半导体元件形成一个整体的结构的分立半导体器件。
所述的安装工序可以包括,在所述的金属板上固定分立半导体元件的背面,电连接所述的金属板和上述背面电极的工序。
所述的分割工序可以是分割成分立半导体器件的工序,把多个所述的分立半导体元件形成一个整体,在其周围切断所述的包封树脂,用整体包封树脂进行树脂包封多个所述的分立半导体元件。
能不伴随包封树脂用的金属模的变更而容易得到具有把多个分立半导体元件包封成一个整体的结构的分立半导体器件。
所述的切断工序是切断所述的金属板的工序,把连接多个所述的分立半导体元件的所述的小片连接垫片和域所述的引线连接垫片形成为一个整体,所述的分割工序可以是分割分立半导体器件的工序,把所述的小片连接垫片和/或所述的引线连接垫片形成为一个整体,在这样形成的所述的分立半导体元件的周围,切断上述包封的树脂,共用上述小片连接垫片和引线连接垫片,用所述的树脂把多个所述的分立半导体元件用树脂包封成一个整体。
能不伴随包封树脂用的金属模而容易获得这样的半导体器件,具有串联并联多个分立半导体元件并且把多个分立半导体元件由树脂包封成整体的结构。
附图说明
图1是本发明实施例1的分立半导体器件的透视图。
图2(a)是本发明实施例1的单面安装基板的俯视图。
图2(b)是沿图2(a)A-A’的剖面图。
图3是本发明实施例1的在母板装载分立半导体器件情况的剖面图。
图4是本发明实施例1的分立半导体器装配流程图。
图5是片状单面安装基板的俯视图。
图6是小片连接工序后单面安装基板的俯视图。
图7是引线连接工序后单面安装基板的俯视图。
图8是树脂包封工序后单面安装基板的俯视图。
图9(a)是树脂包封工序后单面安装基板的俯视图。
图9(b)是树脂包封工序后单面安装基板的剖面图。
图10是作标记工序后单面安装基板的俯视图。
图11(a)是框架装配架固定后的俯视图。
图11(b)是沿图11(a)的B-B‘的剖面图。
图12是分割工序后单面安装基板的俯视图。
图13是用带缠绕工序后的俯视图。
图14是本发明实施例2的分立半导体器件的透视图。
图15是本发明实施例2的分立半导体器件的俯视图。
图16是沿图14C-C‘的剖面图。
图17是铜框架的俯视图。
图18是小片连接工序后的俯视图。
图19是引线连接工序后的俯视图。
图20是分割工序后分立半导体器件的剖面图。
图21(a)是本发明实施例3的分立半导体器件的透视图。
图21(b)是本发明实施例3的分立半导体器件的俯视图。
图22是本发明实施例4的分立半导体器件的透视图图。
图23(a)是本发明实施例4的分立半导体器件的俯视图。
图23(b)是沿图22D-D’的剖面图。
图24(a)是本发明实施例4的另一个分立半导体器件的俯视图。
图24(b)是本发明实施例4的另一个分立半导体器件的剖面图。
图25(a)是已有结构的分立半导体器件的俯视图。
图25(b)是已有结构的分立半导体器件的剖视图。
图26(a)是表示用于制造已有结构的分立半导体器件的引线框架。
图26(b)是引线框架部分的放大图。
图27是已有结构的分立半导体器件的装配流程图。
具体实施方式
实施例1
参看附图说明本发明实施例1。
图1是关于实施例1的半导体器件100的透视图,由单面安装基板1和封装树脂2构成。
图2(a)是装载半导体芯片前述单面安装基板1的俯视图。图2(b)是关于A-A’的剖面图。
在单面安装基板1上面,通过具有开口的绝缘聚酰亚胺膜4固定铜箔,并且使铜箔两面露出,外形尺寸为1.2×1.0×0.55t(mm)。这样的铜箔,把铜箔的两面作为连接电极,用作小片连接垫片5和引线连接垫片6。
在小片连接垫片5的上面固定分立半导体元件8,在引线连接垫片6的上面连接Au引线。另一方面,小片连接垫片5和引线连接垫片6的背面,成为在把半导体器件100连接在母板上的外部连接端。
图3是关于实施例1的把半导体器件100装载在母板10上的剖面图。
在图3在单面布线基板1的小片连接垫片5的表面通过背面电极固定分立半导体元件8,利用Au引线9分别连接分立半导体元件8的表面电极和单面安装基板1的引线连接垫片6。还有,为了保护分立半导体元件8和Au引线9,在单面基板1的上面形成环氧树脂系列的包封树脂2。该分立半导体器件100的小片连接垫片5和引线连接垫片6的背面,通过焊接材料11和母板10的连接电极相连。
这样的半导体器件100,因为通过由热导率高的铜箔等形成的小片连接垫片5和引线连接垫片6,使分立半导体元件8直接和母板10相连,所以提高了分立半导体元件8的散热特性。
还有,因为,分立半导体元件8的背面电极和小片连接垫片5直接相连,分立半导体元件8和小片连接垫片6由Au引线9相连,并且这样的小片连接垫片5和引线连接垫片6和母板直接相连,所以象以前一样,和通过引线连接分立半导体元件8与母板10的情况相比,能缩短布线的距离。因而在高频段利用分立半导体器件100的情况,能降低损耗和提高高频特性。
还有,因为分立半导体器件100的背面直接作为外部接线端,能和母板10直接相连,与用引线连接情况和用凸点电极连接情况相比,能减小安装面积和降低高度。因而,能使安装分立半导体器件100的母板10小型化和薄型化。
其次,利用图4~图13说明本实施例的分立半导体器件的制造方法。
图4是表示本实施例的分立半导体器件100的装配流程图。在图5中,16表示把片状的分立半导体元件分割成单个的分立半导体元件8的切片工序,17表示装载在把分割成单个的分立半导体元件8以矩阵形状排列的在小片连接垫片上的工序,18表示利用Au引线9连接小片连接分立半导体元件8的电极和引线连接垫片6的连接工序,19表示由环氧树脂2进行树脂包封分立半导体元件8和Au引线9的工序,20表示在半导体器件100上面附加标记的作标记工序,21表示把片状基板分割成单个的分立半导体器件10的分割工序,22表示进行检查分立半导体器件100的检查工序,23表示包装检查合格的半导体器件100的带缠绕工序。通过所述的8个工序进行装配分立半导体器件100。
关于本实施例的分立半导体器件100的制造方法,如图5所示,首先准备片状单面安装基板1。图中12是聚酰亚胺等材料制成的片状基板,把图2(a)所示的布线图形设置成矩阵形状。还有,13是用于决定片状基板12位置的2.0mmΦ的通孔,14是传送片状基板12的传送用的装料槽,15是分割片状基板时的切断线,在片状基板12上电镀形成的东西。片状基板12的外形,例如,是35×38×0.75t(mm),构成小片连接垫片5和引线连接垫片6组合结构,100个布线图形,隔开切断线15的间隔(约0.1mm)设置成矩阵形状。
这样的布线图形,在所定位置形成开口的聚酰亚胺薄膜等片状部件的背面,分别热压铜箔等导电的金属箔,利用光刻技术腐蚀这样的金属箔,只在开口的背面残留金属箔。
其次,如图6所示,把切成小片的分立半导体元件8,利用Au环氧树脂连接固定在片状基板12的小片连接垫片5上。
本实施例,因为分立半导体元件8有背面电极,利用所述的连接工序连接背面电极和小片连接垫片5。
还有,该实施例的制造方法能同样适用没有背面电极的分立半导体元件。
这样一来,把分立半导体元件8固定在按矩阵形状设置布线的整个小片连接垫片5上。利用以前的引线框架的结构,必须逐个的固定分立半导体元件8,而本实施例能成批的小片连接,则能减少制造工序。
其次,如图7所示,用Au引线9电连接分立半导体元件8表面上的电极和片状基板12上引线连接垫片6。
其次,如图8所示,在片状基板12安装面进行树脂封装。进行树脂封装工序,加热环氧树脂系包封树脂,边加压边融化,把这样的熔化的包封树脂注入到片状树脂基板12所定位置的金属空腔中。图8中,25是表示各分立半导体器件100的电极方向在包封树脂2上形成的穴部。
在利用以前的引线框架的方法中,对于每个半导体器件100单独利用金属型空腔形成包封树脂2,但是,本实施例在片状树脂基板12上设置矩阵形状的数百个半导体器件的包封树脂2,利用一个金属模空腔整体的形成。
因此,比以前的方法,能增加树脂制造步骤和提高包封树脂的制造效率。
其中,在图8作为表示分立半导体器件的电极方向的部件在包封树脂2形成槽部24,但是如图9(a)(b)所示,能利用使各分立半导体器件一面包封厚度薄的部件(利用这样形状的金属模空腔)。这样的构造,能把包封树脂薄的部分用作后述分立半导体器件100中的切断部分,容易切断,同时可排队确认利用整体馈线情况的电极方向。
其次,如图10所示,在片状基板12上形成的包封树脂2上面,利用激光标记等作标记装置,作标一定的文字。图10标记由分立半导体器件的[LF]构成的文字。
其次,如图11(a)(b)所示,片状基板12,由于利用切片装置分割分立或单个半导体器件100,把下面粘着包封树脂2侧作为下面,利用粘结带28固定在框架装配架27上。图11(a)表示固定在框架装配架上的俯视图,图11(b)表示沿B-B的剖面图。
还有,如图2所示,利用粘结带28固定框架装配架27上的片状基板12,利用切片装置沿所定的切断线15由背面(片状基板12侧)进行切断,形成各分立半导体器件100。
这样,本实施例的制造方法,因为利用不能由金属模的空腔决定半导体器件的外形切断工序,所以能通用外型不同的其他机型和金属模。因此,每个机型不必要制造金属模,能减低成本。
还有,机种变化时不需要金属模变化作业,能提高制造效率。
切断的各分立半导体器件100,在贴上粘接带28的情况,进行检测工序。在检测工序,在每个区域由分立半导体器件的小片连接垫片5和引线连接垫片6的背面构成的外部接线端,压着接触引线端等的接线端,在各区进行成批处理。因此,和检查各半导体器件的情况相比,能减少检查时间和节省劳力。
最后,如图13所示,从所述的粘接带28取下通过检查判定为合格品的分立半导体器件包装在载带上。图13中,29是包装半导体器件的载带。具有以前那样引线的半导体器件,因为树脂包封突出的外引线抗外力弱,包封树脂厚使半导体器件高度高等等理由,不能利用纸制的载带,必须利用高价的聚氯乙烯和聚苯乙烯等塑料压制的带。
与此相反由于本发明的分立半导体器件,是无引线的构造,不发生引线的曲折,并且由于半导体元件本身是薄型元件,所以能利用廉价的纸制的载带。因此,减少塑料制品的使用量,而且有效地防止地球资源减少和环境污染的发生。
实施例2
参照附图说明本发明的实施例2。
图14是实施例2的分立半导体器件101的透视图,它由铜基板30和包封树脂2构成。
图15是实施例2的分立半导体器件101的俯视图(除去包封树脂2状态)。
分立半导体器件101的外形是,1.6×2.1×0.65t(mm),铜板的厚度是0.1mm。
图16是沿图14的C-C的剖面图。
和实施例1一样,在由铜构成的小片连接垫片5上,装载分立半导体元件8,由Au引线9连接分立半导体元件8和引线连接垫片6。还有,为了保护分立半导体元件8和Au引线9利用环氧树脂系包封树脂2用树脂包封安装面。
这样的分立半导体器件101,通过利用焊料11把由小片连接垫片5和引线连接垫片6的背面形成的外部接线端连接到母板10上,这样的分立半导体器件101安装在母板10上。
因为通过由热导率高的铜板构成的引线连接垫片6把分立半导体元件8直接连接到母板10上,能提高散热率。
还有,因为从分立半导体元件8到引线连接垫片6的布线是Au引线9的长度,所以能缩短布线的距离,在高频段利用分立半导体器件101的情况,能把损耗抑制到最小程度。
还有,不用凸点而把小片连接垫片5和引线连接垫片6的背面作为外部连接端直接连接分立半导体器件101和母板10,则能谋求分立半导体器件101的小型化和薄型化。
其次,参照图17~20说明本实施例的分立半导体器件101的制造方法。
本实施例的分立半导体器件101的制造方法,如图17所示,首先,准备铜框架31,设置在中央安装分立半导体器件8的装配区32。这样的装配区32或铜框架31,电镀AgPd等用于安装芯片。这样的铜框架31,因为不设置固定连接分立半导体器件8的布线图形,所以必须预先设定分立半导体器件8的位置。
图中,33是用于决定铜框架位置的Ф2.0mm的贯通孔,34是为了防止铜框架31热变形而设置的凹槽。还有,35是分割铜框架31时的切断线,切入铜框架31的沟。对于铜框架31的尺寸,外形尺寸是47×47×0.1t(mm),装配区尺寸32是22×22(mm)。
本实施例的装配流程图是和图4所示的实施例1的情况相同。
其次如图18所示,在铜框架31的所定位置用导电连接材料24以矩阵形状连接分立半导体器件8和小片连接。,根据分立半导体器件的外形来判断设置在铜框架31的切断线,分立半导体元件8的连接位置是构成如图15所示的小片连接垫片5的位置。实施例2和实施例1一样,为了能成批的用小片连接所定组的分立半导体元件8,能降低成本。
其次,如图19所示,用铜引线9电连接铜框架31的一定的位置和分立半导体元件8的电极。和分立半导体元件8小片连接位置相隔预定距离在分立半导体元件8的两测位置进行引线连接。
接着利用和实施例1相同的方法,用整体封装树脂进行树脂封装铜框架31安装面,在包封树脂上的一定位置进行标记后,如图20所示,进行切断铜框架31的工序。
进行标记后的铜框架31,在实施例1中用的框架装配架27上设置的粘接带28上,把树脂封装面作为下面固定,切断铜框架31,分割成小片连接垫片5和引线连接垫片6。
这样的切断工序,在实施例1,利用小片切割装置,沿所定的切断线15进行切断,分割分立半导体器件100,在本实施例通过切断铜框架31和树脂来分割分立半导体器件101,同时切断铜框架31,形成小片连接垫片5和引线连接垫片6。
图20中,36是用于利用小片切割装置切割分立半导体器件101的切断部,37是利用激光切割装置成切断分立半导体器件101的铜框架31,电隔离小片连接垫片5和引线连接垫片6之间形成的切断部。
最后,和实施例1一样,进行检查工序,由粘接带选定合格品取出分立半导体器件101包捆在载带上。
实施例3
图21(a)是本实施例的分立半导体器件103的透视图,图21(b)是分立半导体器件103的俯视图。
本实施例的分立半导体器件103,一个分立半导体器件103是由装载两个分立半导体元件8的结构构成。
即,在实施例1,如图12所示的分割工序,分别切断各分立半导体元件8的四周,各分立半导体器件100是作为装载各分立半导体元件8的结构,而本实施例如图21(b)所示,切断两个分立半导体元件8的四周,每个分立半导体器件103是装载两个分立半导体元件8结构。
象这样,本实施例,只是改变分割工序的切断位置作装载多个分立半导体元件8的分立半导体器件103,对应用户的要求,能容易变化装载的分立半导体元件8。
因此,这样的构造,能更大的减少分立半导体器件103的安装面积和安装成本。
如图21(b)所示,通过改变分割工序的切断位置,无论设置纵向横向的任意位置都能容易的制造分立半导体元件8。
还有,利用本实施例的方法,能容易的制造把3个分立半导体元件8设置在1个分立半导体器件103中的结构。
实施例4
图22是表示本发明4的分立半导体器件104的透视图。图23(a)是表示本实施例分立半导体器件104的俯视图,图23(b)是沿图22D-D′的剖面图。
本实施例的分立半导体器件104和实施例3一样,成为在一个分立半导体器件104装载两个分立半导体元件8的结构。
本实施例的分立半导体器件104的制造方法,在实施例2中改变包封树脂和铜框架31的切断位置36,能容易的进行。
即图在20所示的实施例12的切断工序,在每个分立半导体元件8的四周不设置包封树脂的切断沟36,把两个分立半导体元件8作为一组切断包封树脂进行制作。
象这样,本实施例,只是改变分割工序的包封树脂的切断位置,能制造装载多个分立半导体元件8的分立半导体器件104,根据用户要求能改变装载的分立半导体元件8。
还有,这样的构造,能减少分立半导体器件104的安装面积和安装成本。
图22(a)是分立半导体器件104‘的俯视图,有关本实施例的的分立半导体器件104‘装载两个分立半导体元件8,共用引线连接垫片6,串联连接,图22(b)是分立半导体器件104‘的剖面图。
能这样地制造分立半导体器件104,在所述的切断工序,不切断两个分立半导体元件8之间的铜框架31,两个分立半导体元件8共用整体的引线连接垫片6。
这样,本实施例改变分割工序包封树脂和金属板的切断位置只是设置不切断的区域,能制造电气地装载多个分立半导体元件8的分立半导体器件104,根据用户的要求能容易的变化装载的分立半导体元件8。
图24表示形成共用的引线连接垫片6,串联连接各分立半导体元件8,但是形成共用的小片连接垫片5和引线连接垫片6,也能并联分立半导体元件8。
还有,利用串联或并联结构,用同样的方法也能制造3个以上的分立半导体元件8。
由上述说明可知,根据本发明的分立半导体器件,和利用以前的引线情况相比,能使安装的面积减小,并且,由于能减小安装高度,所以能提供能高密度封装的分立半导体元件。
还有,因为能大幅度的提高分立半导体元件的散热效率,所以能使用功率MOS器件等大的分立半导体元件。
还有,能缩短分立半导体元件和母板的连接距离,能提高在高频段利用的分立半导体器件的高频特性。
还有,根据本发明利用的制造方法,因为在不伴随金属模变化的情况,能变化分立半导体器件的外形,所以,能缩短分立半导体器件100的开发时间,降低开发费用,特别是,对于所需多品种生产量少的分立半导体器件,其效果很好。
还有,象利用引线框架那样,不产生不需要的引线框架,则能谋求降低制造的成本。
还有能容易的制造装载多个分立半导体元件的分立半导体器件。
还有,能串联并联装载多个分立半导体元件的分立半导体器件。
Claims (12)
1.一种分立半导体器件,其特征在于包括:
限定多个开口的绝缘薄片;
小片连接垫片和引线连接垫片,在该绝缘薄片的背面上以一定间隔重叠相应的开口,所述引线连接垫片具有一内表面和一外表面,
分立半导体元件,固定在所述小片连接垫片的相应的内表面上,所述分立半导体元件包括电连接到所述引线连接垫片的相应内表面的电极,和
包封树脂,设置在要包封所述的分立半导体元件的所述的小片连接垫片和所述的引线连接垫片的一面上。
2.按照权利要求1所述的分立半导体器件,其特征在于:
所述小片连接垫片和引线连接垫片是导电的金属板,固定在所述绝缘薄片上一定的位置,和
所述的包封树脂,设置在为包封所述的半导体元件的所述小片连接垫片和引线连接垫片的一面上。
3.按照权利要求2所述的分立半导体器件,其特征在于,用整体的所述的包封树脂包封所述多个分立半导体元件。
4.按照权利要求1所述的分立半导体器件,其特征在于,所述多个分立半导体元件的各个通常具有所述小片连接垫片和/或引线连接垫片,并用所述树脂包封。
5.按照权利要求1所述的分立半导体器件,进一步包括:所述分立半导体器件背表面上的多个电极,电连接到所述引线连接垫片。
6.一种分立半导体器件的制造方法,其特征在于包括以下工序:
在绝缘薄片的背面一定位置分别固定导电的金属板,同时把该金属板上的所述的绝缘薄片开口,形成多组小片连接垫片和引线连接垫片,
安装所述分立半导体元件,该安装工序把分立半导体元件的背面分别固定在所述的小片连接垫片上,电连接各分立半导体元件的电极和所述的引线连接垫片,
用树脂包封所述的绝缘薄片的安装面,用整体包封树脂包封在所述的绝缘薄片的内表面上安装的所述多个分立半导体元件,和
在所述的分立半导体元件的四周切断所述的包封树脂,以便将所述包封树脂分割成分立半导体器件。
7.按照权利要求6所述的方法,其特征在于,所述安装工序进一步包括将所述的分立半导体器件的一个背面电极固定在相应的小片连接垫片上以电连接所述小片连接垫片和该背面电极。
8.按照权利要求6所述的方法,其特征在于,所述分割工序包括切断组成一体的多个分立半导体元件四周的包封树脂,使得至少一个所述分立半导体器件包括用整体的包封树脂包封的多个所述的分立半导体元件。
9.一种分立半导体器件的制造方法,其特征在于包括下列工序:
安装多个分立半导体元件,所述安装工序包括:把所述多个分立半导体元件的背面固定在导电金属板上,电连接各分立半导体元件的电极到所述金属板的指定位置,
用整体包封树脂包封所述金属板的安装面,
从背面切割所述金属板,使所述的金属板成为按间隔设置的小片连接垫片和引线连接垫片,
在所述的分立半导体元件的四周切断所述的包封树脂,分割各分立半导体器件。
10.按照权利要求9所述的方法,其特征在于,所述安装工序包括将所述多个分立半导体元件的背面电极固定在金属板上,并电连接该金属板与该背部电极。
11.按照权利要求9所述的方法,其特征在于,所述分割工序包括切断合成一体的多个分立半导体元件周围的包封树脂,分割该分立半导体器件,用整体的包封树脂包封每个分立半导体器件的所述多个分立半导体元件。
12.按照权利要求9所述的方法,其特征在于,所述的切断金属板的工序包括切断所述金属板,使得连接到所述多个分立半导体元件的所述的小片连接垫片和/或引线连接垫片成为一个整体,和
所述的分割工序包括切断所述分立半导体元件周围的包封树脂,这些分立半导体元件形成得使连接到所述多个分立半导体元件的所述的小片连接垫片和/或引线连接垫片成为一个整体,由此得到所述的分立半导体器件,其中所述的多个分立半导体元件用整体树脂包封,通常共用所述小片连接垫片和/或引线连接垫片。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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JP277230/1997 | 1997-10-09 | ||
JP27723097A JP3837215B2 (ja) | 1997-10-09 | 1997-10-09 | 個別半導体装置およびその製造方法 |
JP277230/97 | 1997-10-09 |
Publications (2)
Publication Number | Publication Date |
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CN1214544A CN1214544A (zh) | 1999-04-21 |
CN1160781C true CN1160781C (zh) | 2004-08-04 |
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CNB981024785A Expired - Lifetime CN1160781C (zh) | 1997-10-09 | 1998-06-06 | 分立半导体器件及其制造方法 |
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Country | Link |
---|---|
US (1) | US6163069A (zh) |
JP (1) | JP3837215B2 (zh) |
KR (1) | KR100389230B1 (zh) |
CN (1) | CN1160781C (zh) |
TW (1) | TW405235B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109691242A (zh) * | 2016-10-14 | 2019-04-26 | 欧姆龙株式会社 | 电子装置及其制造方法 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000022044A (ja) | 1998-07-02 | 2000-01-21 | Mitsubishi Electric Corp | 半導体装置とその製造方法 |
US6636334B2 (en) * | 1999-03-26 | 2003-10-21 | Oki Electric Industry Co., Ltd. | Semiconductor device having high-density packaging thereof |
JP3501281B2 (ja) * | 1999-11-15 | 2004-03-02 | 沖電気工業株式会社 | 半導体装置 |
JP3827497B2 (ja) | 1999-11-29 | 2006-09-27 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP3778773B2 (ja) * | 2000-05-09 | 2006-05-24 | 三洋電機株式会社 | 板状体および半導体装置の製造方法 |
US6238952B1 (en) * | 2000-02-29 | 2001-05-29 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
TW497371B (en) * | 2000-10-05 | 2002-08-01 | Sanyo Electric Co | Semiconductor device and semiconductor module |
JP3634735B2 (ja) * | 2000-10-05 | 2005-03-30 | 三洋電機株式会社 | 半導体装置および半導体モジュール |
JP4354109B2 (ja) * | 2000-11-15 | 2009-10-28 | Okiセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
JP3628971B2 (ja) * | 2001-02-15 | 2005-03-16 | 松下電器産業株式会社 | リードフレーム及びそれを用いた樹脂封止型半導体装置の製造方法 |
JP4611569B2 (ja) * | 2001-05-30 | 2011-01-12 | ルネサスエレクトロニクス株式会社 | リードフレーム及び半導体装置の製造方法 |
KR100445072B1 (ko) * | 2001-07-19 | 2004-08-21 | 삼성전자주식회사 | 리드 프레임을 이용한 범프 칩 캐리어 패키지 및 그의제조 방법 |
US20070108609A1 (en) * | 2001-07-19 | 2007-05-17 | Samsung Electronics Co., Ltd. | Bumped chip carrier package using lead frame and method for manufacturing the same |
US6737931B2 (en) * | 2002-07-19 | 2004-05-18 | Agilent Technologies, Inc. | Device interconnects and methods of making the same |
CN1326235C (zh) * | 2003-06-03 | 2007-07-11 | 胜开科技股份有限公司 | 封装积体电路基板的制造方法 |
KR100796587B1 (ko) * | 2004-09-02 | 2008-01-21 | 삼성에스디아이 주식회사 | 도너 기판의 제조 방법 및 그를 이용한 유기 전계 발광소자의 제조 방법 |
JP2006222298A (ja) * | 2005-02-10 | 2006-08-24 | Renesas Technology Corp | 半導体装置およびその製造方法 |
WO2007136417A2 (en) * | 2005-11-07 | 2007-11-29 | Exactech, Inc. | Mounting system and method for enhancing implant fixation to bone |
DE102006044690B4 (de) * | 2006-09-22 | 2010-07-29 | Infineon Technologies Ag | Elektronisches Bauteil und Verfahren zum Herstellen |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59208756A (ja) * | 1983-05-12 | 1984-11-27 | Sony Corp | 半導体装置のパツケ−ジの製造方法 |
JPS6225444A (ja) * | 1985-07-26 | 1987-02-03 | Hitachi Ltd | 連続配線基板 |
US5280194A (en) * | 1988-11-21 | 1994-01-18 | Micro Technology Partners | Electrical apparatus with a metallic layer coupled to a lower region of a substrate and metallic layer coupled to a lower region of a semiconductor device |
JPH0691176B2 (ja) * | 1989-12-07 | 1994-11-14 | 株式会社東芝 | 大電力用半導体装置 |
JPH04118678A (ja) * | 1990-09-10 | 1992-04-20 | Seiko Epson Corp | 現像方法 |
JPH04171969A (ja) * | 1990-11-06 | 1992-06-19 | Fujitsu Ltd | 実装icチップ樹脂封止構造及び樹脂封止方法 |
US5172214A (en) * | 1991-02-06 | 1992-12-15 | Motorola, Inc. | Leadless semiconductor device and method for making the same |
US5157480A (en) * | 1991-02-06 | 1992-10-20 | Motorola, Inc. | Semiconductor device having dual electrical contact sites |
US5438305A (en) * | 1991-08-12 | 1995-08-01 | Hitachi, Ltd. | High frequency module including a flexible substrate |
JPH05129473A (ja) * | 1991-11-06 | 1993-05-25 | Sony Corp | 樹脂封止表面実装型半導体装置 |
US5285352A (en) * | 1992-07-15 | 1994-02-08 | Motorola, Inc. | Pad array semiconductor device with thermal conductor and process for making the same |
US5583377A (en) * | 1992-07-15 | 1996-12-10 | Motorola, Inc. | Pad array semiconductor device having a heat sink with die receiving cavity |
US5422615A (en) * | 1992-09-14 | 1995-06-06 | Hitachi, Ltd. | High frequency circuit device |
US5309322A (en) * | 1992-10-13 | 1994-05-03 | Motorola, Inc. | Leadframe strip for semiconductor packages and method |
US5355283A (en) * | 1993-04-14 | 1994-10-11 | Amkor Electronics, Inc. | Ball grid array with via interconnection |
JPH07142627A (ja) * | 1993-11-18 | 1995-06-02 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US5521429A (en) * | 1993-11-25 | 1996-05-28 | Sanyo Electric Co., Ltd. | Surface-mount flat package semiconductor device |
DE4431604A1 (de) * | 1994-09-05 | 1996-03-07 | Siemens Ag | Schaltungsanordnung mit einem Chipkartenmodul und einer damit verbundenen Spule |
DE69524730T2 (de) * | 1994-10-31 | 2002-08-22 | Koninklijke Philips Electronics N.V., Eindhoven | Verfahren zur Herstellung einer Halbleitervorrichtung für Mikrowellen |
US5561322A (en) * | 1994-11-09 | 1996-10-01 | International Business Machines Corporation | Semiconductor chip package with enhanced thermal conductivity |
JPH08316372A (ja) * | 1995-05-16 | 1996-11-29 | Toshiba Corp | 樹脂封止型半導体装置 |
JP3264147B2 (ja) * | 1995-07-18 | 2002-03-11 | 日立電線株式会社 | 半導体装置、半導体装置用インターポーザ及びその製造方法 |
US5696666A (en) * | 1995-10-11 | 1997-12-09 | Motorola, Inc. | Low profile exposed die chip carrier package |
JPH09260568A (ja) * | 1996-03-27 | 1997-10-03 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
KR0185512B1 (ko) * | 1996-08-19 | 1999-03-20 | 김광호 | 칼럼리드구조를갖는패키지및그의제조방법 |
KR100214549B1 (ko) * | 1996-12-30 | 1999-08-02 | 구본준 | 버텀리드 반도체 패키지 |
US5894108A (en) * | 1997-02-11 | 1999-04-13 | National Semiconductor Corporation | Plastic package with exposed die |
US5977630A (en) * | 1997-08-15 | 1999-11-02 | International Rectifier Corp. | Plural semiconductor die housed in common package with split heat sink |
US5942796A (en) * | 1997-11-17 | 1999-08-24 | Advanced Packaging Concepts, Inc. | Package structure for high-power surface-mounted electronic devices |
-
1997
- 1997-10-09 JP JP27723097A patent/JP3837215B2/ja not_active Expired - Lifetime
-
1998
- 1998-05-01 US US09/070,724 patent/US6163069A/en not_active Expired - Lifetime
- 1998-05-27 TW TW087108209A patent/TW405235B/zh not_active IP Right Cessation
- 1998-06-05 KR KR10-1998-0020879A patent/KR100389230B1/ko not_active IP Right Cessation
- 1998-06-06 CN CNB981024785A patent/CN1160781C/zh not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109691242A (zh) * | 2016-10-14 | 2019-04-26 | 欧姆龙株式会社 | 电子装置及其制造方法 |
Also Published As
Publication number | Publication date |
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JP3837215B2 (ja) | 2006-10-25 |
JPH11121644A (ja) | 1999-04-30 |
KR100389230B1 (ko) | 2003-10-22 |
US6163069A (en) | 2000-12-19 |
KR19990036521A (ko) | 1999-05-25 |
CN1214544A (zh) | 1999-04-21 |
TW405235B (en) | 2000-09-11 |
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