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CN111785622B - Annealing process, device and metal contact layer forming method for forming metal silicide - Google Patents

Annealing process, device and metal contact layer forming method for forming metal silicide Download PDF

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CN111785622B
CN111785622B CN202010679523.9A CN202010679523A CN111785622B CN 111785622 B CN111785622 B CN 111785622B CN 202010679523 A CN202010679523 A CN 202010679523A CN 111785622 B CN111785622 B CN 111785622B
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姜兰
归琰
沈耀庭
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
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    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
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    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6219—Fin field-effect transistors [FinFET] characterised by the source or drain electrodes
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers

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Abstract

The invention relates to an annealing process for forming metal silicide, which relates to the semiconductor integrated circuit technology, in the annealing process in the forming process of the metal silicide used as a metal contact layer on a grid electrode, a source electrode and a drain electrode of a semiconductor device, a plurality of heat sources are arranged on at least one side of a wafer, the plurality of heat sources cover the surface of the wafer and the area around the wafer, and a switch unit is arranged for controlling the temperature of each heat source.

Description

形成金属硅化物的退火工艺、装置及金属接触层形成方法Annealing process, device and metal contact layer forming method for forming metal silicide

技术领域technical field

本发明涉及半导体集成电路技术，尤其涉及一种金属硅化物的退火工艺。The present invention relates to semiconductor integrated circuit technology, in particular to an annealing process of metal silicide.

背景技术Background technique

随着半导体技术的不断发展，MOS器件特征尺寸不断地减小，源极漏极之间的距离也越来越短，短沟道效应越来越严重，传统的平面器件(如硅MOSFET)的尺寸持续按比例缩小将变得越来越困难。集成电路技术发展到20nm及以下技术节点时，FinFET(Fin Field-Effect Transistor，鳍式场效应晶体管)应运而生，其是一种立体型器件，相对于平面式晶体管，鳍式场效应晶体管(FinFET)具有立体式沟道结构，具有更好的导通电流和关断电流特性，也能改善短沟道效应(SCE)，并其与传统CMOS工艺兼容，而被广泛应用。With the continuous development of semiconductor technology, the feature size of MOS devices is continuously reduced, the distance between source and drain is getting shorter and shorter, and the short channel effect is becoming more and more serious. Continued scaling down will become increasingly difficult. When integrated circuit technology develops to 20nm and below technology nodes, FinFET (Fin Field-Effect Transistor, fin field effect transistor) emerges as the times require, which is a three-dimensional device. Compared with planar transistors, fin field effect transistors ( FinFET) has a three-dimensional channel structure, has better on-current and off-current characteristics, can also improve the short channel effect (SCE), and is compatible with traditional CMOS processes, and is widely used.

鳍式场效应晶体管通常包括鳍体，鳍体由形成于半导体衬底上的纳米条或纳米片组成。同一半导体衬底上的鳍体平行排列且各鳍体之间隔离有介质层。栅极结构覆盖在部分长度的鳍体的顶部表面和侧面，被栅极结构覆盖的鳍体的表面用于形成沟道，也即在鳍体的顶部表面和两个侧面都具有沟道。通常栅极结构包括叠加而成的栅介质层和栅导电材料层。源区和漏区形成在栅极结构两侧的鳍体中。A fin field effect transistor generally includes a fin body, which consists of nano-stripes or nano-sheets formed on a semiconductor substrate. The fin bodies on the same semiconductor substrate are arranged in parallel, and a dielectric layer is isolated between the fin bodies. The gate structure covers the top surface and the side surfaces of the partial length of the fin body, and the surface of the fin body covered by the gate structure is used to form a channel, that is, the channel is formed on the top surface and both sides of the fin body. Generally, the gate structure includes a gate dielectric layer and a gate conductive material layer which are stacked. Source and drain regions are formed in the fin bodies on both sides of the gate structure.

在鳍式场效应晶体管的金属栅极和源/漏极形成之后，通常在衬底的有源区内形成一层金属层，如金属钛(Ti)，然后进行退火工艺使金属层的金属与衬底(如硅衬底)发生反应生成金属硅化物而形成金属接触层。在14nm及以下技术工艺中，金属硅化物与Si/SiGe衬底之间的接触电阻对器件内阻和寄生外阻的影响越来越大。对于镍作为金属层的，由于金属镍比较活泼，在高温热退火时容易产生在28nm中Ni piping和spiking缺陷。在14nm制程中，金属钛由于其较好的热稳定性而被广泛应用为金属层。栅极以及源/漏极沉积金属钛层工艺和退火工艺共同影响晶圆片内电阻片内均匀度。首先金属钛层沉积时均匀度一般较差；其次目前的退火工艺一般为高温激光退火(Laser Annealing)，其是一种微秒级退火工艺，其利用激光光束快速地在硅片表面进行扫描，从而达到硅片上某一微分区域的快速退火的作用，激光退火使晶圆面内的受热一般比较均匀，由于金属钛层沉积时均匀度一般较差，则形成的金属硅化物的电阻片内均匀度也较差，影响器件性能，继而影响器件良率。After the metal gate and source/drain of the fin field effect transistor are formed, a metal layer, such as metal titanium (Ti), is usually formed in the active area of the substrate, and then an annealing process is performed to make the metal of the metal layer and the metal layer. A substrate (eg, a silicon substrate) reacts to form a metal silicide to form a metal contact layer. In the technology process of 14nm and below, the contact resistance between the metal silicide and the Si/SiGe substrate has an increasing influence on the internal resistance and parasitic external resistance of the device. For nickel as the metal layer, Ni piping and spiking defects at 28nm are easily generated during high temperature thermal annealing due to the active metal nickel. In the 14nm process, titanium metal is widely used as a metal layer due to its better thermal stability. The gate and source/drain deposition metal titanium layer process and annealing process together affect the intra-wafer resistance intra-chip uniformity. Firstly, the uniformity of the metal titanium layer is generally poor during deposition; secondly, the current annealing process is generally high-temperature laser annealing (Laser Annealing), which is a microsecond-level annealing process that uses a laser beam to quickly scan the surface of the silicon wafer. So as to achieve the effect of rapid annealing of a certain differential area on the silicon wafer. Laser annealing makes the heating in the wafer surface generally more uniform. Uniformity is also poor, affecting device performance, which in turn affects device yield.

发明内容SUMMARY OF THE INVENTION

本发明提供的形成金属硅化物的退火工艺，包括：S1：提供一晶圆，晶圆上包括形成的栅极结构及位于栅极结构两侧的源极和漏极，并在栅极结构、源极和漏极上形成有金属层；S2：将晶圆置于一退火装置中，该退火装置包括多个热源和一开关单元，多个热源置于晶圆的至少一侧，并覆盖晶圆的至少一侧的表面及晶圆周侧的区域，开关单元连接每一热源；以及S3：获得晶圆面内形成的金属层的厚度分布数据，根据金属层的厚度分布数据计算每一热源的目标温度，开关单元根据每一热源的目标温度控制每一热源工作在其目标温度以对晶圆进行退火工艺。The annealing process for forming a metal silicide provided by the present invention includes: S1: providing a wafer, the wafer includes a gate structure formed and a source electrode and a drain electrode located on both sides of the gate structure, and the gate structure, A metal layer is formed on the source electrode and the drain electrode; S2: the wafer is placed in an annealing device, the annealing device includes a plurality of heat sources and a switch unit, and the plurality of heat sources are placed on at least one side of the wafer and cover the wafer. On the surface of at least one side of the circle and the area on the peripheral side of the wafer, the switch unit is connected to each heat source; and S3: obtain the thickness distribution data of the metal layer formed in the wafer surface, and calculate the thickness distribution data of each heat source according to the thickness distribution data of the metal layer. The target temperature, the switch unit controls each heat source to work at its target temperature according to the target temperature of each heat source to perform an annealing process on the wafer.

更进一步的，在晶圆的两侧均设置多个热源。Furthermore, multiple heat sources are arranged on both sides of the wafer.

更进一步的，退火装置还包括开关控制装置，开关控制装置包括一输入端和至少一输出端，输入端接收每一热源的目标温度信号，根据每一热源的目标温度信号得到开关单元中每一开关的控制信号，并通过其输出端输出开关控制信号至开关单元中的每一个开关器件，以控制每一开关器件的导通程度，进而控制与该开关器件连接的热源的温度。Further, the annealing device also includes a switch control device, the switch control device includes an input end and at least one output end, the input end receives the target temperature signal of each heat source, and obtains each of the switch units according to the target temperature signal of each heat source. The control signal of the switch is outputted to each switching device in the switching unit through its output terminal to control the degree of conduction of each switching device, thereby controlling the temperature of the heat source connected to the switching device.

更进一步的，所述退火工艺为等温退火工艺、尖峰退火工艺或等温退火工艺和尖峰退火工艺的结合。Further, the annealing process is an isothermal annealing process, a spike annealing process, or a combination of the isothermal annealing process and the spike annealing process.

更进一步的，退火工艺中，热源的目标温度区间为450℃至700℃之间,其升温速率为30℃/s至200℃/s之间；气体流量包括氮气和氦气，氮气和氦气的总流量在15slm至250slm之间；退火工艺中的吹气方式为顶部吹气、边缘吹气或顶部吹气和边缘吹气的结合；退火工艺的退火时间为1s至30s之间；晶圆转速为50r/min至100r/min之间；氧气(O2)含量小于等于10ppm。Furthermore, in the annealing process, the target temperature range of the heat source is between 450°C and 700°C, and the heating rate is between 30°C/s and 200°C/s; the gas flow includes nitrogen and helium, and nitrogen and helium. The total flow rate of the annealing process is between 15slm and 250slm; the blowing method in the annealing process is top blowing, edge blowing or a combination of top blowing and edge blowing; the annealing time of the annealing process is between 1s and 30s; The rotation speed is between 50r/min and 100r/min; the oxygen (O 2 ) content is less than or equal to 10ppm.

本发明提供的形成金属硅化物的退火装置，包括：多个热源，置于晶圆的至少一侧，并覆盖晶圆的至少一侧的表面及晶圆周侧的区域；开关单元，连接每一热源；以及开关控制装置，包括一输入端和至少一输出端，输入端接收每一热源的目标温度信号，开关控制装置根据每一热源的目标温度信号得到开关单元中每一开关的控制信号，并通过其输出端输出开关控制信号至开关单元中的每一个开关器件，以控制每一开关器件的导通程度，进而控制与该开关器件连接的热源的温度，其中每一热源的目标温度信号与晶圆面内与该热源对应的点的金属层的厚度有关。The annealing device for forming metal silicide provided by the present invention includes: a plurality of heat sources, which are placed on at least one side of the wafer and cover the surface of at least one side of the wafer and the area on the peripheral side of the wafer; a switch unit is connected to each a heat source; and a switch control device, comprising an input end and at least one output end, the input end receives the target temperature signal of each heat source, the switch control device obtains the control signal of each switch in the switch unit according to the target temperature signal of each heat source, and output a switch control signal to each switch device in the switch unit through its output terminal to control the degree of conduction of each switch device, and then control the temperature of the heat source connected to the switch device, wherein the target temperature signal of each heat source It is related to the thickness of the metal layer at the point in the wafer plane corresponding to the heat source.

更进一步的，在晶圆的两侧均设置了多个热源。Furthermore, multiple heat sources are arranged on both sides of the wafer.

更进一步的，任一侧的多个热源在晶圆表面和周侧均匀排列。Furthermore, the multiple heat sources on either side are evenly arranged on the wafer surface and the perimeter.

更进一步的，热源为发热灯。Further, the heat source is a heating lamp.

本发明提供的FinFet器件金属接触层形成方法，包括：S1：提供一晶圆，在晶圆上形成多个鳍体，各鳍体平行排列；S2：形成多条多晶硅栅，所述多晶硅栅覆盖鳍体的部分的顶部表面和侧面，所述多晶硅栅覆盖的鳍体的区域用于形成沟道区，源极区域和漏极区域位于多晶硅栅的两侧；S3：在鳍体上形成源极区域和漏极区域，在源极区域和漏极区域上外延形成金属硅化物；S4：去除多晶硅栅，在多晶硅栅的去除区域形成金属栅；S5：离子注入在金属硅化物上形成非晶层以形成源极和漏极；S6：在金属栅、源极和漏极上形成金属层；S7：将晶圆置于一退火装置中，该退火装置包括多个热源和一开关单元，多个热源置于晶圆的至少一侧，并覆盖晶圆的至少一侧的表面及晶圆周侧的区域，开关单元连接每一热源；以及S8：获得晶圆面内形成的金属层的厚度分布数据，根据金属层的厚度分布数据计算每一热源的目标温度，开关单元根据每一热源的目标温度控制每一热源工作在其目标温度以对晶圆进行退火工艺。The method for forming a metal contact layer of a FinFet device provided by the present invention includes: S1: providing a wafer, forming a plurality of fin bodies on the wafer, and each fin body is arranged in parallel; S2: forming a plurality of polysilicon gates, the polysilicon gates cover The top surface and side surface of the part of the fin body, the area of the fin body covered by the polysilicon gate is used to form a channel region, and the source region and the drain region are located on both sides of the polysilicon gate; S3: forming a source electrode on the fin body region and drain region, epitaxially form metal silicide on the source region and drain region; S4: remove the polysilicon gate, form a metal gate in the removed region of the polysilicon gate; S5: ion implantation forms an amorphous layer on the metal silicide to form a source electrode and a drain electrode; S6: forming a metal layer on the metal gate, source electrode and drain electrode; S7: placing the wafer in an annealing device, the annealing device includes a plurality of heat sources and a switching unit, a plurality of The heat source is placed on at least one side of the wafer, and covers the surface of at least one side of the wafer and the area on the peripheral side of the wafer, and the switch unit is connected to each heat source; and S8: Obtain thickness distribution data of the metal layer formed in the wafer surface and calculating the target temperature of each heat source according to the thickness distribution data of the metal layer, and the switch unit controls each heat source to work at its target temperature according to the target temperature of each heat source to anneal the wafer.

更进一步的，金属层为钛金属层或钴金属层。Further, the metal layer is a titanium metal layer or a cobalt metal layer.

更进一步的，在S3中外延形成的金属硅化物为硅锗或硅磷的金属硅化物。Furthermore, the metal silicide epitaxially formed in S3 is a metal silicide of silicon germanium or silicon phosphorus.

更进一步的，在晶圆的两侧均设置多个热源。Furthermore, multiple heat sources are arranged on both sides of the wafer.

更进一步的，退火装置还包括开关控制装置，开关控制装置包括一输入端和至少一输出端，输入端接收每一热源的目标温度信号，根据每一热源的目标温度信号得到开关单元中每一开关的控制信号，并通过其输出端输出开关控制信号至开关单元中的每一个开关器件，以控制每一开关器件的导通程度，进而控制与该开关器件连接的热源的温度。Further, the annealing device also includes a switch control device, the switch control device includes an input end and at least one output end, the input end receives the target temperature signal of each heat source, and obtains each of the switch units according to the target temperature signal of each heat source. The control signal of the switch is outputted to each switching device in the switching unit through its output terminal to control the degree of conduction of each switching device, thereby controlling the temperature of the heat source connected to the switching device.

更进一步的，所述退火工艺为等温退火工艺、尖峰退火工艺或等温退火工艺和尖峰退火工艺的结合。Further, the annealing process is an isothermal annealing process, a spike annealing process, or a combination of the isothermal annealing process and the spike annealing process.

更进一步的，退火工艺中，热源的目标温度区间为450℃至700℃之间,其升温速率为30℃/s至200℃/s之间；气体流量包括氮气和氦气，氮气和氦气的总流量在15slm至250slm之间；退火工艺中的吹气方式为顶部吹气、边缘吹气或顶部吹气和边缘吹气的结合；退火工艺的退火时间为1s至30s之间；晶圆转速为50r/min至100r/min之间；氧气(O2)含量小于等于10ppm。Furthermore, in the annealing process, the target temperature range of the heat source is between 450°C and 700°C, and the heating rate is between 30°C/s and 200°C/s; the gas flow includes nitrogen and helium, and nitrogen and helium. The total flow rate of the annealing process is between 15slm and 250slm; the blowing method in the annealing process is top blowing, edge blowing or a combination of top blowing and edge blowing; the annealing time of the annealing process is between 1s and 30s; The rotation speed is between 50r/min and 100r/min; the oxygen (O 2 ) content is less than or equal to 10ppm.

在作为半导体器件的栅极、源极和漏极上的金属接触层的金属硅化物的形成过程中的退火工艺中，在晶圆的至少一侧设置多个热源，多个热源覆盖晶圆表面及晶圆周侧的区域，并设置开关单元，用于控制每个热源的温度，首先获得晶圆面内形成的金属层的厚度分布数据，然后根据金属层的厚度分布数据计算每一热源的目标温度，并使开关单元控制每一热源工作在其目标温度以对晶圆进行退火工艺，而使形成的金属硅化物的厚度在晶圆面内及电阻片内均匀度好，而提高接触电阻的均匀度，进而提高器件性能，继而提高器件良率。During the annealing process during the formation of the metal silicide as the metal contact layer on the gate, source and drain of the semiconductor device, a plurality of heat sources are provided on at least one side of the wafer, and the plurality of heat sources cover the surface of the wafer and the area on the peripheral side of the wafer, and set a switch unit to control the temperature of each heat source, first obtain the thickness distribution data of the metal layer formed in the wafer surface, and then calculate the target of each heat source according to the thickness distribution data of the metal layer temperature, and make the switch unit control each heat source to work at its target temperature to anneal the wafer, so that the thickness of the formed metal silicide has a good uniformity in the wafer surface and the resistor sheet, and improves the contact resistance. uniformity, thereby improving device performance and thus improving device yield.

附图说明Description of drawings

图1为本发明一实施例的晶圆上半导体器件的局部结构示意图。FIG. 1 is a schematic diagram of a partial structure of a semiconductor device on a wafer according to an embodiment of the present invention.

图2为本发明一实施例的在晶圆上形成金属硅化物而进行退火工艺的装置的侧视示意图。2 is a schematic side view of an apparatus for forming metal silicide on a wafer and performing an annealing process according to an embodiment of the present invention.

图中主要组件附图标记说明如下：The main components in the figure are described with reference numerals as follows:

200、退火装置；100、晶圆；210、220、开关单元；230、开关控制装置。200, an annealing device; 100, a wafer; 210, 220, a switch unit; 230, a switch control device.

具体实施方式Detailed ways

下面将结合附图，对本发明中的技术方案进行清楚、完整的描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在不做出创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

本发明一实施例中，在于提供一种形成金属硅化物的退火工艺，包括：S1：提供一晶圆，晶圆上包括形成的栅极结构及位于栅极结构两侧的源极和漏极，并在栅极结构、源极和漏极上形成有金属层；S2：将晶圆置于一退火装置中，该退火装置包括多个热源和一开关单元，多个热源置于晶圆的至少一侧，并覆盖晶圆的至少一侧的表面及晶圆周侧的区域，开关单元连接每一热源；S3：获得晶圆面内形成的金属层的厚度分布数据，根据金属层的厚度分布数据计算每一热源的目标温度，开关单元根据每一热源的目标温度控制每一热源工作在其目标温度以对晶圆进行退火工艺。In an embodiment of the present invention, an annealing process for forming metal silicide is provided, including: S1: providing a wafer, the wafer includes a gate structure formed on the wafer, and a source electrode and a drain electrode located on both sides of the gate structure. , and a metal layer is formed on the gate structure, the source electrode and the drain electrode; S2: the wafer is placed in an annealing device, the annealing device includes a plurality of heat sources and a switch unit, and the plurality of heat sources are placed on the wafer At least one side, and covers at least one surface of the wafer and the area on the peripheral side of the wafer, and the switch unit is connected to each heat source; S3: Obtain the thickness distribution data of the metal layer formed in the wafer surface, according to the thickness distribution of the metal layer The data calculates the target temperature of each heat source, and the switch unit controls each heat source to work at its target temperature according to the target temperature of each heat source to perform an annealing process on the wafer.

请参阅图1和图2，图1为本发明一实施例的晶圆上半导体器件的局部结构示意图，图2为本发明一实施例的在晶圆上形成金属硅化物而进行退火工艺的装置的侧视示意图。具体的，在S1中，如图1所示，提供一晶圆100，晶圆100上包括形成的栅极结构110及位于栅极结构110两侧的源极121和漏极122，并在栅极结构110、源极121和漏极122上形成有金属层(图中未示出)，在一实施例中，金属层的厚度在30埃米至150埃米之间，在一实施例中，还在金属层上形成一层保护层，保护层的厚度在40埃米至100埃米之间，如金属层是钛，其保护层可为氮化钛；在S2中，如图2所示，将晶圆100置于一退火装置200中，退火装置200包括多个热源，如图2所示的沿晶圆100表面设置的编号为1-56的56个热源，如图2所示的实施例中在晶圆100的两侧均设置了多个热源，但本发明不限于两侧均设置多个热源，只其中一侧设置多个热源亦可，也即在晶圆100的至少一侧设置多个热源；并如图2所示，晶圆任一侧的多个热源覆盖晶圆表面及晶圆周侧的区域，也即任一侧的多个热源不仅覆盖晶圆表面，还延伸到晶圆之外的区域，即覆盖晶圆周侧的区域。如图2所示，以晶圆上侧为例，编号为8-20的13个热源覆盖了晶圆的上表面，编号1-7的7个热源覆盖晶圆上表面左侧的周侧的区域，编号21-26的6个热源覆盖晶圆上表面右侧的周侧的区域，且编号1-26的26个热源从左至右依次排列，晶圆下侧的编号35-48的14个热源覆盖了晶圆的下表面，编号29-34的6个热源覆盖晶圆下表面左侧的周侧的区域，编号49-54的6个热源覆盖晶圆下表面右侧的周侧的区域，且编号29-54的26个热源从左至右依次排列。在一实施例中，置于晶圆上侧的多个热源与置于晶圆下侧的多个热源一一对称设置。在一实施例中，置于晶圆上侧的多个热源与置于晶圆下侧的多个热源一一交错设置，如置于晶圆下侧的29号热源位于置于晶圆上侧的1号和2号热源之间，置于晶圆上侧的2号热源位于置于晶圆下侧的29号和30号热源之间，也即一一交错设置。如图2所示，退火装置200还包括开关单元，以晶圆上侧为例，开关单元210连接位于晶圆100上侧的1-26号热源，具体的开关单元210包括1-13号开关器件，1号开关器件连接13和14号热源，2号开关器件连接12和15号热源，依次类推，13号开关器件连接1和26号热源；对于晶圆下侧，开关单元220连接位于晶圆100下侧的29-54号热源，具体的开关单元220包括15-27号开关器件，15号开关器件连接41和42号热源，16号开关器件连接40和43热源，依次类推，27号开关器件连接29和54号热源，如此，开关单元连接每一热源。在本发明一实施例中，任一侧的多个热源在晶圆表面和周侧均匀排列。在本发明一实施例中，热源为发热灯，如灯管或灯泡；S3：获得晶圆面内形成的金属层的厚度分布数据，根据金属层的厚度分布数据计算每一热源的目标温度，开关单元根据每一热源的目标温度控制每一热源工作在其目标温度以对晶圆进行退火工艺，由于一般形成的金属层的厚度的均匀度较差，为使后续形成的金属硅化物的厚度一致，若获得晶圆某一处的金属层的厚度较厚，则可设置其附件的热源的温度较高，以使该点以较高的温度进行退火工艺，而若获得晶圆某一处的金属层的厚度较薄，则可设置其附近的热源的温度较低，以使该点以较低的温度进行退火工艺，如此实现晶圆上各点的退火温度的单独控制，而使晶圆面内通过退火工艺形成厚度均匀度高的金属硅化物层，以弥补之前金属层形成工艺形成的金属层厚度均匀度差的问题，而使形成的金属硅化物(如图1中标号140所示)的厚度在晶圆面内及电阻片内均匀度好，而提高接触电阻的均匀度，进而提高器件性能，继而提高器件良率。更具体的，在一实施例中，退火装置还包括开关控制装置230，开关控制装置230包括一输入端和至少一输出端，输入端接收每一热源的目标温度信号，根据每一热源的目标温度信号得到开关单元210和220中每一开关的控制信号，并通过其输出端输出开关控制信号至开关单元210和220中的每一个开关器件，以控制每一开关器件的导通程度，进而控制与该开关器件连接的热源的温度。在一实施例中，开关单元中每一开关器件为IGBT，本发明对开关器件的类型不限定，只要其能根据开关信号控制其导通程度即可。Please refer to FIGS. 1 and 2. FIG. 1 is a schematic diagram of a partial structure of a semiconductor device on a wafer according to an embodiment of the present invention, and FIG. 2 is an apparatus for forming metal silicide on a wafer and performing an annealing process according to an embodiment of the present invention. Schematic side view. Specifically, in S1 , as shown in FIG. 1 , a wafer 100 is provided. The wafer 100 includes a gate structure 110 formed on the wafer 100 and a source electrode 121 and a drain electrode 122 located on both sides of the gate structure 110 . A metal layer (not shown in the figure) is formed on the electrode structure 110, the source electrode 121 and the drain electrode 122. In one embodiment, the thickness of the metal layer is between 30 angstroms and 150 angstroms. In one embodiment , and a protective layer is formed on the metal layer, and the thickness of the protective layer is between 40 angstroms and 100 angstroms. If the metal layer is titanium, the protective layer can be titanium nitride; in S2, as shown in Figure 2 As shown, the wafer 100 is placed in an annealing apparatus 200. The annealing apparatus 200 includes a plurality of heat sources, such as 56 heat sources numbered 1-56 arranged along the surface of the wafer 100 as shown in FIG. 2, as shown in FIG. 2 In the embodiment of the present invention, a plurality of heat sources are arranged on both sides of the wafer 100, but the present invention is not limited to having a plurality of heat sources arranged on both sides, and only one side of the wafer 100 can be arranged with a plurality of heat sources, that is, at least one side of the wafer 100 is arranged with a plurality of heat sources. Multiple heat sources are arranged on one side; and as shown in Figure 2, multiple heat sources on either side of the wafer cover the wafer surface and the area on the peripheral side of the wafer, that is, multiple heat sources on either side not only cover the wafer surface, but also The area that extends beyond the wafer, that is, the area that covers the peripheral side of the wafer. As shown in Figure 2, taking the upper side of the wafer as an example, 13 heat sources numbered 8-20 cover the upper surface of the wafer, and 7 heat sources numbered 1-7 cover the peripheral side on the left side of the upper surface of the wafer. Area, the 6 heat sources numbered 21-26 cover the area on the right peripheral side of the upper surface of the wafer, and the 26 heat sources numbered 1-26 are arranged in order from left to right, and the 14 heat sources numbered 35-48 on the lower side of the wafer 1 heat source covers the lower surface of the wafer, 6 heat sources numbered 29-34 cover the area on the left side of the lower surface of the wafer, and 6 heat sources numbered 49-54 cover the area on the right side of the lower surface of the wafer. area, and the 26 heat sources numbered 29-54 are arranged in order from left to right. In one embodiment, the plurality of heat sources placed on the upper side of the wafer and the plurality of heat sources placed on the lower side of the wafer are arranged symmetrically one-to-one. In one embodiment, the plurality of heat sources placed on the upper side of the wafer and the plurality of heat sources placed on the lower side of the wafer are staggered one by one. For example, the No. 29 heat source placed on the lower side of the wafer is placed on the upper side of the wafer. Between the No. 1 and No. 2 heat sources, the No. 2 heat source placed on the upper side of the wafer is located between the No. 29 and No. 30 heat sources placed on the lower side of the wafer, that is, staggered one by one. As shown in FIG. 2 , the annealing apparatus 200 further includes a switch unit. Taking the upper side of the wafer as an example, the switch unit 210 is connected to the No. 1-26 heat sources located on the upper side of the wafer 100 , and the specific switch unit 210 includes No. 1-13 switches. device, the No. 1 switching device is connected to the heat sources 13 and 14, the switching device No. 2 is connected to the heat sources 12 and 15, and so on, the switching device No. 13 is connected to the heat sources 1 and 26; for the lower side of the wafer, the switch unit 220 is connected to the No. 29-54 heat sources on the lower side of the circle 100, the specific switch unit 220 includes No. 15-27 switching devices, No. 15 switching device is connected to No. 41 and No. 42 heat sources, No. 16 switching device is connected to No. 40 and 43 heat sources, and so on, No. 27 The switching device connects heat sources 29 and 54, so that the switching unit connects to each heat source. In an embodiment of the present invention, the plurality of heat sources on either side are evenly arranged on the wafer surface and the peripheral side. In an embodiment of the present invention, the heat source is a heating lamp, such as a lamp tube or a light bulb; S3: Obtain the thickness distribution data of the metal layer formed in the wafer surface, and calculate the target temperature of each heat source according to the thickness distribution data of the metal layer, The switch unit controls each heat source to work at its target temperature according to the target temperature of each heat source to perform an annealing process on the wafer. Since the thickness of the generally formed metal layer is poor in uniformity, in order to make the thickness of the metal silicide formed subsequently Consistently, if the thickness of the metal layer in a certain part of the wafer is thicker, the temperature of the heat source of its attachment can be set higher, so that the annealing process is performed at a higher temperature at this point, and if a certain part of the wafer is obtained If the thickness of the metal layer is thinner, the temperature of the heat source nearby can be set lower, so that the annealing process is performed at a lower temperature at this point, so that the annealing temperature of each point on the wafer can be individually controlled, and the crystal In the circular plane, a metal silicide layer with high thickness uniformity is formed by an annealing process to make up for the problem of poor thickness uniformity of the metal layer formed by the previous metal layer forming process, and the formed metal silicide (as shown by the reference number 140 in FIG. 1 ) The thickness of the shown) has good uniformity in the wafer surface and in the resistor sheet, which improves the uniformity of the contact resistance, thereby improving the device performance, and then improving the device yield. More specifically, in one embodiment, the annealing device further includes a switch control device 230, the switch control device 230 includes an input terminal and at least one output terminal, and the input terminal receives the target temperature signal of each heat source, according to the target temperature of each heat source. The temperature signal obtains the control signal of each switch in the switch units 210 and 220, and outputs the switch control signal to each switch device in the switch units 210 and 220 through its output terminal, so as to control the degree of conduction of each switch device, and then Controls the temperature of the heat source connected to the switching device. In one embodiment, each switching device in the switching unit is an IGBT. The present invention does not limit the type of the switching device, as long as it can control its degree of conduction according to the switching signal.

在一实施例中，在晶圆上侧还设置有27号和28号热源，其由14号开关器件控制，27号和28号热源设置在与1-26号热源的排列方向垂直的方向上的晶圆的两侧。同样的，在一实施例中，也可在晶圆上侧还设置有55号和56号热源，其由28号开关器件控制，55号和56号热源设置在与29-54号热源的排列方向垂直的方向上的晶圆的两侧。In one embodiment, the upper side of the wafer is also provided with No. 27 and No. 28 heat sources, which are controlled by No. 14 switching devices, and the No. 27 and No. 28 heat sources are arranged in a direction perpendicular to the arrangement direction of No. 1-26 heat sources. both sides of the wafer. Similarly, in one embodiment, heat sources No. 55 and No. 56 may also be provided on the upper side of the wafer, which are controlled by the switching device No. 28, and the heat sources No. 55 and No. 56 are arranged in an arrangement with the heat sources No. 29-54. The directions are perpendicular to the sides of the wafer.

在一实施例中，较佳的，所述退火工艺采用双面加热的退火工艺，也即在晶圆的两侧均设置多个热源，如此可进一步提高接触电阻的均匀度。In one embodiment, preferably, the annealing process adopts a double-sided heating annealing process, that is, multiple heat sources are arranged on both sides of the wafer, so that the uniformity of the contact resistance can be further improved.

在一实施例中，所述退火工艺为等温退火工艺、尖峰退火工艺或等温退火工艺和尖峰退火工艺的结合。在一实施例中，退火工艺中，热源的目标温度区间为450℃至700℃之间,其升温速率为30℃/s至200℃/s之间。在一实施例中，退火工艺中，气体流量包括氮气和氦气，氮气和氦气的总流量在15slm至250slm之间。在一实施例中，退火工艺中的吹气方式为顶部吹气、边缘吹气或顶部吹气和边缘吹气的结合。在一实施例中，退火工艺的退火时间为1s至30s之间。在一实施例中，退火工艺中，晶圆转速为50r/min至100r/min之间，在一实施例中，退火工艺中，氧气(O2)含量小于等于10ppm。In one embodiment, the annealing process is an isothermal annealing process, a spike annealing process, or a combination of the isothermal annealing process and the spike annealing process. In one embodiment, in the annealing process, the target temperature range of the heat source is between 450°C and 700°C, and the heating rate thereof is between 30°C/s and 200°C/s. In one embodiment, in the annealing process, the gas flow includes nitrogen and helium, and the total flow of nitrogen and helium is between 15 slm and 250 slm. In one embodiment, the blowing method in the annealing process is top blowing, edge blowing, or a combination of top blowing and edge blowing. In one embodiment, the annealing time of the annealing process is between 1 s and 30 s. In one embodiment, in the annealing process, the wafer rotation speed is between 50 r/min and 100 r/min. In one embodiment, in the annealing process, the oxygen (O 2 ) content is less than or equal to 10 ppm.

在一实施例中，金属层为钛(Ti)金属层或钴(Co)金属层，对应的形成的金属硅化物为富金属相钛化硅(TiSix)或富金属相钴化硅(CoSix)。In one embodiment, the metal layer is a titanium (Ti) metal layer or a cobalt (Co) metal layer, and the corresponding formed metal silicide is a metal-rich phase titanium silicon (TiSix) or a metal-rich phase cobalt silicon (CoSix) .

请参阅图2，本发明还提供一种形成金属硅化物的退火装置，包括：多个热源，置于晶圆100的至少一侧，并覆盖晶圆的至少一侧的表面及晶圆周侧的区域；开关单元(如210或220)，连接每一热源；开关控制装置230，包括一输入端和至少一输出端，输入端接收每一热源的目标温度信号，开关控制装置230根据每一热源的目标温度信号得到开关单元(如210或220)中每一开关的控制信号，并通过其输出端输出开关控制信号至开关单元(如210或220)中的每一个开关器件，以控制每一开关器件的导通程度，进而控制与该开关器件连接的热源的温度，其中每一热源的目标温度信号与晶圆面内与该热源对应的点的金属层的厚度有关。而使开关单元(如210或220)控制每一热源工作在其目标温度以对晶圆进行退火工艺。Referring to FIG. 2 , the present invention also provides an annealing apparatus for forming metal silicide, comprising: a plurality of heat sources placed on at least one side of the wafer 100 and covering the surface of at least one side of the wafer and the peripheral side of the wafer area; switch unit (such as 210 or 220), connected to each heat source; switch control device 230, including an input end and at least one output end, the input end receives the target temperature signal of each heat source, the switch control device 230 according to each heat source The target temperature signal of the switch unit (such as 210 or 220) obtains the control signal of each switch in the switch unit, and outputs the switch control signal to each switch device in the switch unit (such as 210 or 220) through its output terminal to control each The degree of conduction of the switch device controls the temperature of the heat source connected to the switch device, wherein the target temperature signal of each heat source is related to the thickness of the metal layer at the point corresponding to the heat source in the wafer surface. The switch unit (eg, 210 or 220 ) controls each heat source to operate at its target temperature to anneal the wafer.

如图2所示的退火装置200，包括多个热源，如编号为1-56的56个热源。如图2所示的实施例中在晶圆100的两侧均设置了多个热源，但本发明不限于两侧均设置多个热源，只其中一侧设置多个热源亦可，也即在晶圆100的至少一侧设置多个热源；并如图2所示，晶圆任一侧的多个热源覆盖晶圆表面及晶圆周侧的区域，也即任一侧的多个热源不仅覆盖晶圆表面，还延伸到晶圆之外的区域，即覆盖晶圆周侧的区域。如图2所示，以晶圆上侧为例，编号为8-20的13个热源覆盖了晶圆的上表面，编号1-7的7个热源覆盖晶圆上表面左侧的周侧的区域，编号21-26的6个热源覆盖晶圆上表面右侧的周侧的区域，且编号1-26的26个热源从左至右依次排列，晶圆下侧的编号35-48的14个热源覆盖了晶圆的下表面，编号29-34的6个热源覆盖晶圆下表面左侧的周侧的区域，编号49-54的6个热源覆盖晶圆下表面右侧的周侧的区域，且编号29-54的26个热源从左至右依次排列。在一实施例中，置于晶圆上侧的多个热源与置于晶圆下侧的多个热源一一对称设置。在一实施例中，置于晶圆上侧的多个热源与置于晶圆下侧的多个热源一一交错设置，如置于晶圆下侧的29号热源位于置于晶圆上侧的1号和2号热源之间，置于晶圆上侧的2号热源位于置于晶圆下侧的29号和30号热源之间，也即一一交错设置。更具体的，如图2所示，对于晶圆上侧，开关单元210连接位于晶圆100上侧的1-26号热源，具体的开关单元210包括1-13号开关器件，1号开关器件连接13和14号热源，2号开关器件连接12和15号热源，依次类推，13号开关器件连接1和26号热源；对于晶圆下侧，开关单元220连接位于晶圆100下侧的29-54号热源，具体的开关单元210包括15-27号开关器件，15号开关器件连接41和42号热源，16号开关器件连接40和43热源，依次类推，27号开关器件连接29和54号热源，如此，开关单元连接每一热源。在本发明一实施例中，任一侧的多个热源在晶圆表面和周侧均匀排列。在本发明一实施例中，热源为发热灯，如灯管或灯泡。在工作过程中，首先，如图1所示，在晶圆100上的栅极结构110及位于栅极结构110两侧的源极121和漏极122上形成有金属层(图中未示出)，然后获得晶圆面内形成的金属层的厚度分布数据，根据金属层的厚度分布数据计算每一热源的目标温度，即每一热源的目标温度信号与晶圆面内与该热源对应的点的金属层的厚度有关，开关单元根据每一热源的目标温度控制每一热源工作在其目标温度以对晶圆进行退火工艺，由于一般形成的金属层的厚度的均匀度较差，为使后续形成的金属硅化物的厚度一致，若获得晶圆某一处的金属层的厚度较厚，则可设置其附件的热源的温度较高(如开关控制装置控制热源对应的开关器件的驱动电流较大，以使其较充分的导通，而使热源的温度较高)，以使该点以较高的温度进行退火工艺，而若获得晶圆某一处的金属层的厚度较薄，则可设置其附近的热源的温度较低(如开关控制装置控制热源对应的开关器件的驱动电流较小，而使热源的温度较低)，以使该点以较低的温度进行退火工艺，如此实现晶圆上各点的退火温度的单独控制，而使晶圆面内通过退火工艺形成厚度均匀度高的金属硅化物层，以弥补之前金属层形成工艺形成的金属层厚度均匀度差的问题，而使形成的金属硅化物(如图1中标号140所示)的厚度在晶圆面内及电阻片内均匀度好，而提高接触电阻的均匀度，进而提高器件性能，继而提高器件良率。The annealing apparatus 200 shown in FIG. 2 includes a plurality of heat sources, such as 56 heat sources numbered 1-56. In the embodiment shown in FIG. 2 , a plurality of heat sources are arranged on both sides of the wafer 100 , but the present invention is not limited to having a plurality of heat sources arranged on both sides, and only one side can be arranged with a plurality of heat sources. At least one side of the wafer 100 is provided with a plurality of heat sources; and as shown in FIG. 2 , the plurality of heat sources on either side of the wafer cover the area of the wafer surface and the peripheral side of the wafer, that is, the plurality of heat sources on either side not only cover The surface of the wafer also extends to the area outside the wafer, that is, the area covering the peripheral side of the wafer. As shown in Figure 2, taking the upper side of the wafer as an example, 13 heat sources numbered 8-20 cover the upper surface of the wafer, and 7 heat sources numbered 1-7 cover the peripheral side on the left side of the upper surface of the wafer. Area, the 6 heat sources numbered 21-26 cover the area on the right peripheral side of the upper surface of the wafer, and the 26 heat sources numbered 1-26 are arranged in order from left to right, and the 14 heat sources numbered 35-48 on the lower side of the wafer 1 heat source covers the lower surface of the wafer, 6 heat sources numbered 29-34 cover the area on the left side of the lower surface of the wafer, and 6 heat sources numbered 49-54 cover the area on the right side of the lower surface of the wafer. area, and the 26 heat sources numbered 29-54 are arranged in order from left to right. In one embodiment, the plurality of heat sources placed on the upper side of the wafer and the plurality of heat sources placed on the lower side of the wafer are arranged symmetrically one-to-one. In one embodiment, the plurality of heat sources placed on the upper side of the wafer and the plurality of heat sources placed on the lower side of the wafer are staggered one by one. For example, the No. 29 heat source placed on the lower side of the wafer is placed on the upper side of the wafer. Between the No. 1 and No. 2 heat sources, the No. 2 heat source placed on the upper side of the wafer is located between the No. 29 and No. 30 heat sources placed on the lower side of the wafer, that is, staggered one by one. More specifically, as shown in FIG. 2 , for the upper side of the wafer, the switch unit 210 is connected to the No. 1-26 heat sources located on the upper side of the wafer 100 , and the specific switch unit 210 includes No. 1-13 switch devices, No. 1 switch device. No. 13 and No. 14 heat sources are connected, No. 2 switch device is connected to No. 12 and No. 15 heat sources, and so on, No. 13 switch device is connected to No. 1 and No. 26 heat sources; for the lower side of the wafer, the switch unit 220 is connected to the 29th heat source located on the underside of the wafer 100 - No. 54 heat source, the specific switch unit 210 includes No. 15-27 switching devices, No. 15 switching device is connected to No. 41 and No. 42 heat sources, No. 16 switching device is connected to No. 40 and 43 heat sources, and so on, No. 27 switching device is connected to No. 29 and 54 Number of heat sources, so that the switch unit is connected to each heat source. In an embodiment of the present invention, the plurality of heat sources on either side are evenly arranged on the wafer surface and the peripheral side. In an embodiment of the present invention, the heat source is a heat-generating lamp, such as a lamp tube or a light bulb. In the working process, first, as shown in FIG. 1 , a metal layer (not shown in the figure) is formed on the gate structure 110 on the wafer 100 and the source electrode 121 and the drain electrode 122 located on both sides of the gate structure 110 ), then obtain the thickness distribution data of the metal layer formed in the wafer surface, and calculate the target temperature of each heat source according to the thickness distribution data of the metal layer, that is, the target temperature signal of each heat source and the corresponding heat source in the wafer surface The thickness of the metal layer is related to the point, and the switch unit controls each heat source to work at its target temperature according to the target temperature of each heat source to perform the annealing process on the wafer. Since the thickness of the generally formed metal layer is poor, in order to make The thickness of the subsequently formed metal silicide is the same. If the thickness of the metal layer obtained at a certain part of the wafer is thicker, the temperature of the heat source attached to it can be set to be higher (for example, the switch control device controls the drive current of the switch device corresponding to the heat source). is larger to make it more fully conductive and the temperature of the heat source is higher), so that the annealing process is performed at a higher temperature at this point, and if the thickness of the metal layer at a certain part of the wafer is thinner, Then the temperature of the heat source nearby can be set to be lower (for example, the switch control device controls the drive current of the switch device corresponding to the heat source to be lower, so that the temperature of the heat source is lower), so that the annealing process is performed at a lower temperature at this point, In this way, the annealing temperature of each point on the wafer is individually controlled, and the metal silicide layer with high thickness uniformity is formed in the wafer surface through the annealing process to make up for the poor thickness uniformity of the metal layer formed by the previous metal layer forming process. Therefore, the thickness of the formed metal silicide (as shown by the reference numeral 140 in FIG. 1 ) has a good uniformity in the wafer plane and in the resistor sheet, thereby improving the uniformity of the contact resistance, thereby improving the performance of the device, and then improving the device. Yield.

在一实施例中，开关单元中每一开关器件为IGBT，本发明对开关器件的类型不限定，只要其能根据开关信号控制其导通程度即可。In one embodiment, each switching device in the switching unit is an IGBT. The present invention does not limit the type of the switching device, as long as it can control its degree of conduction according to the switching signal.

在一实施例中，在晶圆上侧还设置有27号和28号热源，其由14号开关器件控制，27号和28号热源设置在与1-26号热源的排列方向垂直的方向上的晶圆的两侧。同样的，在一实施例中，也可在晶圆上侧还设置有55号和56号热源，其由28号开关器件控制，55号和56号热源设置在与29-54号热源的排列方向垂直的方向上的晶圆的两侧。In one embodiment, the upper side of the wafer is also provided with No. 27 and No. 28 heat sources, which are controlled by No. 14 switching devices, and the No. 27 and No. 28 heat sources are arranged in a direction perpendicular to the arrangement direction of No. 1-26 heat sources. both sides of the wafer. Similarly, in one embodiment, heat sources No. 55 and No. 56 may also be provided on the upper side of the wafer, which are controlled by the switching device No. 28, and the heat sources No. 55 and No. 56 are arranged in an arrangement with the heat sources No. 29-54. The directions are perpendicular to the sides of the wafer.

在一实施例中，较佳的，所述退火工艺采用双面加热的退火工艺，也即在晶圆的两侧均设置多个热源，如此可进一步提高接触电阻的均匀度。In one embodiment, preferably, the annealing process adopts a double-sided heating annealing process, that is, multiple heat sources are arranged on both sides of the wafer, so that the uniformity of the contact resistance can be further improved.

在一实施例中，较佳的，所述退火工艺采用双面加热的退火工艺，也即在晶圆的两侧均设置多个热源，其工作原理和设置方式与上述其中一侧的热源相似，如此可进一步提高接触电阻的均匀度。In one embodiment, preferably, the annealing process adopts a double-sided heating annealing process, that is, multiple heat sources are arranged on both sides of the wafer, and the working principle and setting method are similar to the above-mentioned heat sources on one side. , which can further improve the uniformity of contact resistance.

在一实施例中，热源的目标温度区间为450℃至700℃之间,其升温速率为30℃/s至200℃/s之间。In one embodiment, the target temperature range of the heat source is between 450°C and 700°C, and the heating rate thereof is between 30°C/s and 200°C/s.

本发明还提供一种FinFet器件金属接触层形成方法，包括：S1：提供一晶圆，在晶圆上形成多个鳍体，各鳍体平行排列；S2：形成多条多晶硅栅，所述多晶硅栅覆盖鳍体的部分的顶部表面和侧面，所述多晶硅栅覆盖的鳍体的区域用于形成沟道区，源极区域和漏极区域位于多晶硅栅的两侧；S3：在鳍体上形成源极区域和漏极区域，在源极区域和漏极区域上外延形成金属硅化物；S4：去除多晶硅栅，在多晶硅栅的去除区域形成金属栅；S5：离子注入在金属硅化物上形成非晶层以形成源极和漏极；S5：去除多晶硅栅，在多晶硅栅的去除区域形成金属栅；S6：在金属栅、源极和漏极上形成金属层；S7：将晶圆置于一退火装置中，该退火装置包括多个热源和一开关单元，多个热源置于晶圆的至少一侧，并覆盖晶圆的至少一侧的表面及晶圆周侧的区域，开关单元连接每一热源；以及S8：获得晶圆面内形成的金属层的厚度分布数据，根据金属层的厚度分布数据计算每一热源的目标温度，开关单元根据每一热源的目标温度控制每一热源工作在其目标温度以对晶圆进行退火工艺。The present invention also provides a method for forming a metal contact layer of a FinFet device, including: S1: providing a wafer, forming a plurality of fin bodies on the wafer, and each fin body is arranged in parallel; S2: forming a plurality of polysilicon gates, the polysilicon The gate covers the top surface and the side surface of the part of the fin body, the area of the fin body covered by the polysilicon gate is used to form a channel region, and the source region and the drain region are located on both sides of the polysilicon gate; S3: formed on the fin body Source region and drain region, epitaxially form metal silicide on the source region and drain region; S4: remove the polysilicon gate, and form a metal gate in the removed region of the polysilicon gate; S5: ion implantation forms a non-metal silicide on the metal silicide. S5: remove the polysilicon gate and form a metal gate in the removed area of the polysilicon gate; S6: form a metal layer on the metal gate, source and drain; S7: place the wafer on a In the annealing device, the annealing device includes a plurality of heat sources and a switch unit, the plurality of heat sources are placed on at least one side of the wafer, and cover the surface of at least one side of the wafer and the area on the peripheral side of the wafer, and the switch unit is connected to each heat source; and S8: obtaining thickness distribution data of the metal layer formed in the wafer surface, calculating a target temperature of each heat source according to the thickness distribution data of the metal layer, and the switch unit controls each heat source to work at its target temperature according to the target temperature of each heat source Target temperature to anneal the wafer.

请参阅图1和图2。具体的，经过S1至S6，如图1所示，在晶圆100上包括形成的栅极结构110及位于栅极结构110两侧的源极121和漏极122，并在栅极结构110、源极121和漏极122上形成有金属层(图中未示出)，在一实施例中，金属层的厚度在30埃米至150埃米之间，在一实施例中，还在金属层上形成一层保护层，保护层的厚度在40埃米至100埃米之间，如金属层是钛，其保护层可为氮化钛；在S7中，如图2所示，将晶圆100置于一退火装置200中，退火装置200包括多个热源，如图2所示的沿晶圆100表面设置的编号为1-56的56个热源，如图2所示的实施例中在晶圆100的两侧均设置了多个热源，但本发明不限于两侧均设置多个热源，只其中一侧设置多个热源亦可，也即在晶圆100的至少一侧设置多个热源；并如图2所示，晶圆任一侧的多个热源覆盖晶圆表面及晶圆周侧的区域，也即任一侧的多个热源不仅覆盖晶圆表面，还延伸到晶圆之外的区域，即覆盖晶圆周侧的区域。如图2所示，以晶圆上侧为例，编号为8-20的13个热源覆盖了晶圆的上表面，编号1-7的7个热源覆盖晶圆上表面左侧的周侧的区域，编号21-26的6个热源覆盖晶圆上表面右侧的周侧的区域，且编号1-26的26个热源从左至右依次排列，晶圆下侧的编号35-48的14个热源覆盖了晶圆的下表面，编号29-34的6个热源覆盖晶圆下表面左侧的周侧的区域，编号49-54的6个热源覆盖晶圆下表面右侧的周侧的区域，且编号29-54的26个热源从左至右依次排列。在一实施例中，置于晶圆上侧的多个热源与置于晶圆下侧的多个热源一一对称设置。在一实施例中，置于晶圆上侧的多个热源与置于晶圆下侧的多个热源一一交错设置，如置于晶圆下侧的29号热源位于置于晶圆上侧的1号和2号热源之间，置于晶圆上侧的2号热源位于置于晶圆下侧的29号和30号热源之间，也即一一交错设置。如图2所示，退火装置200还包括开关单元，以晶圆上侧为例，开关单元210连接位于晶圆100上侧的1-26号热源，具体的开关单元210包括1-13号开关器件，1号开关器件连接13和14号热源，2号开关器件连接12和15号热源，依次类推，13号开关器件连接1和26号热源；对于晶圆下侧，开关单元220连接位于晶圆100下侧的29-54号热源，具体的开关单元210包括15-27号开关器件，15号开关器件连接41和42号热源，16号开关器件连接40和43热源，依次类推，27号开关器件连接29和54号热源，如此，开关单元连接每一热源。在本发明一实施例中，任一侧的多个热源在晶圆表面和周侧均匀排列。在本发明一实施例中，热源为发热灯，如灯管或灯泡；S8：获得晶圆面内形成的金属层的厚度分布数据，根据金属层的厚度分布数据计算每一热源的目标温度，开关单元根据每一热源的目标温度控制每一热源工作在其目标温度以对晶圆进行退火工艺，由于一般形成的金属层的厚度的均匀度较差，为使后续形成的金属硅化物的厚度一致，若获得晶圆某一处的金属层的厚度较厚，则可设置其附件的热源的温度较高，以使该点以较高的温度进行退火工艺，而若获得晶圆某一处的金属层的厚度较薄，则可设置其附近的热源的温度较低，以使该点以较低的温度进行退火工艺，如此实现晶圆上各点的退火温度的单独控制，而使晶圆面内通过退火工艺形成厚度均匀度高的金属硅化物层，以弥补之前金属层形成工艺形成的金属层厚度均匀度差的问题，而使形成的金属硅化物(如图1中标号140所示)的厚度在晶圆面内及电阻片内均匀度好，而提高接触电阻的均匀度，进而提高器件性能，继而提高器件良率。更具体的，在一实施例中，退火装置还包括开关控制装置230，开关控制装置230包括一输入端和至少一输出端，输入端接收每一热源的目标温度信号，根据每一热源的目标温度信号得到开关单元210和220中每一开关的控制信号，并通过其输出端输出开关控制信号至开关单元210和220中的每一个开关器件，以控制每一开关器件的导通程度，进而控制与该开关器件连接的热源的温度。在一实施例中，开关单元中每一开关器件为IGBT，本发明对开关器件的类型不限定，只要其能根据开关信号控制其导通程度即可。See Figure 1 and Figure 2. Specifically, after S1 to S6, as shown in FIG. 1, the wafer 100 includes the gate structure 110 and the source electrode 121 and the drain electrode 122 located on both sides of the gate structure 110, and the gate structure 110, A metal layer (not shown in the figure) is formed on the source electrode 121 and the drain electrode 122. In one embodiment, the thickness of the metal layer is between 30 angstroms and 150 angstroms. A protective layer is formed on the layer, and the thickness of the protective layer is between 40 angstroms and 100 angstroms. If the metal layer is titanium, the protective layer can be titanium nitride; in S7, as shown in FIG. The circle 100 is placed in an annealing apparatus 200, and the annealing apparatus 200 includes a plurality of heat sources, such as 56 heat sources numbered 1-56 arranged along the surface of the wafer 100 as shown in FIG. 2, in the embodiment shown in FIG. 2 A plurality of heat sources are arranged on both sides of the wafer 100, but the present invention is not limited to having a plurality of heat sources arranged on both sides, and only one side of the wafer 100 can be arranged with a plurality of heat sources, that is, at least one side of the wafer 100 is arranged with a plurality of heat sources. and as shown in Figure 2, multiple heat sources on either side of the wafer cover the wafer surface and the area around the wafer, that is, multiple heat sources on either side not only cover the wafer surface, but also extend to the wafer The other area is the area covering the peripheral side of the wafer. As shown in Figure 2, taking the upper side of the wafer as an example, 13 heat sources numbered 8-20 cover the upper surface of the wafer, and 7 heat sources numbered 1-7 cover the peripheral side on the left side of the upper surface of the wafer. Area, the 6 heat sources numbered 21-26 cover the area on the right peripheral side of the upper surface of the wafer, and the 26 heat sources numbered 1-26 are arranged in order from left to right, and the 14 heat sources numbered 35-48 on the lower side of the wafer 1 heat source covers the lower surface of the wafer, 6 heat sources numbered 29-34 cover the area on the left side of the lower surface of the wafer, and 6 heat sources numbered 49-54 cover the area on the right side of the lower surface of the wafer. area, and the 26 heat sources numbered 29-54 are arranged in order from left to right. In one embodiment, the plurality of heat sources placed on the upper side of the wafer and the plurality of heat sources placed on the lower side of the wafer are arranged symmetrically one-to-one. In one embodiment, the plurality of heat sources placed on the upper side of the wafer and the plurality of heat sources placed on the lower side of the wafer are staggered one by one. For example, the No. 29 heat source placed on the lower side of the wafer is placed on the upper side of the wafer. Between the No. 1 and No. 2 heat sources, the No. 2 heat source placed on the upper side of the wafer is located between the No. 29 and No. 30 heat sources placed on the lower side of the wafer, that is, staggered one by one. As shown in FIG. 2 , the annealing apparatus 200 further includes a switch unit. Taking the upper side of the wafer as an example, the switch unit 210 is connected to the No. 1-26 heat sources located on the upper side of the wafer 100 , and the specific switch unit 210 includes No. 1-13 switches. device, the No. 1 switching device is connected to the heat sources 13 and 14, the switching device No. 2 is connected to the heat sources 12 and 15, and so on, the switching device No. 13 is connected to the heat sources 1 and 26; for the lower side of the wafer, the switch unit 220 is connected to the No. 29-54 heat sources on the lower side of the circle 100, the specific switch unit 210 includes No. 15-27 switching devices, No. 15 switching device is connected to No. 41 and No. 42 heat sources, No. 16 switching device is connected to No. 40 and 43 heat sources, and so on, No. 27 The switching device connects heat sources 29 and 54, so that the switching unit connects to each heat source. In an embodiment of the present invention, the plurality of heat sources on either side are evenly arranged on the wafer surface and the peripheral side. In an embodiment of the present invention, the heat source is a heating lamp, such as a lamp tube or a light bulb; S8: Obtain thickness distribution data of the metal layer formed in the wafer surface, and calculate the target temperature of each heat source according to the thickness distribution data of the metal layer, The switch unit controls each heat source to work at its target temperature according to the target temperature of each heat source to perform an annealing process on the wafer. Since the thickness of the generally formed metal layer is poor in uniformity, in order to make the thickness of the metal silicide formed subsequently Consistently, if the thickness of the metal layer in a certain part of the wafer is thicker, the temperature of the heat source of its attachment can be set higher, so that the annealing process is performed at a higher temperature at this point, and if a certain part of the wafer is obtained If the thickness of the metal layer is thinner, the temperature of the heat source nearby can be set lower, so that the annealing process is performed at a lower temperature at this point, so that the annealing temperature of each point on the wafer can be individually controlled, and the crystal In the circular plane, a metal silicide layer with high thickness uniformity is formed by an annealing process to make up for the problem of poor thickness uniformity of the metal layer formed by the previous metal layer forming process, and the formed metal silicide (as shown by the reference number 140 in FIG. 1 ) The thickness of the shown) has good uniformity in the wafer surface and in the resistance sheet, which improves the uniformity of the contact resistance, thereby improving the performance of the device, and then improving the yield of the device. More specifically, in one embodiment, the annealing device further includes a switch control device 230. The switch control device 230 includes an input terminal and at least one output terminal. The input terminal receives the target temperature signal of each heat source. According to the target temperature of each heat source. The temperature signal obtains the control signal of each switch in the switch units 210 and 220, and outputs the switch control signal to each switch device in the switch units 210 and 220 through its output terminal to control the degree of conduction of each switch device, and then Controls the temperature of the heat source connected to the switching device. In one embodiment, each switching device in the switching unit is an IGBT. The present invention does not limit the type of the switching device, as long as it can control its degree of conduction according to the switching signal.

在一实施例中，在晶圆上侧还设置有27号和28号热源，其由14号开关器件控制，27号和28号热源设置在与1-26号热源的排列方向垂直的方向上的晶圆的两侧。同样的，在一实施例中，也可在晶圆上侧还设置有55号和56号热源，其由28号开关器件控制，55号和56号热源设置在与29-54号热源的排列方向垂直的方向上的晶圆的两侧。In one embodiment, the upper side of the wafer is also provided with No. 27 and No. 28 heat sources, which are controlled by No. 14 switching devices, and the No. 27 and No. 28 heat sources are arranged in a direction perpendicular to the arrangement direction of No. 1-26 heat sources. both sides of the wafer. Similarly, in one embodiment, heat sources No. 55 and No. 56 may also be provided on the upper side of the wafer, which are controlled by the switching device No. 28, and the heat sources No. 55 and No. 56 are arranged in an arrangement with the heat sources No. 29-54. The directions are perpendicular to the sides of the wafer.

在一实施例中，较佳的，所述退火工艺采用双面加热的退火工艺，也即在晶圆的两侧均设置多个热源，如此可进一步提高接触电阻的均匀度。In one embodiment, preferably, the annealing process adopts a double-sided heating annealing process, that is, multiple heat sources are arranged on both sides of the wafer, so that the uniformity of the contact resistance can be further improved.

在一实施例中，所述退火工艺为等温退火工艺、尖峰退火工艺或等温退火工艺和尖峰退火工艺的结合。在一实施例中，退火工艺中，热源的目标温度区间为450℃至700℃之间,其升温速率为30℃/s至200℃/s之间。在一实施例中，退火工艺中，气体流量包括氮气和氦气，氮气和氦气的总流量在15slm至250slm之间。在一实施例中，退火工艺中的吹气方式为顶部吹气、边缘吹气或顶部吹气和边缘吹气的结合。在一实施例中，退火工艺的退火时间为1s至30s之间。在一实施例中，退火工艺中，晶圆转速为50r/min至100r/min之间，在一实施例中，退火工艺中，氧气(O2)含量小于等于10ppm。In one embodiment, the annealing process is an isothermal annealing process, a spike annealing process, or a combination of the isothermal annealing process and the spike annealing process. In one embodiment, in the annealing process, the target temperature range of the heat source is between 450°C and 700°C, and the heating rate is between 30°C/s and 200°C/s. In one embodiment, in the annealing process, the gas flow includes nitrogen and helium, and the total flow of nitrogen and helium is between 15 slm and 250 slm. In one embodiment, the blowing method in the annealing process is top blowing, edge blowing, or a combination of top blowing and edge blowing. In one embodiment, the annealing time of the annealing process is between 1 s and 30 s. In one embodiment, in the annealing process, the wafer rotation speed is between 50 r/min and 100 r/min. In one embodiment, in the annealing process, the oxygen (O 2 ) content is less than or equal to 10 ppm.

在一实施例中，金属层为钛(Ti)金属层或钴(Co)金属层，对应的形成的金属硅化物为富金属相钛化硅(TiSix)或富金属相钴化硅(CoSix)。In one embodiment, the metal layer is a titanium (Ti) metal layer or a cobalt (Co) metal layer, and the corresponding formed metal silicide is a metal-rich phase titanium silicon (TiSix) or a metal-rich phase cobalt silicon (CoSix) .

在一实施例中，在S3中外延形成的金属硅化物为硅锗或硅磷的金属硅化物。锗硅的金属硅化物形成的外延层，用于提高PMOS管的沟道区的空穴迁移率，PMOS管的源区和漏区形成于所述源漏嵌入式外延层中。硅磷的金属硅化物形成的外延层，用于提高NMOS管的沟道区的电子迁移率，NMOS管的源区和漏区形成于所述源漏嵌入式外延层中。In one embodiment, the metal silicide epitaxially formed in S3 is silicon germanium or silicon phosphorus metal silicide. The epitaxial layer formed by metal silicide of silicon germanium is used to improve the hole mobility of the channel region of the PMOS transistor, and the source region and the drain region of the PMOS transistor are formed in the source-drain embedded epitaxial layer. The epitaxial layer formed of silicon phosphorus metal silicide is used to improve the electron mobility of the channel region of the NMOS transistor, and the source region and the drain region of the NMOS transistor are formed in the source-drain embedded epitaxial layer.

如上所述，在作为半导体器件的栅极、源极和漏极上的金属接触层的金属硅化物的形成过程中的退火工艺中，在晶圆的至少一侧设置多个热源，多个热源覆盖晶圆表面及晶圆周侧的区域，并设置开关单元，用于控制每个热源的温度，首先获得晶圆面内形成的金属层的厚度分布数据，然后根据金属层的厚度分布数据计算每一热源的目标温度，并使开关单元控制每一热源工作在其目标温度以对晶圆进行退火工艺，而使形成的金属硅化物的厚度在晶圆面内及电阻片内均匀度好，而提高接触电阻的均匀度，进而提高器件性能，继而提高器件良率。As described above, in the annealing process during the formation of the metal silicide as the metal contact layer on the gate, source and drain of the semiconductor device, a plurality of heat sources are provided on at least one side of the wafer, the plurality of heat sources Covering the area on the wafer surface and the peripheral side of the wafer, and setting a switch unit to control the temperature of each heat source, first obtain the thickness distribution data of the metal layer formed in the wafer surface, and then calculate each A target temperature of a heat source, and the switch unit controls each heat source to work at its target temperature to perform an annealing process on the wafer, so that the thickness of the formed metal silicide has a good uniformity in the wafer surface and the resistor sheet, and Improve the uniformity of the contact resistance, thereby improving the device performance, thereby improving the device yield.

最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention. scope.

Claims (16)

1. An annealing process for forming metal silicide, comprising:
s1: providing a wafer, wherein the wafer comprises a formed grid structure, a source electrode and a drain electrode which are positioned at two sides of the grid structure, and metal layers are formed on the grid structure, the source electrode and the drain electrode;
s2: placing a wafer in an annealing device, wherein the annealing device comprises a plurality of heat sources and a switch unit, the heat sources are placed on at least one side of the wafer and cover the surface of at least one side of the wafer and the area around the wafer, and the switch unit is connected with each heat source; and
s3: the method comprises the steps of obtaining thickness distribution data of a metal layer formed in a wafer surface, calculating target temperature of each heat source according to the thickness distribution data of the metal layer, and controlling each heat source to work at the target temperature according to the target temperature of each heat source by a switch unit so as to carry out annealing process on the wafer.
2. The annealing process for forming metal silicide of claim 1 wherein a plurality of heat sources are provided on both sides of the wafer.
3. The annealing process for forming metal silicide of claim 1, wherein the annealing apparatus further comprises a switch control apparatus, the switch control apparatus comprises an input terminal and at least one output terminal, the input terminal receives the target temperature signal of each heat source, obtains the control signal of each switch in the switch unit according to the target temperature signal of each heat source, and outputs the switch control signal to each switch device in the switch unit through the output terminal thereof, so as to control the conduction degree of each switch device, thereby controlling the temperature of the heat source connected to the switch device.
4. The annealing process for forming metal silicide of claim 1, wherein the annealing process is an isothermal annealing process, a spike annealing process, or a combination thereof.
5. The annealing process for forming metal silicide according to claim 4, wherein in the annealing process, the target temperature range of the heat source is 450 ℃ to 700 ℃, and the temperature rise rate is 30 ℃/s to 200 ℃/s; the gas flow rate comprises nitrogen and helium, and the total flow rate of the nitrogen and the helium is between 15slm and 250 slm; the blowing mode in the annealing process is top blowing, edge blowing or the combination of the top blowing and the edge blowing; the annealing time of the annealing process is between 1s and 30 s; the rotating speed of the wafer is between 50r/min and 100 r/min; the oxygen (O2) content is 10ppm or less.
6. An annealing apparatus for forming metal silicide using the annealing process for forming metal silicide of claim 1, comprising:
the heat sources are arranged on at least one side of the wafer and cover the surface of at least one side of the wafer and the area on the peripheral side of the wafer;
a switch unit connected to each heat source; and
the switch control device comprises an input end and at least one output end, the input end receives a target temperature signal of each heat source, the switch control device obtains a control signal of each switch in the switch unit according to the target temperature signal of each heat source and outputs the switch control signal to each switch device in the switch unit through the output end of the switch control device so as to control the conduction degree of each switch device and further control the temperature of the heat source connected with the switch device, wherein the target temperature signal of each heat source is related to the thickness of a metal layer of a point, corresponding to the heat source, in the wafer surface.
7. The annealing apparatus for forming metal silicide of claim 6, wherein a plurality of heat sources are provided on both sides of the wafer.
8. The annealing apparatus for forming metal silicide of claim 6, wherein the plurality of heat sources on either side are uniformly arranged on the surface and the peripheral side of the wafer.
9. The annealing device for forming metal silicide of claim 6, wherein the heat source is a heat lamp.
10. A method for forming a metal contact layer of a FinFet device is characterized by comprising the following steps:
s1: providing a wafer, and forming a plurality of fin bodies on the wafer, wherein the fin bodies are arranged in parallel;
s2: forming a plurality of polysilicon gates, wherein the polysilicon gates cover partial top surfaces and partial side surfaces of the fin bodies, the fin body areas covered by the polysilicon gates are used for forming channel areas, and source electrode areas and drain electrode areas are positioned on two sides of the polysilicon gates;
s3: forming a source electrode region and a drain electrode region on the fin body, and epitaxially forming metal silicide on the source electrode region and the drain electrode region;
s4: removing the polysilicon gate, and forming a metal gate in the removal region of the polysilicon gate;
s5: ion implantation is carried out to form an amorphous layer on the metal silicide so as to form a source electrode and a drain electrode;
s6: forming a metal layer on the metal gate, the source electrode and the drain electrode;
s7: placing a wafer in an annealing device, wherein the annealing device comprises a plurality of heat sources and a switch unit, the heat sources are placed on at least one side of the wafer and cover the surface of at least one side of the wafer and the area around the wafer, and the switch unit is connected with each heat source; and
s8: the method comprises the steps of obtaining thickness distribution data of a metal layer formed in a wafer surface, calculating the target temperature of each heat source according to the thickness distribution data of the metal layer, and controlling each heat source to work at the target temperature according to the target temperature of each heat source by a switch unit so as to carry out annealing process on the wafer.
11. The method of forming a metal contact layer for a FinFet device of claim 10 wherein the metal layer is a titanium metal layer or a cobalt metal layer.
12. The method of forming a metal contact layer for a FinFet device of claim 10 wherein the metal silicide epitaxially formed in S3 is a metal silicide of silicon germanium or silicon phosphorous.
13. The FinFet device metal contact layer formation method of claim 10, wherein a plurality of heat sources are provided on both sides of the wafer.
14. The method as claimed in claim 10, wherein the annealing device further comprises a switch control device, the switch control device comprises an input terminal and at least one output terminal, the input terminal receives the target temperature signal of each heat source, obtains a control signal for each switch in the switch unit according to the target temperature signal of each heat source, and outputs the switch control signal to each switch device in the switch unit through the output terminal thereof, so as to control the conduction degree of each switch device and further control the temperature of the heat source connected to the switch device.
15. The method of forming a metal contact layer for a FinFet device of claim 10 wherein the annealing process is an isothermal annealing process, a spike annealing process or a combination of isothermal and spike annealing processes.
16. The FinFet device metal contact layer forming method of claim 15, wherein in the annealing process, the target temperature interval of the heat source is between 450 ℃ and 700 ℃, and the temperature rise rate is between 30 ℃/s and 200 ℃/s; the gas flow rate comprises nitrogen and helium, and the total flow rate of the nitrogen and the helium is between 15slm and 250 slm; the blowing mode in the annealing process is top blowing, edge blowing or the combination of the top blowing and the edge blowing; the annealing time of the annealing process is between 1s and 30 s; the rotating speed of the wafer is between 50r/min and 100 r/min; the oxygen (O2) content is 10ppm or less.
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