CN107611123B - Direct Bandgap GeSn Complementary TFET - Google Patents

Abstract

The present invention relates to a direct bandgap GeSn complementary TFET, comprising: a Si substrate 101; a Ge epitaxial layer 102 arranged on the upper surface of the substrate 101; a GeSn layer 103 arranged on the upper surface of the Ge epitaxial layer 102; a P-type substrate 104 , N-type substrate 105, disposed in GeSn layer 103; first source region 106, first drain region 107, disposed in P-type substrate 104 and located at both sides; second source region 108, second drain region 109 , arranged in the N-type substrate 105 and located on both sides; the first source region electrode 110 is arranged on the upper surface of the first source region 106; the first drain region electrode 111 is arranged on the upper surface of the first drain region 107; The second source region electrode 112 is disposed on the upper surface of the second source region 108 ; the second drain region electrode 113 is disposed on the upper surface of the second drain region 109 . The present invention uses the crystallized Ge layer as the Ge epitaxial layer, which can effectively reduce the dislocation density, surface roughness, and interface defects of the Ge epitaxial layer, and improve the quality of the Ge epitaxial layer to obtain a higher-quality GeSn epitaxial layer, which is a high-performance TFET. The preparation provides the material basis.

Description

Direct Bandgap GeSn Complementary TFET

technical field

The invention relates to the technical field of integrated circuits, in particular to a direct bandgap GeSn complementary TFET.

Background technique

The semiconductor industry is a symbol of modern technology. With the rapid progress of the modern technology industry in recent decades, the market size of the semiconductor industry dominated by integrated circuits has also continued to grow. Now it has become one of the important pillar industries of the global economy. With the continuous reduction of the feature size of semiconductor devices, especially after entering the nanometer size, the impact of negative effects such as short channel effect in the device on the performance of the device leakage current, sub-threshold characteristics, on-state/off-state current, etc. is becoming more and more prominent. , the contradiction between circuit speed and power consumption will become more and more serious.

Aiming at this problem, it has been proposed that a more effective method is to reduce the influence of the short channel effect by replacing the traditional MOSFET with a new type of device with a low subthreshold swing, the tunneling field effect transistor. Tunneling field effect transistor (Tunneling field effect transistor, referred to as TFET) is a PIN structure transistor, it works based on the quantum tunneling effect of carriers, and can be optimized through device, so that the subthreshold swing of the tunneling transistor is in It drops below 60mV/dec at room temperature. Using complementary TFETs instead of traditional CMOS can further reduce circuit size, lower voltage, and reduce power consumption.

However, due to the small on-state current of the tunneling transistor, its circuit performance is insufficient, which limits the application of the tunneling transistor.

Contents of the invention

Therefore, in order to solve the technical defects and deficiencies existing in the prior art, the present invention proposes a direct bandgap GeSn complementary TFET.

Specifically, a direct bandgap GeSn complementary TFET 100 proposed by an embodiment of the present invention includes:

Si substrate 101;

Ge epitaxial layer 102, disposed on the upper surface of the substrate 101;

GeSn layer 103, disposed on the upper surface of the Ge epitaxial layer 102;

A P-type substrate 104 and an N-type substrate 105 are disposed in the GeSn layer 103;

The first source region 106 and the first drain region 107 are arranged in the P-type substrate 104 and located on both sides;

The second source region 108 and the second drain region 109 are arranged in the N-type substrate 105 and located on both sides;

a first source region electrode 110, disposed on the upper surface of the first source region 106;

The first drain region electrode 111 is disposed on the upper surface of the first drain region 107;

a second source region electrode 112 disposed on the upper surface of the second source region 108;

The second drain region electrode 113 is disposed on the upper surface of the second drain region 109 .

In one embodiment of the present invention, the Si substrate 101 is N-type single crystal silicon with a doping concentration of 5×10 ¹⁸ cm ⁻³ .

In one embodiment of the present invention, the Ge epitaxial layer 102 is a crystallized Ge layer.

In one embodiment of the present invention, the Ge epitaxial layer 102 is N-type doped and has a thickness of 200-300 nm.

In one embodiment of the present invention, the GeSn layer 103 is N-type doped and has a thickness of 140-160 nm.

In one embodiment of the present invention, the thicknesses of the first source region electrode 110, the first drain region electrode 111, the second source region electrode 112 and the second drain region electrode 113 are all 20- 30nm.

In one embodiment of the present invention, the direct bandgap GeSn complementary TFET10 further includes a first gate dielectric layer 114, a first gate material layer 115, a second gate dielectric layer 116, and a second gate material layer 117; in,

The first gate dielectric layer 114 is disposed in the middle of the upper surface of the P-type substrate 104;

The first gate material layer 115 is disposed on the upper surface of the first gate dielectric layer 114;

The second gate dielectric layer 116 is disposed in the middle of the upper surface of the N-type substrate 105;

The second gate material layer 117 is disposed on the upper surface of the second gate dielectric layer 116 .

In one embodiment of the present invention, the direct bandgap GeSn complementary TFET 10 further includes sidewalls 118, and the sidewalls 118 are arranged on the first gate dielectric layer 114, the first gate material layer 115, Positions on both sides of the second gate dielectric layer 116 and the second gate material layer 117 .

In one embodiment of the present invention, the direct bandgap GeSn complementary TFET 10 further includes an isolation layer 119 , and the isolation layer 119 is disposed on both sides and in the middle of the direct bandgap GeSn complementary TFET 10 .

In one embodiment of the present invention, the direct bandgap GeSn complementary TFET10 further includes a passivation layer 120 and a dielectric layer 121; wherein,

The passivation layer 120 covers the upper surfaces of the first source electrode 110 , the first drain electrode 111 , the second source electrode 112 and the second drain electrode 113 ;

The dielectric layer 110 is filled in the passivation layer 109 and the first source electrode 110, the first drain electrode 111, the second source electrode 112, the second drain electrode 113 and The spatial position where the isolation layer 119 is formed.

In the above-mentioned embodiment, the Ge epitaxial layer is a crystallized Ge layer, which adopts a laser recrystallization (Laser Re-Crystallization, LRC for short) process, that is, a method of thermally induced phase change crystallization. Through continuous laser heat treatment, the Si The Ge epitaxial layer on the substrate is melted and recrystallized, and the dislocation defects of the Ge epitaxial layer are released laterally. Not only can a high-quality Ge epitaxial layer be obtained, but also the problems existing in the conventional two-step process can be overcome. The growth of the material with GeSn provides the necessary foundation, and thus becomes the favorable technical condition for the preparation of the direct bandgap GeSn complementary TFET device.

Other aspects and features of the present invention will become apparent from the following detailed description with reference to the accompanying drawings. It should be understood, however, that the drawings are designed for purposes of illustration only and not as a limitation of the scope of the invention since reference should be made to the appended claims. It should also be understood that, unless otherwise indicated, the drawings are not necessarily drawn to scale and are merely intended to conceptually illustrate the structures and processes described herein.

Description of drawings

The specific implementation manners of the present invention will be described in detail below in conjunction with the accompanying drawings.

Fig. 1 is a schematic structural diagram of a direct bandgap GeSn complementary TFET provided by an embodiment of the present invention;

2 is a schematic diagram of a laser-assisted recrystallization process provided by an embodiment of the present invention;

3 is a schematic structural diagram of another direct bandgap GeSn complementary TFET provided by an embodiment of the present invention;

Fig. 4a-Fig. 4y are process schematic diagrams of a direct bandgap GeSn complementary TFET provided by an embodiment of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

Embodiment one

Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a direct bandgap GeSn complementary TFET 100 provided by an embodiment of the present invention, including:

Si substrate 101;

Ge epitaxial layer 102, disposed on the upper surface of the substrate 101;

GeSn layer 103, disposed on the upper surface of the Ge epitaxial layer 102;

A P-type substrate 104 and an N-type substrate 105 are disposed in the GeSn layer 103;

The first source region 106 and the first drain region 107 are arranged in the P-type substrate 104 and located on both sides;

The second source region 108 and the second drain region 109 are arranged in the N-type substrate 105 and located on both sides;

a first source region electrode 110, disposed on the upper surface of the first source region 106;

The first drain region electrode 111 is disposed on the upper surface of the first drain region 107;

a second source region electrode 112 disposed on the upper surface of the second source region 108;

The second drain region electrode 113 is disposed on the upper surface of the second drain region 109 .

Further, on the basis of the above embodiments, the Si substrate 101 is N-type single crystal silicon with a doping concentration of 5×10 ¹⁸ cm ⁻³ .

Further, on the basis of the above embodiments, the Ge epitaxial layer 102 is a crystallized Ge layer. Among them, laser recrystallization (Laser Re-Crystallization, referred to as LRC process), that is, a method of thermally induced phase change crystallization, is used to melt and recrystallize the Ge epitaxial layer on the Si substrate through continuous laser heat treatment to form the crystallization Ge layer, releasing the dislocation defects of the Ge epitaxial layer laterally, not only can obtain high-quality Ge epitaxial layer, but also can overcome the problems existing in the conventional two-step process, and provide a great opportunity for the growth of high-quality direct bandgap narrow-bandgap GeSn materials. The necessary basis, thus becoming the favorable technical conditions for the preparation of direct bandgap GeSn complementary TFET devices.

Further, on the basis of the above embodiments, the Ge epitaxial layer 102 is N-type doped and has a thickness of 200-300 nm.

Further, on the basis of the above embodiments, the GeSn layer 103 is N-type doped and has a thickness of 140-160 nm.

Further, on the basis of the above embodiments, the thicknesses of the first source region electrode 110, the first drain region electrode 111, the second source region electrode 112 and the second drain region electrode 113 are all 20-30nm.

Further, on the basis of the above embodiments, the direct bandgap GeSn complementary TFET 10 further includes a first gate dielectric layer 114, a first gate material layer 115, a second gate dielectric layer 116 and a second gate material layer 117; of which,

The first gate dielectric layer 114 is disposed in the middle of the upper surface of the P-type substrate 104;

The first gate material layer 115 is disposed on the upper surface of the first gate dielectric layer 114;

The second gate dielectric layer 116 is disposed in the middle of the upper surface of the N-type substrate 105;

The second gate material layer 117 is disposed on the upper surface of the second gate dielectric layer 116 .

Further, on the basis of the above embodiments, please refer to FIG. 3 . FIG. 3 is a schematic structural diagram of another direct bandgap GeSn complementary TFET provided by an embodiment of the present invention. The direct bandgap GeSn complementary TFET10 also includes sidewalls 118, the sidewalls 118 are arranged on both sides of the first gate dielectric layer 114, the first gate material layer 115, the second gate dielectric layer 116 and the second gate material layer 117 side position.

Further, on the basis of the above embodiment, please refer to FIG. 3 again, the direct bandgap GeSn complementary TFET10 further includes an isolation layer 119, and the isolation layer 119 is arranged on two sides inside the direct bandgap GeSn complementary TFET10. side and middle positions.

Further, on the basis of the above embodiments, please refer to FIG. 3 again, the direct bandgap GeSn complementary TFET 10 further includes a passivation layer 120 and a dielectric layer 121; wherein,

The passivation layer 120 covers the upper surfaces of the first source electrode 110 , the first drain electrode 111 , the second source electrode 112 and the second drain electrode 113 ;

The dielectric layer 110 is filled in the passivation layer 109 and the first source electrode 110, the first drain electrode 111, the second source electrode 112, the second drain electrode 113 and The spatial position where the isolation layer 119 is formed.

The beneficial effects of the present invention are specifically:

1. The present invention uses the crystallized Ge layer as the Ge epitaxial layer, which can effectively reduce the dislocation density, surface roughness, and interface defects of the Ge epitaxial layer, and improve the quality of the Ge epitaxial layer to obtain a higher-quality GeSn epitaxial layer, which is high The preparation of performance TFET provides the material basis;

2. The direct bandgap GeSn complementary TFET based on the LRC process provided by the present invention, compared with traditional CMOS devices, has a smaller subthreshold effect and can solve the short channel effect; compared with traditional Si materials, the carrier migration of GeSn materials The efficiency is increased several times, and the indirect bandgap material is converted into a direct bandgap material by adjusting the Sn composition, which increases the carrier tunneling probability, thereby improving the current drive and frequency characteristics of the TFET device.

Embodiment two

Please refer to FIG. 4a-FIG. 4y. FIG. 4a-FIG. 4y are process schematic diagrams of a direct bandgap GeSn complementary TFET provided by an embodiment of the present invention. On the basis of the above embodiments, this embodiment will introduce the process flow of the present invention in more detail. The method includes:

S101. Substrate selection. As shown in Figure 4a, an N-type single crystal silicon (Si) substrate 001 with a doping concentration of 5×10 ¹⁸ cm ^-3 is selected as the initial material 001;

S102, Ge epitaxial layer growth. As shown in Figure 4b, at a temperature of 500°C-600°C, a 200-300nm N-type lightly doped Ge epitaxial layer 002 is grown on the surface of the Si substrate material 001 by using a CVD process;

S103, preparation of a protective layer. As shown in Figure 4b, a 100-150nm SiO ₂ layer 003 is deposited on the surface of the Ge epitaxial layer 002 by using a CVD process;

S104, crystallization of the Ge epitaxial layer and etching of the protective layer. As shown in Figures 4c-4d, the entire substrate material including Si substrate material 001, Ge epitaxial layer 002 and _SiO2 layer 003 is heated to 700°C, and the entire substrate material is continuously crystallized by laser recrystallization process , where the laser wavelength is 808nm, the laser spot size is 10mm×1mm, the laser power is 1.5kW/cm ² , and the laser moving speed is 25mm/s. The entire substrate material is naturally cooled, and SiO is etched by a dry etching process. ₂ layers 003, to obtain high-quality Ge epitaxial layer material 004 formed by recrystallization of direct epitaxial Ge material 002;

S105, GeSn layer growth. As shown in Fig. 4e, the temperature was lowered below 350 °C in _H2 atmosphere with _SnCl4 and _GeH4 as Sn and Ge sources, respectively. The gas flow ratio of GeH ₄ /SnCl ₄ is 6.14˜6.18 (determined by Ge/Sn composition, here we are growing GeSn material of Ge _x Sn _1-x with x=0.86). An N-type lightly doped GeSn region 005 with a thickness of 140-160 nm is grown. The thickness of the GeSn region 005 can also be selected to be 146nm.

S106 , shallow trench isolation. As shown in Figure 4f, a shallow trench isolation structure is prepared in the GeSn region 005, and a trench isolation 006 is formed;

S107, forming a P well. As shown in Figure 4g-4h:

S1071, deposit a layer of photoresist 007 on the surface of the GeSn region 005 and the trench isolation 006, and expose the P well region by photolithography through mask exposure;

S1072, forming a P well 008 in the P well region by ion implantation as the base region of the N-type tunneling transistor;

S1073, removing the photoresist 007;

S1074, annealing. Heating in _H2 environment at 600-1000°C to repair Si surface crystal damage caused by ion implantation.

S108 , depositing an insulating layer and a conductive layer. As shown in FIG. 4i, a high-k gate dielectric layer 009, a gate material layer 010 and a silicon nitride protection layer 011 are deposited with an equivalent oxide thickness (EOT, equivalent oxide thickness) of 1 nm.

Among them, the thinner gate dielectric thickness ensures the control ability of the gate electrode to the tunnel junction, and at the same time, the high-k dielectric is used to significantly improve the electrical characteristics of the device such as drive current and sub-threshold swing.

S109, photolithography of the gate stack region. As shown in Figure 4j-4l:

S1091, depositing photoresist 012, and exposing the mask to photolithography to form the pattern of the gate lamination region;

S1092, respectively etching away the high-k gate dielectric layer 009, the gate material layer 010 and the silicon nitride protection layer 011 until the GeSn region 005 is exposed, forming the gates of the N-type TFET and the P-type TFET;

S1093, removing the photoresist 012 and the silicon nitride protection layer 011;

S110, defining source and drain regions. As shown in Figure 4m-4t:

S1101. Deposit photoresist 013; photoetch the implanted pattern of the P-type TFET source region; implant P+ with an ion dose of 3×10 ¹⁹ cm ^-2 to form N-type doped source region 014; remove photoresist 013 ;

S1102, depositing photoresist 015; photoetching the implanted pattern of the N-type TFET drain region; implanting P+ with an ion dose of 2×10 ¹⁸ cm ^-2 to form an N-type doped drain region 016; removing the photoresist 015;

S1103. Deposit and form photoresist 017; photoetch the implant pattern of P-type TFET drain region; ion implant dose of 5×10 ¹⁸ cm ^-2 BF ²⁺ to form P-type doped drain region 018; remove photolithography Glue 017;

S1104. Deposit and form photoresist 019; photoetch the implanted pattern of the N-type TFET source region; implant BF ²⁺ with an ion dose of 1×10 ¹⁹ cm ^-2 to form the P-type doped source region 020; remove the photolithography Glue 019.

S111, activating the source and drain regions. The source and drain regions are rapidly annealed at a temperature of 400° C. for 5 minutes to activate impurities.

S112, forming side walls. As shown in Figure 4u-4v, deposit a layer of silicon dioxide film 021, then deposit photoresist 022, form N-type TFET gate and P-type TFET gate sidewall 023 after etching, and remove photoresist 022 and 021 with silicon dioxide film.

S113, depositing metal electrodes:

S1131, depositing a dielectric layer. As shown in FIG. 4w, a dielectric layer 024 is formed by depositing 20-30nm of BPSG by CVD process, so as to prevent mobile ions from diffusing to the gate and damage device performance.

S1132 , etching a contact hole. Etch BPSG with nitric acid and hydrofluoric acid to form source and drain contact holes;

S1133, forming a contact electrode. As shown in FIG. 4x: contact metal 025 of 10-20nm is evaporated and deposited, and the contact metal is selectively etched to a designated area, and planarized by chemical mechanical polishing (CMP).

S1134, passivation. As shown in FIG. 4y : 20-30nm silicon nitride 026 is deposited by CVD process for passivating the dielectric.

In summary, this paper uses specific examples to illustrate the structure and implementation of a direct bandgap GeSn complementary TFET provided by the embodiment of the present invention. The description of the above embodiment is only used to help understand the method of the present invention and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation and scope of application. The scope of protection of the present invention should be based on the appended claims.

Claims (9)

1. A direct bandgap GeSn complementary TFET (100), comprising:

a Si substrate (101);

a Ge epitaxial layer (102) arranged on the upper surface of the substrate (101); the Ge epitaxial layer is a crystallized Ge layer, the crystallized Ge layer is processed by adopting a continuous laser recrystallization process, the laser wavelength is 808nm, the laser spot size is 10mm multiplied by 1mm, and the laser power is 1.5kW/cm²The laser moving speed is 25mm/s, and the heating temperature is 700 ℃;

a GeSn layer (103) arranged on the upper surface of the Ge epitaxial layer (102);

a P-type substrate (104) and an N-type substrate (105) which are arranged in the GeSn layer (103);

the first source region (106) and the first drain region (107) are arranged in the P-type substrate (104) and located at two sides;

the second source region (108) and the second drain region (109) are arranged in the N-type substrate (105) and located at two sides;

a first source region electrode (110) disposed on an upper surface of the first source region (106);

a first drain region electrode (111) provided on an upper surface of the first drain region (107);

a second source region electrode (112) disposed on an upper surface of the second source region (108);

and a second drain electrode (113) disposed on an upper surface of the second drain region (109).

2. The complementary TFET (100) according to claim 1, wherein the Si substrate (101) is N-type monocrystalline silicon and has a doping concentration of 5 x 10¹⁸cm^-3。

3. The complementary TFET (100) of claim 1, wherein the Ge epilayer (102) is N-doped and has a thickness of 200 ~ 300 nm.

4. The complementary TFET (100) according to claim 1, wherein the GeSn layer (103) is N-doped and has a thickness of 140 ~ 160 nm.

5. The complementary TFET (100) of claim 1, wherein the first source electrode (110), the first drain electrode (111), the second source electrode (112), and the second drain electrode (113) are each 20 ~ 30nm thick.

6. The complementary TFET (100) of claim 5, further comprising a first gate dielectric layer (114), a first gate material layer (115), a second gate dielectric layer (116), and a second gate material layer (117); wherein,

the first gate dielectric layer (114) is arranged in the middle of the upper surface of the P-type substrate (104);

the first grid electrode material layer (115) is arranged on the upper surface of the first grid electrode dielectric layer (114);

the second gate dielectric layer (116) is arranged in the middle of the upper surface of the N-type substrate (105);

the second gate material layer (117) is arranged on the upper surface of the second gate dielectric layer (116).

7. The complementary TFET (100) according to claim 6, further comprising spacers (118), wherein the spacers (118) are disposed at two sides of the first gate dielectric layer (114), the first gate material layer (115), the second gate dielectric layer (116) and the second gate material layer (117).

8. The complementary TFET (100) of claim 1, further comprising an isolation layer (119), the isolation layer (119) disposed between the P-type substrate (104) and the N-type substrate (105).

9. The complementary TFET (100) of claim 8, further comprising a passivation layer (120) and a dielectric layer (121); wherein,

the passivation layer (120) covers the upper surfaces of the first source region electrode (110), the first drain region electrode (111), the second source region electrode (112) and the second drain region electrode (113);

the dielectric layer (110) is filled in the space positions formed by the passivation layer (109), the first source region electrode (110), the first drain region electrode (111), the second source region electrode (112), the second drain region electrode (113) and the isolation layer (119).