JP3543946B2 - Field effect transistor and method of manufacturing the same - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a vertical field effect transistor structure and a method of manufacturing the same.
In particular, the present invention relates to a fine vertical field effect transistor constituting an LSI. The invention also relates to a double-gate vertical field-effect transistor having a gate electrode on both sides of a semiconductor layer.
[0002]
In particular, it is an object of the present invention to achieve both controllability on the shape of the gate electrode and controllability on the thickness of the semiconductor layer.
[0003]
[Prior art]
In a field-effect transistor formed on an insulating layer provided on a substrate such as a silicon wafer, a structure in which a main channel is formed in a plane substantially perpendicular to the upper surface of the substrate is disclosed by Hasegawa in Japanese Patent Application Laid-open No. FIG. 4 of JP-8670, FIG. 2 of JP-A-64-27270 by Mama, FIG. 1 of JP-A-2-263473 by Hisamoto, and JP-A 10-93093 by Yagishita. Have been.
[0004]
The structure will be described with reference to FIG. An insulator 102 is provided over a semiconductor substrate 101, and a rectangular solid semiconductor layer 103 is provided thereover. A gate insulating film 104 is provided over the surface of the semiconductor layer 103, and a gate electrode 105 is provided over the semiconductor layer 103 over which the gate insulating film 104 is formed. Note that here, the surface of the semiconductor layer 103 refers to the upper surface and side surfaces of the semiconductor layer. The semiconductor layers 103 on both sides of the gate electrode 105 form source / drain regions into which a high concentration of impurities has been introduced. In FIG. 50, portions of the rectangular parallelepiped semiconductor layer 103 located on the near side and the far side with respect to the gate electrode are the source / drain containing high-concentration impurities. By applying an appropriate gate voltage to the gate electrode, a main channel is formed on the side surface of the rectangular solid semiconductor layer 103. Even if a channel is formed on the upper surface of the semiconductor layer 103, the width is small, so that the conduction is not dominant. The height of the normal semiconductor layer (a in FIG. 50) is larger than the width of the rectangular parallelepiped in a plane perpendicular to the direction in which the channel current flows (b in FIG. 50). FIG. 50 is based on FIG. 4 of JP-A-64-8670. In the structure of FIG. 50, the width of the semiconductor layer (b in FIG. 50) is made smaller than the total width of the depletion layer formed from the channels on both sides toward the inside of the semiconductor layer, so that the operation characteristics are excellent. A fully depleted MOSFET is obtained. A fully-depleted MOSFET having gates on both sides of a semiconductor layer in which a channel is formed has a feature of being excellent in suppressing a short-channel effect.
[0005]
In a conventional manufacturing method, first, a structure in which a rectangular parallelepiped semiconductor layer 103 is formed over an insulator 102 is formed by any method, and then the surface of the semiconductor layer 103 is thermally oxidized to provide a gate insulating film 104. Subsequently, a gate electrode material is deposited and then processed by etching to form the gate electrode 105, thereby obtaining the shape shown in FIG.
[0006]
[Problems to be solved by the invention]
(First issue)
Since the positional relationship between the source / drain and the channel is different from that of a normal MOSFET, the layout pattern of the MOSFET in the LSI is not compatible with that of the conventional MOSFET. Therefore, the arrangement of the transistors in the LSI must be changed from the conventional one. In addition, since the source / drain shapes are different, ordinary methods cannot be applied to steps relating to source / drain formation, such as introduction of impurities and formation of silicide. To change the channel width, the height of the transistor must be changed. To mix transistors having various channel widths on one wafer, mix semiconductor layers having various heights. It is necessary, and as a result, irregular irregularities are generated in the wafer, so that processing becomes extremely difficult.
[0007]
Specifically, in a normal field-effect transistor, the channel is formed on the upper surface of the semiconductor layer, whereas in the structure of FIG. 50, the side surface of the rectangular parallelepiped semiconductor layer 103 is a channel mainly contributing to conduction. . For this reason, the source / drain regions connected to the channel also have a vertically long shape. On the other hand, an ordinary field-effect transistor has flat source / drain regions in a direction parallel to the substrate plane as shown in the top view of FIG. For this reason, the field-effect transistor shown in FIG. 50 has a significantly different projection pattern onto the substrate surface than a normal pattern, so that a circuit pattern arranged on the assumption of a normal transistor cannot be used. Further, since the surface of the source / drain region is not on a flat surface parallel to the substrate plane, the process for forming the structure of the source / drain and its peripheral portion is performed under the same conditions as when a normal transistor is performed. Can't do it. In the ion implantation process for forming the source / drain, means for introducing impurities into the side surface of the semiconductor, such as oblique ion implantation with a large angle, is required. Further, in order to reduce the parasitic resistance of the source / drain regions, no means has been proposed for epitaxially growing a semiconductor layer on the source / drain regions or for performing a silicidation process. Also, a process of forming silicide on the source / drain region surface in order to reduce the parasitic resistance cannot be performed by a normal procedure.
[0008]
Therefore, even in a vertical field-effect transistor in which the channel surface is substantially perpendicular to the substrate plane, a transistor structure in which the layout pattern is compatible with that of a conventional MOSFET is desired.
[0009]
(Second task)
To increase the channel width in a normal vertical field-effect transistor, it is necessary to increase the height of the semiconductor layer. As a result, there arises a problem that the unevenness of the element becomes large and processing becomes difficult. For example, it becomes difficult to uniformly introduce impurities in the vertical direction of the semiconductor layer. Further, it becomes difficult to keep the gate dimension uniform in the vertical direction of the semiconductor layer. This problem occurs even if the channel width is made simple, if the channel width is simply increased. Further, when the unevenness of the element becomes large, it becomes difficult to make the thickness of the semiconductor layer in which the channel is formed in the substrate plane direction uniform in the vertical direction of the semiconductor layer in which the channel is formed.
[0010]
In a normal transistor, the channel width can be changed by changing the width of an element to be formed. However, in the case of a vertical field effect transistor, it is necessary to change the height of the transistor in order to change the channel width. Therefore, when transistors having different channel widths are mixed in one LSI, transistors having different heights are mixed. In this case, it is necessary to mix different etching conditions and ion implantation conditions according to the channel width when manufacturing the device, and the processing becomes extremely complicated.
[0011]
Therefore, a transistor structure in which the transistor height does not change even when the channel width is increased, the unevenness of the element does not increase, and the transistors having different channel widths coexist is desired.
[0012]
(Third task)
In a normal vertical field effect transistor, the source / drain region is formed in the thin film region, so that the parasitic resistance of the source / drain region increases. Therefore, a vertical field effect transistor structure in which the parasitic resistance of the source / drain region is small is required.
[0013]
[Means for Solving the Problems]
According to the present invention, a plurality of conduction paths made of a semiconductor are arranged on an insulator in a fixed direction, and the source / source is arranged so as to face each other in a direction perpendicular to the arrangement direction of the conduction paths with the plurality of conduction paths interposed therebetween. A drain region is provided, and the two source / drain regions are connected so as to be electrically connected by the plurality of conduction paths, and a region including at least a central portion of the semiconductor layer forming each of the conduction paths is provided via an insulating film. A gate electrode is provided, and a region where the gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conductive paths forms a channel forming region, and the gate electrode is formed of at least the plurality of conductive layers. The conductive paths are provided along the direction in which the conductive paths are arranged so as to straddle the central portion of the paths. In each of the conductive paths, both side surfaces of the semiconductor layer forming the conductive paths are main conductive paths. I and,
The plurality of conduction paths are formed of semiconductor layer portions separated from each other by openings arranged in a predetermined direction in the semiconductor layer on the insulator,
The width of each of the openings in the arrangement direction is smaller at a position closer to the source / drain region than at a position substantially equidistant from the two source / drain regions.And a field-effect transistor.
[0021]
Further, according to the present invention, as the distance from the position where the gate electrode is arranged, the width of each of the openings in the arrangement direction has a constant slope and becomes narrower, and the shape of the projection of each of the openings on the substrate plane is reduced. The present invention relates to the field-effect transistor of the present invention, which is provided at least in part.
[0022]
The present invention also relates to the field-effect transistor according to the present invention, wherein the shape of each of the openings projected onto the plane of the substrate forms an arc at a position adjacent to the source / drain region.
[0023]
The present invention also relates to the field-effect transistor of the present invention, wherein each of the openings has a circular shape projected onto a substrate plane.
[0024]
Also, in the present invention, the projected shape of each of the openings on the plane of the substrate is substantially square, and is inclined by approximately 45 degrees with respect to the arrangement direction of the openings. Type transistor.
[0025]
Further, according to the present invention, in a cross section perpendicular to a conduction direction connecting the two source / drain regions and covered with a gate electrode, the height of the semiconductor layer forming each of the conduction paths is equal to the width of the semiconductor layer. The field effect transistor according to the present invention, which is the same as or larger than the above.
Further, according to the present invention, in a portion where a gate electrode is provided via an insulating film in a region including at least a central portion of the semiconductor layer forming each of the conductive paths, an upper portion of the semiconductor layer forming a conductive path is provided. An insulating film having a thickness greater than the thickness of the insulating film formed on both side surfaces of the semiconductor layer, and a gate electrode disposed above the thick insulating film; About.
Further, according to the present invention, in a portion where a gate electrode is provided via an insulating film in a region including at least a central portion of the semiconductor layer forming each of the conductive paths, an upper portion of the semiconductor layer forming a conductive path is provided. The present invention relates to the field effect transistor of the present invention, wherein a multilayer insulating film is provided, and a gate electrode is provided on the insulating film.
Further, according to the present invention, at least a part of the thick insulating film formed on the semiconductor layer forming each of the conduction paths is formed of Si. _Three N _Four The invention relates to the field effect transistor of the present invention, which is constituted by a film.
Further, according to the present invention, the insulator under the gate electrode is dug down, and the lower surface of the gate electrode on the dug down insulator is located below the lower surface of each semiconductor layer forming the conduction path. The present invention relates to a field-effect transistor of the present invention.
[0026]
Also, the present inventionA plurality of semiconductor conduction paths are arranged on the insulator in a predetermined direction, and source / drain regions are provided so as to face each other in a direction perpendicular to the arrangement direction of the conduction paths with the plurality of conduction paths interposed therebetween. The two source / drain regions are connected so as to be electrically connected by the plurality of conductive paths, and a gate electrode is formed via an insulating film in a region including at least a central portion of the semiconductor layer forming each of the conductive paths. A region in which a gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conductive paths forms a channel forming region, and the gate electrode is at least a central portion of the plurality of conductive paths. Are provided along the direction of arrangement of the conduction paths so that both sides of the semiconductor layer forming the conduction paths are the main conduction paths in each of the conduction paths. With aA method for manufacturing a field effect transistor, comprising:
Forming a semiconductor layer on an insulator, providing at least one insulating mask film on the semiconductor layer, and forming an opening pattern in which openings are arranged in a predetermined direction in the mask film;Surround multiple arranged openingsPatterning the mask film so that a region remains; and patterning the semiconductor layer using the patterned mask film as a mask to form a semiconductor layer forming the conduction path and the source / drain regions. The present invention relates to a method for manufacturing a field-effect transistor, which is a feature of the present invention.
[0027]
Also, in the present invention, the opening pattern is a pattern in which extra openings are arranged at both ends in the opening arrangement direction, and in the step of patterning the mask film, the opening pattern is patterned so that the extra openings of the opening pattern do not remain. The present invention also relates to a method of manufacturing the above-described field-effect transistor of the present invention.
[0028]
Also, the present inventionA plurality of semiconductor conduction paths are arranged on the insulator in a predetermined direction, and source / drain regions are provided so as to face each other in a direction perpendicular to the arrangement direction of the conduction paths with the plurality of conduction paths interposed therebetween. The two source / drain regions are connected so as to be electrically connected by the plurality of conductive paths, and a gate electrode is formed via an insulating film in a region including at least a central portion of the semiconductor layer forming each of the conductive paths. A region in which a gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conductive paths forms a channel forming region, and the gate electrode is at least a central portion of the plurality of conductive paths. Are provided along the direction of arrangement of the conduction paths so that both sides of the semiconductor layer forming the conduction paths are the main conduction paths in each of the conduction paths. With aA method for manufacturing a field effect transistor, comprising:
Forming a semiconductor layer on an insulator, providing at least one insulating mask film on the semiconductor layer, and depositing a second mask material on the mask film; Processing the second mask material into a rectangular shape to be arranged,ArrangeSecond mask materialEach of the two ends of the side perpendicular to the arrangement direction of the second mask material on the plane of projection onto the substrateOne endDepartmentCover certain areas including, Two extending in the arrangement direction of the second mask materialProviding a resist pattern, selectively etching both the resist pattern and the second mask material and exposing the exposed mask film so that the openings have an opening pattern arranged in a certain direction. Patterning a mask film; and patterning the semiconductor layer using the patterned mask film as a mask to form a semiconductor layer forming the conduction path and the source / drain region. And a method for manufacturing a type transistor.
[0029]
Also, the present inventionA plurality of semiconductor conduction paths are arranged on the insulator in a predetermined direction, and source / drain regions are provided so as to face each other in a direction perpendicular to the arrangement direction of the conduction paths with the plurality of conduction paths interposed therebetween. The two source / drain regions are connected so as to be electrically connected by the plurality of conductive paths, and a gate electrode is formed via an insulating film in a region including at least a central portion of the semiconductor layer forming each of the conductive paths. A region in which a gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conductive paths forms a channel forming region, and the gate electrode is at least a central portion of the plurality of conductive paths. Are provided along the direction of arrangement of the conduction paths so that both sides of the semiconductor layer forming the conduction paths are the main conduction paths in each of the conduction paths. With aA method for manufacturing a field effect transistor, comprising:
Forming a semiconductor layer on an insulator, providing at least one kind of insulating mask film on the semiconductor layer, and providing a mask forming dummy pattern arranged on the mask film at a constant interval on the mask film; Depositing a second mask material on the mask forming dummy pattern and etching back the second mask material to form sidewalls of the second mask material around the mask forming dummy pattern, Removing the mask-forming dummy pattern to leave the sidewall on the mask film; and forming the sidewall.ArrangeSecond mask materialEach of the two ends of the side perpendicular to the arrangement direction of the second mask material on the plane of projection onto the substrateOne endDepartmentCover certain areas including, Two extending in the arrangement direction of the second mask materialProviding a resist pattern, selectively etching both the resist pattern and the second mask material and exposing the exposed mask film so that the openings have an opening pattern arranged in a certain direction. Patterning a mask film; and patterning the semiconductor layer using the patterned mask film as a mask to form a semiconductor layer forming the conduction path and the source / drain region. And a method for manufacturing a type transistor.
Further, according to the present invention, a plurality of conductive paths made of a semiconductor are arranged on an insulator in a fixed direction, and the source is arranged so as to face each other in a direction perpendicular to the arrangement direction of the conductive paths with the plurality of conductive paths interposed therebetween. / Drain regions are provided, these two source / drain regions are connected to be conductive by the plurality of conduction paths, and an insulating film is formed in a region including at least a central portion of the semiconductor layer forming each of the conduction paths. A gate electrode is provided through the semiconductor layer, and a region where the gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conduction paths forms a channel formation region, and the gate electrode includes at least the plurality of gate electrodes. The conductive paths are provided along the direction of arrangement of the conductive paths so as to straddle the center of the conductive paths. In each of the conductive paths, both side surfaces of the semiconductor layer forming the conductive path are the main conductive paths. Become a route,
A width of a semiconductor layer forming each conduction path in a direction parallel to a substrate surface in a cross section perpendicular to a conduction direction connecting the two source / drain regions is substantially equidistant from the two source / drain regions. The present invention relates to a field-effect transistor characterized in that the width of a position near a source / drain region is larger than the width of a position.
Further, according to the present invention, a plurality of conductive paths made of a semiconductor are arranged on an insulator in a fixed direction, and the source is arranged so as to face each other in a direction perpendicular to the arrangement direction of the conductive paths with the plurality of conductive paths interposed therebetween. / Drain regions are provided, these two source / drain regions are connected to be conductive by the plurality of conduction paths, and an insulating film is formed in a region including at least a central portion of the semiconductor layer forming each of the conduction paths. A gate electrode is provided through the semiconductor layer, and a region where the gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conduction paths forms a channel formation region, and the gate electrode includes at least the plurality of gate electrodes. The conductive paths are provided along the direction of arrangement of the conductive paths so as to straddle the center of the conductive paths. In each of the conductive paths, both side surfaces of the semiconductor layer forming the conductive path are the main conductive paths. Become a route,
The width in the direction parallel to the substrate surface of the semiconductor layer forming each conduction path in a cross section perpendicular to the conduction direction connecting the two source / drain regions is constant at a position covered by the gate electrode. At a position closer to the source / drain region than the gate electrode. A field-effect transistor having a structure that is larger than a width at a position covered by a gate electrode.
Further, according to the present invention, a plurality of conductive paths made of a semiconductor are arranged on an insulator in a fixed direction, and the source is arranged so as to face each other in a direction perpendicular to the arrangement direction of the conductive paths with the plurality of conductive paths interposed therebetween. / Drain regions are provided, these two source / drain regions are connected to be conductive by the plurality of conduction paths, and an insulating film is formed in a region including at least a central portion of the semiconductor layer forming each of the conduction paths. A gate electrode is provided through the semiconductor layer, and a region where the gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conduction paths forms a channel formation region, and the gate electrode includes at least the plurality of gate electrodes. The conductive paths are provided along the direction of arrangement of the conductive paths so as to straddle the center of the conductive paths. In each of the conductive paths, both side surfaces of the semiconductor layer forming the conductive path are the main conductive paths. Become a route,
The plurality of conductive paths are formed of semiconductor layer portions separated from each other by openings arranged in a predetermined direction in the semiconductor layer on the insulator,
The present invention relates to a field-effect transistor, wherein the conduction path and the source / drain region are made of a material integrally formed.
Further, according to the present invention, a plurality of conductive paths made of a semiconductor are arranged on an insulator in a fixed direction, and the source is arranged so as to face each other in a direction perpendicular to the arrangement direction of the conductive paths with the plurality of conductive paths interposed therebetween. / Drain regions are provided, these two source / drain regions are connected to be conductive by the plurality of conduction paths, and an insulating film is formed in a region including at least a central portion of the semiconductor layer forming each of the conduction paths. A gate electrode is provided through the semiconductor layer, and a region where the gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conduction paths forms a channel formation region, and the gate electrode includes at least the plurality of gate electrodes. The conductive paths are provided along the direction of arrangement of the conductive paths so as to straddle the center of the conductive paths. In each of the conductive paths, both side surfaces of the semiconductor layer forming the conductive path are the main conductive paths. Become a route,
The plurality of conductive paths are formed of semiconductor layer portions separated from each other by openings arranged in a predetermined direction in the semiconductor layer on the insulator,
The present invention relates to a field-effect transistor, in which a part of the opening which is in contact with a source / drain region is not covered with a gate electrode.
Further, according to the present invention, a plurality of conductive paths made of a semiconductor are arranged on an insulator in a fixed direction, and the source is arranged so as to face each other in a direction perpendicular to the arrangement direction of the conductive paths with the plurality of conductive paths interposed therebetween. / Drain regions are provided, these two source / drain regions are connected to be conductive by the plurality of conduction paths, and an insulating film is formed in a region including at least a central portion of the semiconductor layer forming each of the conduction paths. A gate electrode is provided through the semiconductor layer, and a region where the gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conduction paths forms a channel formation region, and the gate electrode includes at least the plurality of gate electrodes. The conductive paths are provided along the direction of arrangement of the conductive paths so as to straddle the center of the conductive paths. In each of the conductive paths, both side surfaces of the semiconductor layer forming the conductive path are the main conductive paths. Becomes a path, the plurality of conductive paths, a method of manufacturing a field-effect transistor made of a semiconductor layer portions separated from each other by an opening which is arranged and formed in a predetermined direction to the semiconductor layer on the insulator,
Providing a plurality of conductive paths connected to a common semiconductor region between the conductive paths and providing openings arranged in a single direction in a single semiconductor layer at positions where the conductive paths are separated from each other; And a method for manufacturing a field effect transistor.
Also, in the present invention, the width of each of the openings in the arrangement direction may be such that, in a portion adjacent to a position where the source / drain region is formed, each of the openings has a predetermined distance from the source / drain region. And a width in the arrangement direction of the field-effect transistor according to the present invention.
The present invention also relates to the method of manufacturing a field effect transistor according to the present invention, wherein the width of each of the openings in the arrangement direction is formed so as to be constant in a portion covered with the gate electrode.
[0030]
The present invention also provides a gate electrode or a dummy gate electrode that straddles a plurality of semiconductor layer portions separated from each other by an opening in a direction in which the openings formed in the semiconductor layer in the step of patterning the semiconductor layer are arranged. And a method of manufacturing the field-effect transistor according to the present invention.
[0031]
Further, according to the present invention, the impurity is introduced into the semiconductor layer portion forming the conduction path by depositing a material containing a high-concentration impurity on an inner wall of each opening formed in the semiconductor layer in the step of patterning the semiconductor layer. And a method of manufacturing the field-effect transistor according to the present invention, wherein the impurity is diffused from the material containing the high-concentration impurity into the semiconductor layer portion by heat treatment.
[0032]
Further, the present invention relates to the above-mentioned method for producing a field-effect transistor according to the present invention, wherein the insulator exposed in each opening formed in the step of patterning a semiconductor layer is etched to a predetermined depth. .
[0033]
Further, according to the present invention, the field effect transistor according to the present invention is characterized in that hydrogen annealing is performed on a side surface of the semiconductor layer exposed in each opening formed in the step of patterning the semiconductor layer. About the method.
[0034]
Further, according to the present invention, the side surface of the semiconductor layer exposed in each of the openings formed in the step of patterning the semiconductor layer is formed by SiO 2₂The present invention relates to the method for manufacturing a field-effect transistor according to the present invention, wherein the method is covered with a film and heat-treated at a temperature of 1200 ° C. or more for 1 hour or more.
[0035]
Further, according to the present invention, the side surface of the semiconductor layer exposed in each opening formed in the step of patterning the semiconductor layer is covered with an insulating film, and a laser beam, the side surface of the semiconductor layer covered with the insulating film, or The present invention relates to the method for manufacturing a field effect transistor according to the present invention, wherein the semiconductor layer forming the conduction path is melted, and the melted region is recrystallized.
[0036]
Further, according to the present invention, the side surface of the semiconductor layer exposed in each opening formed in the step of patterning the semiconductor layer is covered with an insulating film, and an electron beam is used to cover the side surface of the semiconductor layer covered with the insulating film, or The present invention relates to the method for manufacturing a field effect transistor according to the present invention, wherein the semiconductor layer forming the conduction path is melted, and the melted region is recrystallized.
[0037]
Further, according to the present invention, the side surface of the semiconductor layer exposed in each opening formed in the step of patterning the semiconductor layer is covered with an insulating film, and an electric heater is used to cover the side surface of the semiconductor layer covered with the insulating film, or The present invention relates to the method for manufacturing a field effect transistor according to the present invention, wherein the semiconductor layer forming the conduction path is melted, and the melted region is recrystallized.
Further, according to the present invention, a plurality of conductive paths made of a semiconductor are arranged on an insulator in a fixed direction, and the source is arranged so as to face each other in a direction perpendicular to the arrangement direction of the conductive paths with the plurality of conductive paths interposed therebetween. / Drain regions are provided, these two source / drain regions are connected to be conductive by the plurality of conduction paths, and an insulating film is formed in a region including at least a central portion of the semiconductor layer forming each of the conduction paths. A gate electrode is provided through the semiconductor layer, and a region where the gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conduction paths forms a channel formation region, and the gate electrode includes at least the plurality of gate electrodes. The conductive paths are provided along the direction of arrangement of the conductive paths so as to straddle the center of the conductive paths. In each of the conductive paths, both side surfaces of the semiconductor layer forming the conductive path are the main conductive paths. A method of manufacturing a field effect transistor having a structure in which a path,
Providing a first mask material on a semiconductor layer provided on the insulator;
Forming a dummy pattern on the first mask material, subsequently depositing a second mask material over the whole, and then etching it back to form sidewalls made of the second mask material around the dummy pattern. And subsequently removing the dummy pattern;
Patterning the first mask material using a side wall made of the second mask material remaining on the first mask material as a mask,
The semiconductor layer is etched using the first mask material and the second mask material remaining on the first mask material as a mask, and a shape in which a plurality of semiconductor conduction paths are arranged in a certain direction. And a method of manufacturing a field-effect transistor.
Further, according to the present invention, a plurality of conductive paths made of a semiconductor are arranged on an insulator in a fixed direction, and the source is arranged so as to face each other in a direction perpendicular to the arrangement direction of the conductive paths with the plurality of conductive paths interposed therebetween. / Drain regions, these two source / drain regions are connected so as to be conductive by the plurality of conduction paths, and an insulating film is formed in a region including at least a central portion of the semiconductor layer forming each of the conduction paths. A gate electrode is provided through the semiconductor layer, and a region where the gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conduction paths forms a channel formation region, and the gate electrode includes at least the plurality of gate electrodes. The conductive paths are provided along the direction of arrangement of the conductive paths so as to straddle the center of the conductive paths. In each of the conductive paths, both side surfaces of the semiconductor layer forming the conductive path are the main conductive paths. Become a route,
A width of a semiconductor layer forming each conduction path in a direction parallel to a substrate surface in a cross section perpendicular to a conduction direction connecting the two source / drain regions is substantially equidistant from the two source / drain regions. The present invention relates to a field-effect transistor characterized in that the width of a position near a source / drain region is larger than the width of a position.
Further, according to the present invention, a conduction path made of a semiconductor is arranged on an insulator, and source / drain regions are provided so as to face each other with the conduction path interposed therebetween. A gate electrode is provided through an insulating film in a region including at least a central portion of the semiconductor layer forming the conduction path, which is connected so as to conduct, and a gate electrode is provided on both side surfaces of the semiconductor layer forming the conduction path via the insulating film. The region where the gate electrode is formed forms a channel forming region, and the gate electrode is provided in a direction perpendicular to a direction connecting source / drain regions so as to straddle at least a central portion of the conduction path, In the conduction path, both side surfaces of the semiconductor layer forming the conduction path are main conduction paths,
The width in the direction parallel to the substrate surface of the semiconductor layer forming each conduction path in a cross section perpendicular to the conduction direction connecting the two source / drain regions is larger than the width at the position covered by the gate electrode. The present invention relates to a field-effect transistor having a structure that is larger at a position closer to a source / drain region than an electrode.
[0038]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
A typical device structure in the present invention will be described. 1 is a bird's-eye view of the device, and FIG. 2 is a top view of the device of FIG. 1 as viewed from directly above. 3 is a cross-sectional view in the A1-A1 'direction in FIGS. 1 and 2, FIG. 4 is a cross-sectional view in the B1-B1' direction, and FIG. 5 is a cross-sectional view in the C1-C1 'direction.
[0039]
As shown in FIG. 1, a buried insulating film 2 is provided on a silicon substrate 1, and a semiconductor layer 3 patterned in an appropriate shape is provided thereon. In the semiconductor layer 3, a row of openings 10 is provided so as to cross the semiconductor layer 3 (FIG. 2). In the opening 10, the semiconductor layer 3 is removed, and the opening reaches the buried insulating film 2. In the opening arrangement region 34, the gate electrode 5 having a long side in the direction in which the openings 10 are arranged is provided on the semiconductor layer 3 and on the buried insulating film 2 exposed in the openings 10. The semiconductor layer located below the gate electrode 5 forms a channel forming region 7 where no impurity is introduced or an impurity is introduced at a low concentration and a channel is formed by applying an appropriate gate voltage. An insulating film (a gate insulating film 6 on both the top and side surfaces in the embodiment of FIG. 1) is provided on the upper surface and the side surface of the semiconductor layer forming the channel forming region 7, and the semiconductor layer forming the channel forming region 7 is located on the upper side via the insulating film. And the side faces the gate electrode 5. Here, at least the insulating film provided on the side surface of the semiconductor layer forming the channel formation region 7 is a gate insulating film, and the film thickness is set to be thin enough to form a channel on the side surface of the semiconductor layer by applying a gate voltage. . The insulating film above the semiconductor layer forming the channel forming region 7 may be a gate insulating film as thin as the side insulating film, or may be provided thicker than the side insulating film. Further, the material of the upper insulating film and the material of the side insulating film may be different.
[0040]
Portions of the semiconductor layer 3 located on both sides of the region 34 in which the openings 10 are arranged form source / drain regions 4 doped with a high concentration of impurities. In a region between the source / drain region 4 and the channel forming region 7, impurities of the same conductivity type as the source / drain 4 are introduced at a high concentration, and the source / drain region 4 and the channel forming region 7 are connected. The drain connection part 32 is formed. The source / drain region 4 of this embodiment has a role of connecting a wiring via the source / drain contact 16 (FIGS. 35 to 37). The source / drain connecting portion 32 connects the source / drain region 4 and the channel forming region 7 and also has a thickness (a width of a semiconductor layer forming a conduction path) of a portion connecting the high impurity concentration portion and the channel forming region. By reducing the equivalent, or equivalent to the junction depth of a normal field-effect transistor, it has the effect of suppressing the short-channel effect (variation in various characteristics such as threshold voltage due to miniaturization of the transistor).
[0041]
It is noted that the combined portion of the source / drain region 4 and the source / drain connection portion 32 in the transistor has a function of the source / drain region in a normal single drain field effect transistor. For a field effect transistor having a source / drain extension that extends shallowly from the source / drain region to the channel formation region, the source / drain connection 32 of the present embodiment corresponds to the source / drain extension.
[0042]
Although not shown in FIG. 1, various insulators are buried in the openings 10 not covered with the gate electrode 5 in various insulating film deposition steps until the transistor is completed. However, it is not necessary that the inside of the opening 10 is completely filled with the insulator, and a part of the cavity in which the insulator is not embedded may remain.
[0043]
Note that, in FIG. 1, the gate insulating film 6 is not drawn for easy understanding of the drawing.
[0044]
The dimensions of each part are as follows, for example. The thickness of the buried insulating film 2 is, for example, 100 nm. The thickness (height in FIG. 1) of the semiconductor layer 3 is, for example, 120 nm. The width of the opening 10 in the direction in which the openings are arranged (A1-A1 'direction) is 100 nm, and the width of the opening in the direction perpendicular to the direction in which the openings are arranged (C1-C1' direction) is 300 nm. . The width of the semiconductor layer sandwiched between the two openings is 50 nm. At both ends of the opening arrangement region 34, cutouts having a size approximately half the size of the opening are provided in the semiconductor layer. The gate insulating film has a combination of a material and a thickness suitable for suppressing a short channel effect in a transistor to be formed. The material of the gate insulating film is SiO₂, A typical thickness is 1.5-4 nm.
[0045]
However, the thickness of the buried insulating film 2 is not particularly limited. In general, a SIMOX wafer (an SOI substrate manufactured by implanting oxygen into a silicon substrate) has a buried insulating layer having a thickness of about 100 nm to 400 nm, and is manufactured by bonding two bonded silicon substrates via an insulating film. In the case of an SOI wafer, it is generally about 1 to 3 μm.(Registered trademark)Some bonded wafers using a technology (a technology for separating a thin film silicon layer by forming porous silicon) have a thickness of about 50 nm. Generally, in a logic circuit, it is desirable to set the thickness to 150 nm or less so that heat can easily escape through the buried insulating layer. However, the effect of the present invention is not affected by the thickness of the buried insulating layer. Has no restrictions.
[0046]
The width of the semiconductor layer sandwiched between the two openings 10 is desirably about the same as or smaller than the gate length from the viewpoint of suppressing the short channel effect, and is preferably half or less of the gate length. This is particularly desirable from the viewpoint of suppressing the channel effect. Although the gate length is not particularly limited, a typical gate length assumed for the field-effect transistor to which the present invention is applied is in a range from 10 nm to 0.25 μm. The relationship between the width and the height of the semiconductor layer will be described later in detail with reference to FIG.
[0047]
The material of each part is as follows. The buried insulating film 2 may be an insulator.₂And SiO₂Besides, for example, Si₃N₄Alternatively, an insulator made of AlN, alumina, other metal oxides, an insulator made of an organic material, or the like may be used. Alternatively, the buried insulating film 2 may be replaced with a cavity, and a transistor having a buried insulating layer made of a cavity may be formed. In order to enjoy the effects of the present invention, the material of the semiconductor layer 3 is not particularly limited, but single crystal silicon is most preferable from the viewpoint of compatibility with a normal LSI process. The material of the gate electrode 5 may be a conductor having a material having a required work function and conductivity. For example, n⁺Type or p⁺Mold of polysilicon, n⁺Type or p⁺Type polycrystalline SiGe mixed crystal, n⁺Type or p⁺Type polycrystalline Ge, n⁺Type or p⁺Semiconductors such as polycrystalline SiC, metals such as Mo, W and Ta, metal nitrides such as TiN and WN, and silicide compounds such as platinum silicide and erbium silicide.
[0048]
In the figures, the gate length (the dimension of the gate electrode in the direction connecting two source / drain regions to be formed later; the dimensions in the B1-B1 'direction and the C1-C1' direction in FIGS. 1, 2 and 4 are equivalent). Is set so as not to fill the opening. For example, it is set to 150 nm. However, if the source / drain regions are provided so as to reach both ends of the opening 10, the gate electrode may completely cover the opening.
[0049]
A low-concentration impurity may be introduced into the semiconductor layer forming the channel formation region, or no impurity may be introduced at all. The impurities are, for example, boron, phosphorus and arsenic, and the concentration thereof is 10¹⁹cm^-3Is less than. In order to obtain a fully depleted operation with excellent device characteristics, the concentration should be 10¹⁸cm^-3It is desirable to be less than. When a material whose work function is suitable for controlling the threshold value is selected as a material of the gate electrode (metal such as Mo, W, Ta, metal nitride such as TiN, WN, platinum silicide, erbium silicide, SiGe Do not need to introduce impurities, and even if¹⁸cm^-3Less than is good. In addition, the impurity concentration is set to a low concentration until the depletion layers extending from the channels on both side surfaces to the center of the semiconductor layer at least contact the gate electrode with a threshold voltage applied thereto, and the operating characteristics are improved. An excellent complete depletion operation can be achieved, and the effect of suppressing the short channel effect caused by the double gate structure can be enjoyed.
[0050]
Impurities having the same conductivity type as the channel conductivity type are introduced into the source / drain regions 4 at a high concentration. In the case of an n-channel transistor, an n-type impurity such as phosphorus or arsenic is introduced, and in the case of a p-channel transistor, a p-type impurity such as boron is introduced. The impurity concentration introduced into the source / drain regions is 10¹⁹cm^-3That is typically 5 × 10¹⁹cm^-3~ 5 × 10²⁰cm^-3It is.
[0051]
Since the potential of the channel formation region of this transistor is controlled by the gate electrodes provided on both side surfaces of the semiconductor layer forming the channel formation region, the controllability with respect to the potential of the channel formation region is high, and the short channel effect is suppressed. The characteristics of the element are improved. In addition, due to the electric field from the gate electrodes disposed on both sides of the semiconductor layer, the width of the semiconductor layer (see FIG. 4) is larger than the sum of the widths of two depletion layers formed from both sides of the semiconductor layer toward the inside of the semiconductor layer. 3 W₃), The element can be operated in a fully depleted mode, so that the subthreshold characteristic (the degree to which the transistor turns off sharply when a gate voltage lower than the threshold voltage is applied) is improved, and the substrate floating effect is improved. (Abnormal operation due to accumulation of excess carriers in the semiconductor layer) is suppressed.
[0052]
When the insulating film on the semiconductor layer forming the channel forming region 7 is thin and a channel is formed on the semiconductor layer, the height of the semiconductor layer (h in FIG. 3)₃) And the width of the semiconductor layer (W in FIG. 3)₃), The sum of the channel widths on both sides (vertical direction in the cross section in FIG. 3) is twice the width of the channel formed on the upper surface of the semiconductor (horizontal direction in the cross section in FIG. 3). Height of semiconductor layer h₃Is the width W of the semiconductor layer₃If it is larger, the sum of the channel widths on both side surfaces (vertical direction in the cross section in FIG. 3) is twice or more the width of the channel formed on the upper surface of the semiconductor layer (horizontal direction in the cross section in FIG. 3). Can be the dominant channel. Accordingly, the height h of the semiconductor layer forming the channel formation region₃And the width W of the same semiconductor layer₃Or the height h of the same semiconductor layer₃Is the width W of the semiconductor layer.₃It is desirable to make it larger.
[0053]
Equivalent thickness (the equivalent thickness is obtained by dividing the thickness of the insulating film by the relative dielectric constant of the insulating film, and calculating the quotient obtained by dividing the thickness by a relative dielectric constant of the insulating film). SiO₂Is multiplied by the relative permittivity of In the case where an insulating film having a large size is provided above the semiconductor layer forming the channel forming region 7 and carriers forming the channel are not induced on the upper surface, the channel is formed only on both side surfaces of the semiconductor layer forming the channel forming region 7. Is done. In this case, the channel width per conduction path (35) is twice the height of the semiconductor layer forming the channel formation region 7.
[0054]
Here, the appropriate height h of the semiconductor layer forming the channel formation region 7₃Will be described with reference to FIG. In a cross section in which the channel forming region 7 and the openings 10 are periodically arranged, one cycle divided by a chain line is considered. Assuming that the channel width on one side surface is W, the sum of the channel widths is 2 W in a structure having one period. On the other hand, the width of the semiconductor layer forming the channel formation region 7 in FIG._si(W in FIG. 3₃), The width of the opening 10 separating the channel formation region 7 is W_spThen, the width of one cycle is W_si+ W_spIt becomes. The channel width obtained when a normal transistor (for example, the structure shown in FIG. 52) is formed in the same region is W_si+ W_spTherefore, in order to realize a channel width larger than that of a normal transistor in the transistor of the present invention, 2W> W_si+ W_spWhat is necessary is just to satisfy the condition. If both sides are divided by 2, W> (W_si+ W_sp) / 2. That is, W is W_siAnd W_spShould be larger than the average. Channel width W on one side surface and height h of channel forming region 7_SiAre considered to be the same, so that the height h of the semiconductor layer forming the channel formation region 7 is_Si(H₃) Is the width W of the semiconductor layer forming the channel formation region 7._siAnd opening 10 width W_spIt can be said that it is better if it is larger than the average. Here, as a typical example, the width W of the semiconductor layer forming the channel formation region 7 is shown._siAnd opening 10 width W_spAre the same, the average of both is W_siAnd the height h of the semiconductor layer forming the channel formation region 7_SiIs the width W of the channel forming region 7_siIt is concluded that larger is better. W_siAnd W_spAre not necessarily equal, but W_si= W_spH_Si> W_SiIs adopted as a guideline for designing a transistor, the above condition W> (W_si+ W_sp) / 2, at least a transistor that does not deviate significantly is obtained.
[0055]
Further, as another typical structure, when the width of the semiconductor layer forming the channel formation region 7 is smaller than the width of the opening, W_si<W_spSo h₃> W_spIs satisfied, the above condition W> (W_si+ W_sp) / 2 can always be satisfied.
[0056]
In addition, this field effect transistor has a source / drain shape and a gate electrode shape of a substrate, although the channel is formed on a side surface of a semiconductor layer substantially perpendicular to the substrate plane as a main conduction path. The shape when projected onto the surface (FIG. 2) is the same as that of a normal field-effect transistor (FIG. 52). Also, the shape of the element region 15 is the same as that of a normal field-effect transistor except for the arrangement of openings crossing the center. That is, the channel formation region and the source / drain connection portion 32 have a vertical structure, but the shape of the source / drain region is the same as that of a normal field effect transistor except for the periphery of the opening. Therefore, the contact 16 for the source / drain region and the contact 17 for the gate electrode can be manufactured by the same pattern (FIG. 35) and the same steps as those of a normal field-effect transistor (FIG. 52). Also, the source / drain regions are the same as ordinary field-effect transistors except for the periphery of the opening 10. Therefore, the source / drain regions are formed for forming source / drain regions, silicidation, or lowering the resistance. In the step of epitaxially growing a semiconductor layer thereon, a step similar to that for a conventional field-effect transistor or a step similar to that for a conventional SOI field-effect transistor can be used. Therefore, except for adding an opening arrangement portion, almost the same pattern as that of a normal transistor can be used, and the formation of the opening and the processing around the opening (for example, processing of the gate electrode) are excluded. In a process (for example, formation of a contact to a gate and a source / drain), a feature is that the same process as that for a conventional field-effect transistor can be used. Therefore, the first problem can be solved.
[0057]
Further, the channel portion has a structure in which vertical transistors having a fixed height (typically 200 nm or less, preferably 120 nm or less, more preferably 60 nm or less) are connected in parallel, and the channel width is set to each conduction path. Therefore, even in a transistor having a large channel width, the height of the channel formation region is kept constant. In the case where transistors having different channel widths are mixed in a circuit, the number of conductive paths to be arranged may be simply changed, so that there is no need to change the height of the transistor, and there is no variation in the height of the transistor. In addition, since the height of the transistor can be kept at a certain value or less, even when impurities are introduced from above the semiconductor by impurity introduction means such as ion implantation, the impurity concentration is kept in the vertical direction perpendicular to the substrate plane of the semiconductor layer. Good uniformity. In addition, the uniformity of the gate dimension (particularly, the length in the direction connecting the two sources / drains, that is, the gate length) is good in the vertical direction of the semiconductor layer. Further, the thickness of the semiconductor layer in the substrate plane direction is excellent in the vertical direction. Therefore, the second problem can be solved. The uniformity of the impurity concentration in the vertical direction perpendicular to the substrate plane of the semiconductor layer, the gate dimension, and the thickness of the semiconductor layer in the substrate plane direction described above are improved as the semiconductor layer is thinner (the semiconductor in the channel portion is improved). Layer height h_siIs preferably 120 nm or less, more preferably 60 nm or less.
[0058]
In this field-effect transistor, gate electrodes are provided on both side surfaces of a semiconductor layer forming a channel formation region, so that a structure called a double gate structure is formed. This is a structure in which two gate electrodes are provided with a thin-film (typically 50 nm or less) semiconductor layer interposed therebetween. For example, Sekikawa, T. Sekikawa, Solid-State Electronics, Vol. 27, p. 827 (1984). 27, pp. 827, 1984), and by Tanaka in 1991, IEDM, Technical Digest, pp. 683-686 (T. Tanaka, 1991 IEEE, IEDM, pp. 683-686). ing. Sekikawa and Tanaka report that by employing a structure in which gate electrodes are formed above and below a semiconductor layer parallel to the substrate plane, the short channel effect is suppressed. However, a problem with this structure is that, in a structure in which gate electrodes are provided above and below a semiconductor layer, upper and lower gate electrodes cannot be formed simultaneously. For this reason, the position of the upper and lower gates cannot be determined in a self-aligned manner, and the position of the upper and lower gates is shifted, or the size of the upper and lower gates (particularly, the gate length, that is, the size of the gate in the direction connecting the source and the drain) is reduced. There is a problem that they cannot be aligned. The structure of the present embodiment realizes a double gate structure by providing gate electrodes on both side surfaces of the semiconductor layer, can suppress a short channel effect, and can easily form gate electrodes on both side surfaces simultaneously (for example, The displacement of the gates on both sides and the difference in dimensions can be greatly reduced as compared with the prior art.
[0059]
Next, an example in which the structure is partially changed in the first embodiment will be described. The top view of FIG. 6 shows an example in which the opening provided in the semiconductor layer is circular. FIG. 7 shows a structure in which notches are not provided in the semiconductor layer at both ends of the opening arrangement region 34. 6 and 7, the outline of the opening originally hidden under the gate electrode is also shown in order to facilitate understanding of the positional relationship between the gate electrode 5 and the opening 10.
[0060]
FIG. 8 shows that when the opening 10 is provided in the semiconductor layer 3, the buried insulating layer 2 is dug down to a certain depth in the opening, and the lower end of the gate electrode 5 reaches a position slightly lower than the lower end of the semiconductor layer 3. Structure. When the lower edge of the gate electrode is aligned with the lower edge of the semiconductor layer, or when the lower edge of the gate electrode is located above the lower edge of the semiconductor layer, the lower edge of the semiconductor layer or the lower corner of the semiconductor layer (these are respectively It is relatively difficult to sufficiently control the potential of the element region end and the corner of the element region end of a normal field-effect transistor by the gate electrode, and a leakage current easily flows between the source and the drain. On the other hand, when the lower end of the gate electrode 7 reaches a position slightly lower than the lower end of the semiconductor layer 3 as shown in FIG. 8, the leakage current near the lower end of the semiconductor layer can be easily suppressed. Further, as shown in the cross-sectional view of FIG. 26, the buried insulating layer 2 is subjected to taper etching to form a shape in which the side surface of the buried oxide film has a slope below the lower end of the semiconductor layer 3. Is also good. In the structure of FIG. 26 as well, since the lower end of the gate electrode is lower than the lower end of the semiconductor layer, controllability of the gate electrode with respect to the potential at the lower end of the semiconductor layer can be improved. 8 and 26 show the case where the gate insulating film 6 having the same thickness is provided on both the side surface and the upper surface of the semiconductor layer forming the channel formation region 7, but the material of the insulating film on the upper surface and the side surface is different. The present invention may be applied to different cases, or to the case where the upper surface insulating film is thicker than the side surface insulating film.
[0061]
Although the case where the silicon substrate 1 serving as the supporting substrate is provided under the insulator (buried oxide film 2) below the semiconductor layer has been described here, the present invention provides a method in which the silicon substrate 1 is formed under a semiconductor forming a field-effect transistor. Applicable if there is an insulator. For example, the present invention can be applied to a structure in which an insulator itself under a semiconductor layer serves as a support substrate, such as an SOS structure (silicon-on-sapphire) in which a semiconductor is provided on a sapphire substrate. Further, the material of the support substrate may not be silicon, but may be an insulator such as quartz or AlN. This structure can be formed, for example, by transferring single-crystal silicon to be the semiconductor layer 3 onto an insulator such as quartz or AlN by a general laminating step and a thinning step used for manufacturing an SOI substrate.
[0062]
In the case where one of the source / drain regions is exclusively used as a source and the other is exclusively used as a drain, as in a CMOS-structured inverter, NAND gate, NOR gate, etc., in this specification, both are simply referred to. Called source / drain.
[0063]
(Embodiment 2)
Some modifications of the transistor of Embodiment 1 will be described with respect to the three arrangements of the channel forming region 7, the opening 10 provided in the semiconductor layer, and the source / drain region 4. FIGS. 27 to 34 are top views of the field-effect transistor viewed from the same position as FIGS. 2, 6, and 7, and particularly, the left end is enlarged. In any of the element structures shown in FIGS. 27 to 34, the openings 10 are arranged so as to cross the semiconductor layer 3 and the gate electrode 5 is provided so as to straddle the semiconductor layer 3 along the direction in which the openings are arranged. The semiconductor layer 3 is provided with a source / drain region 4 into which a high concentration of conductive impurities is introduced, with the gate electrode 5 and the opening 10 interposed therebetween. The semiconductor layer 3 under the gate electrode forms a channel forming region 7 having a low impurity concentration, and a channel is mainly formed on a side surface of the semiconductor layer forming the channel forming region 7. 27 to 34, the outline of the opening originally hidden under the gate electrode is also shown in order to facilitate understanding of the positional relationship between the gate electrode 5 and the opening 10. Also, the gate insulating film 6 is omitted for easy understanding of the drawing. Actually, the gate insulating film 6 is provided on the side surface of the semiconductor layer forming the channel forming region 7, and the side surface of the semiconductor layer forming the channel forming region 7 faces the gate electrode 5 via the gate insulating film 6. Further, on the upper surface of the semiconductor layer forming the channel formation region 7, the gate insulating film 6 or an insulating film having an equivalent thickness larger than that of the gate insulating film (for example, the pad oxide film 8 of FIG.₃N₄(Combined film 9).
[0064]
Between the two source / drain regions 4, there is provided a conduction path arrangement region 31 in which a plurality of conduction paths 33, which are semiconductor regions connecting the two source / drain regions, are provided. This is the same in the transistors whose structures are shown in FIGS. 1 to 8 and FIG. 35, and in the element structures described in the third embodiment and thereafter. The hatched portions in FIG. 27 clearly indicate one of the conduction paths 33. The conduction path 33 includes the channel forming region 7 and the source / drain connection portion 32 which is a high impurity concentration region in the conduction path. The channel forming region 7 is a region located below the gate electrode and having a low impurity concentration (or no impurity is introduced). The source / drain connection portion 32 in the conduction path is located between the channel forming region 7 and the source / drain region 4 and is a region in which impurities of the same conductivity type as the source / drain region are introduced at a high concentration. When a part of the source / drain connection part 32 or a part of the source / drain region 4 is located below the gate electrode 5, the part between the gate electrode 5 and the source / drain connection part 32, An insulating layer is provided between the source / drain 4. The thickness of this insulating layer may be about the same as the gate insulating film, or may be thicker than the gate insulating film.
[0065]
In addition, the form of the conduction path 33 may be such that both the channel forming region 7 and the high impurity concentration region (source / drain connection portion 32) in the conduction path are arranged below the gate electrode (FIG. 28). . Further, in addition to the channel formation region 7 and the source / drain connection portion 32, a part of the source / drain region may be located below the gate electrode (FIG. 28). Alternatively, the channel forming region 7 and the source / drain region 4 may be directly connected without having the source / drain connecting portion 32 in the conduction path 33 (FIG. 29). FIGS. 27 to 29 show the case where the projection shape of the opening 10 on the substrate plane draws a curve at least in the vicinity of the source / drain region. However, as shown in FIGS. May be a polygon such as a hexagon or an octagon. Further, as shown in FIGS. 46 to 49, a substantially square quadrangle which is inclined with respect to the extension direction of the gate electrode (same as the direction in which the openings are arranged) may be used. Further, as shown in FIGS. 33 and 34, the width of the opening may be reduced in a certain range on the source / drain region side.
[0066]
In the embodiments shown in FIGS. 27 to 31, 33, 34 and 46 to 49, in each case, the arrangement direction of the openings (perpendicular to the direction connecting the source / drain, Width W of opening (direction parallel to surface)_spIs the value at the center of the opening (position equidistant from the two sources / drains) (W in FIG. 27)._sp1) Near the source / drain region (for example, W in FIG. 27)._sp2). Conversely, the width W of the semiconductor layer 3 forming the conduction path 33_siIs the value at the center of the channel formation region (position equidistant from the two sources / drains) (W in FIG. 27)._si1) In the vicinity of the source / drain regions (for example, W in FIG. 27)._si2), At the position connected to the source / drain region. That is, the shapes of FIGS. 27 to 31, 33, 34, and 46 to 49 all have the width W of the semiconductor layer from the channel formation region 7 to the source / drain region 4._siIn this case, the width W of the channel forming region in the lateral direction is increased._siOr at least the width W at the center of the channel forming region._SiIs reduced, which is effective in improving the S factor, suppressing the short channel effect, and the like, as well as improving the characteristics of the transistor, as in the case of reducing the thickness of the semiconductor layer in a normal SOI field effect transistor. On the other hand, at the position in contact with the source / drain region, the width of the semiconductor layer forming the conduction path 33 increases, so that the effect of reducing the parasitic resistance can be obtained. Further, a conduction path 33 having a source / drain connection portion 32 (a shape shown in FIGS. 27, 28, 30, 31, 33, 34, and 46 to 49) which is a region containing a high concentration impurity is formed. If it has, the contact area between the source / drain connection portion 32 and the channel formation region 7 is reduced. Then, when a drain junction which is a high-concentration impurity region is formed shallowly in a normal field-effect transistor, when a source / drain extension having a high impurity concentration and a shallow junction is provided, or when a semiconductor layer is thinned in an SOI field-effect transistor, As a result, the cross-sectional area of the high-concentration impurity region is reduced at the portion where the high-concentration impurity region and the channel formation region are in contact with each other, as in the case where the drain, which is the high-concentration impurity region, is formed thin. Thus, the characteristics of the transistor are improved. That is, by reducing the width of the source / drain connection portion in the arrangement direction of the openings in the portion in contact with the semiconductor layer forming the channel formation region, a short channel effect suppressing effect can be obtained, and at the same time, the source / drain connection in the arrangement direction of the openings is obtained. By increasing the width of the portion at the portion in contact with the source / drain region, a parasitic resistance suppressing action can be obtained, and the third problem can be suppressed.
[0067]
The shape of the opening may be a square as shown in FIG. In this case, W_si, W_spAre both constant. In this case, there is a feature that the structure is simple and the manufacture is easy. Further, as described below, there is a feature that the parasitic capacitance 36 is small.
[0068]
Next, the parasitic capacitance 36 between the gate side surface and the source / drain side surface will be described with reference to FIGS. FIG. 54 shows a top view in the case where there is an opening (or a space in which an insulator is embedded in the opening) between the gate end and the source / drain region. This corresponds to a case where at least a part of the source / drain connection part 32 is not covered with the gate. FIG. 55 shows a top view in the case where there is no opening (or a space in which an insulator is embedded in the opening) between the gate end and the source / drain region. This corresponds to a case where all of the source / drain connection portions 32 are covered with the gate. 56 and 57 are cross-sectional views taken along a line A205-A205 'in FIG. 54 and a cross section taken along a line A206-A206' in FIG. In FIGS. 54 and 55, the outline of the opening 10 and the outline of the gate insulating film 6 that are actually hidden below the gate electrode 5 are clearly shown for easy viewing.
[0069]
In the structure having an opening between the gate end and the source / drain region (FIGS. 54 and 56), the side surface of the gate is separated from the side surface of the source / drain region by a distance corresponding to the opening. The parasitic capacitance 36 between them is small. On the other hand, in the structure having no opening between the gate end and the source / drain region (FIGS. 55 and 57), since the distance between the gate side surface and the source / drain side surface is small, the parasitic capacitance between the gate side surface and the source / drain side surface is small. 36 becomes large, which is disadvantageous for high-speed operation of the element. In the step of depositing an insulating film such as a step of depositing a PSG and a step of depositing an interlayer insulating film in the opening 10 of the transistor of the present invention, SiO₂, PSG or the like is buried, but the inside of the opening is SiO₂, PSG or the like, or even if a cavity that is not filled with the insulator remains in the opening, the parasitic capacitance 36 in the structure of FIG. 54 and FIG. Is still smaller than the parasitic capacitance 36 in the above structure.
[0070]
Therefore, a structure in which at least a part of the source / drain connection portion 32 is not covered with the gate electrode on both the side surface and the upper surface (the structure in FIGS. 27, 30 to 34, and FIGS. 46 to 49) is a parasitic structure. This can be said to be advantageous in reducing the capacity.
[0071]
In the structures shown in FIGS. 1, 6, 7, and 27 to 34, the channel plane is slightly inclined from the (100) plane (or equivalent plane) or the (100) plane (or equivalent plane). The openings are arranged in the [100] direction (or a direction equivalent thereto) so that they are plane. In the structure of FIGS. 46 to 49 in which one side of the square opening is inclined 45 degrees with respect to the arrangement direction of the openings, if the arrangement direction of the openings is set to the [110] direction (or a direction equivalent thereto). , The channel plane is formed in the (100) plane (or a direction equivalent thereto). When the channel plane is formed on the (100) plane or a plane slightly inclined from the (100) plane, excellent characteristics can be obtained in that the interface state is small and the mobility of the channel carrier is large. 46 to 49 relate to the same transistor, FIG. 46 shows the positional relationship between the opening and the gate electrode, FIG. 47 is a top view after forming contacts with the source / drain and the gate, and FIG. FIG. 49 is a bird's-eye view of the layer shape, and FIG. 49 is a bird's-eye view after the gate electrode is formed. In FIG. 49, the gate insulating film is omitted to make the drawing easier to see. FIG. 49 shows a case where the mask film 9 and the pad film 8 have been removed from the source / drain connection portion 32 (both need not necessarily be removed).
[0072]
Note that the shapes of the various openings and the source / drain connection described in the present embodiment can be applied to the various forms described in the first embodiment. In addition, the various openings and the source / drain connection portions described in this embodiment have the shape of a transistor in which an insulating film having the same thickness as a side surface of a channel formation region is provided above a channel formation region; The present invention can be applied to a transistor having an insulating film thicker than the side surface of the channel formation region, and a transistor having a multilayer insulating film above the channel formation region.
[0073]
(Embodiment 3)
Next, a manufacturing method for forming the field-effect transistors of Embodiments 1 and 2 will be described.
[0074]
100 nm thick SiO 2 on silicon substrate 1₂An SOI (silicon-on-insulator) substrate having a buried insulating layer 2 and a semiconductor layer 3 made of a single-crystal silicon layer with a thickness of 120 nm is prepared on the buried insulating layer 2. Next, a pad oxide film 8 is provided by thermally oxidizing the upper portion of the semiconductor layer 3 by 20 nm, and a 50 nm thick Si is formed thereon by CVD.₃N₄A membrane 9 is provided. Next, a resist pattern having a pattern in which openings are arranged is provided by a lithography process, and the pad oxide film 8 and the Si film are formed by a normal etching process such as RIE using the resist pattern as a mask.₃N₄The film 9 is patterned (FIG. 9).
[0075]
Next, a resist pattern is provided to cover a predetermined area including the pattern in which the openings are arranged (for example, a range surrounded by a dotted line A9 in FIG. 9).₃N₄The film 9 and the pad oxide film 8 are patterned by RIE. After removing the resist, the remaining Si₃N₄Using the film 9 and the pad oxide film 8 as a mask, the etching rate for silicon is₃N₄Selective RIE (reactive ion etching, reactive ion etching) faster than the etching rate for the film is performed to pattern the semiconductor layer 3 (FIG. 10). As a result, Si outside the certain area (in this case, the area surrounded by the dotted line of A9)₃N₄The film 9, the pad oxide film 8, and the semiconductor layer 3 are removed.
[0076]
Also, following the etching of silicon, SiO 2₂Etching rate for Si₃N₄By performing selective RIE faster than the etching rate for the film, SiO₂The shape in which the upper end of the film 2 is located below the lower end of the semiconductor layer 3 (FIG. 8), or SiO 2 in the opening₂A shape in which the surface of the film 2 is inclined (FIG. 26) can also be obtained. In addition, Si₃N₄The two-layer structure of the film 9 and the pad film (pad oxide film 8) is Si₃N₄A single-layer structure of only the film 9 may be used (hereinafter, a single-layer structure and a multi-layer structure are collectively referred to as a “mask film 9” as appropriate). The material of the mask film may be any material that can selectively etch the semiconductor layer 3. For example, SiO₂But it's fine. The shape of the opening is not limited to the shape shown here. For example, the shapes shown in FIGS. 27 to 34 and FIGS. 46 to 49 may be used. In the process described here, SiO₂The main reason for providing the pad film 8 made of₃N₄Preventing the semiconductor layer 3 from being stressed by direct contact between the film 9 and the semiconductor layer 3;₃N₄When the film 9 and the semiconductor layer come into direct contact with each other,₃N₄To prevent generation of a large amount of interface states at the interface between the film 9 and the semiconductor layer 3, for example,₃N₄The purpose of the present invention is to avoid a problem caused by the direct contact between the film 9 and the semiconductor layer 3. Si₃N₄If the problem caused by the direct contact between the film 9 and the semiconductor layer 3 is small, the pad oxide film 8 may be omitted.
[0077]
Further, after the opening 10 is formed in the semiconductor layer 3 by etching (after the formation of the shape in FIG. 10), when the upper portion of the buried insulating film 2 is subsequently etched, in order to prevent the mask film from being entirely lost by the etching, It is preferable to select a combination of the material of the mask film and the material of the buried insulating layer so that only the buried insulating layer can be selectively etched. If the combination does not satisfy this condition, the following is performed. For example, the mask film 9 is made of the same SiO 2 as the buried oxide film.₂In this case, the thickness of the mask film 9 may be increased in anticipation that a part of the mask film 9 will be removed when the buried oxide film 2 is etched. Generally speaking, when the buried insulating layer is etched after the etching of the semiconductor layer in the opening, and the material of the buried insulating layer and the material of the mask film 9 are the same, the depth T at which the buried insulating layer is etched is T._boxovThan the thickness of the mask film T_maskShould be increased.
[0078]
Further, after the semiconductor layer is exposed, a heat treatment step for flattening and cleaning the side surface of the exposed semiconductor layer before forming the gate insulating film on the surface of the semiconductor layer may be added. For example, hydrogen annealing is performed. Typical hydrogen annealing conditions are 10 to 50,000 Pa, 850 to 1100 ° C., and about 5 to 60 minutes. However, when the distance between the openings is small and the thickness of the semiconductor layer in the plane direction of the substrate is small, the heat treatment may be performed in a shorter time or at a lower temperature to avoid aggregation of the semiconductor layer. Further, another gas such as HCl may be mixed in a hydrogen atmosphere.
[0079]
Further, after the openings 10 arranged so as to cross the semiconductor layer 3 are provided, the exposed side surfaces of the semiconductor layer are made of SiO 2._TwoBy covering with a film and performing a heat treatment at a temperature of 980 ° C. or more (more preferably, a temperature of 1200 ° C. or more) for 1 hour or more,During the step of providing the openingSide view of exposed semiconductor layer, That is, the semiconductor interface on the side of the openingMay be added. Here, the temperature of 980 ° C. or more is SiO_TwoThe temperature is required to impart fluidity to the film, and a temperature of 1200 ° C. or higher is a temperature required to make the flow remarkable. The heat treatment is performed in nitrogen. Alternatively, it is performed in an inert gas such as Ar. In addition, oxygen is mixed in the atmosphere for performing the heat treatment, and the exposed side surface of the semiconductor layer 3 is oxidized, so that the width W of the semiconductor layer forming the channel formation region is obtained._SiMay be reduced (the thickness of the semiconductor layer forming the channel formation region in the plane direction of the substrate is reduced).
[0080]
After the openings 10 arranged so as to cross the semiconductor layer 3 are provided, the exposed side surface of the semiconductor layer is covered with an insulating film (for example, this insulating film is made of SiO 2).₂Film, Si₃N₄It is made of an insulator such as a film. Further, for example, it is composed of a multilayer film composed of a plurality of insulators. ), And heating by a beam such as a laser beam or an electron beam, or a heat source such as an electric heater, to melt a part of the semiconductor region where the conduction path or the channel formation region is formed near the side surface and re-use the semiconductor region. A crystallization step may be performed. Similarly, by heating with a beam such as a laser beam or an electron beam, or a heat source such as an electric heater, the entire semiconductor region (projection) in which a conduction path or a channel formation region is formed is melted, and the melted region is re-used. It may be crystallized. The purpose of this step is to flatten the unevenness generated on the side surface of the semiconductor layer by the RIE step. The power and energy of a beam such as a laser beam or an electron beam, the temperature of the electric heater, and the scanning speed of the beam and the electric heater are preferably such that only the surface of the semiconductor region (projection) where the conduction path or the channel forming region is formed is melted. Preferably, the inside is not melted, or the protrusion in which the conduction path is formed is melted and the semiconductor region in which the source / drain region is formed is not melted. This is because, in the process of lowering the temperature of the substrate after the beam scanning, the region inside the semiconductor protrusion that has not been melted or the source / drain region that has not been melted is used as a seed crystal (seed) to melt the region. Is to recrystallize. Further, in order to remove defects such as fixed charges or traps generated in the buried oxide film due to the melt recrystallization, a high-temperature heat treatment step (1000 ° C. or higher, typically 1300 ° C. or higher) after the melt crystallization is performed. A heat treatment at 1360 ° C. for one hour or more in an oxidizing atmosphere or a non-oxidizing atmosphere) or a lower temperature heat treatment in an oxidizing atmosphere may be performed.
[0081]
Next, the SiO₂An insulating film for forming the dummy gate insulating film 18 is deposited to a thickness of 10 nm, and is etched back (a step of removing the material film deposited on the flat portion and leaving the material film deposited on the side wall portion) by RIE to obtain a semiconductor. A dummy gate insulating film 18 is provided on the inner wall of the opening 10 in the layer 3 and on the side surface of the semiconductor layer (side surface around the semiconductor layer forming the element region). Subsequently, polysilicon is deposited by CVD and processed by normal lithography and RIE to provide a dummy gate electrode 11. At this stage, the shapes of the pad oxide film 8 and the Si₃N₄It is the same as FIG. 1 except that the film 9 is present and the dummy gate insulating film 18 and the dummy gate electrode 11 are provided instead of the gate insulating film 6 and the gate electrode 5 (the dummy gate electrode 11 in FIG. 39). 39, but the dummy gate insulating film 18 is omitted in FIG. 39 to make the drawing easier to see). Here, the reason why the dummy gate insulating film 18 and the dummy gate electrode 11 are formed is that a so-called replacement gate process for forming the gate insulating film 6 and the gate electrode 5 again in a space obtained by removing these later. This is preparation for implementation.
[0082]
When the replacement gate process is not performed, the gate insulating film 6 is formed instead of forming the dummy gate insulating film 18 and the gate electrode 5 is formed instead of forming the dummy gate electrode 11 here (in FIG. 39, the gate electrode 5 is formed). 39. However, in FIG. 39, the gate insulating film 6 is omitted for the sake of simplicity of the drawing), followed by introduction of impurities into the source / drain connection regions described below, formation of the source / drain, and wiring The formation may be performed to form a transistor. In this case, in the steps from FIG. 11 to FIG. 16, a shape in which the gate insulating film 6 is provided instead of the dummy gate insulating film 18 and the gate electrode 5 is provided instead of the dummy gate electrode 11 is obtained.
[0083]
In this step (the process leading to FIG. 11), the dummy gate insulating film 18 is deposited by CVD because, if the dummy gate insulating film 18 is formed by thermal oxidation, the mask film ( In this case, the pad oxide film 8 and Si₃N₄Since the width of the semiconductor forming the channel formation region in the substrate plane direction is smaller than the width of the film 9 (two-layer film) in the substrate plane direction, the semiconductor layer forming the channel formation region below the mask film is closer than the end of the mask film. This is because special attention has been paid to prevent the problem that the step also recedes and a step is generated, and the flatness in the vertical direction is easily deteriorated. However, in general, the gate insulating film 6 and the dummy gate insulating film 18 are made of SiO 2₂Other insulating films may be used, and SiO formed by thermal oxidation may be used.₂It may be a film. Generally, the dummy gate insulating film 18 may be made of any material that can be selectively removed from the semiconductor layer 3. Further, the dummy gate electrode 11 is₃N₄For example, the dummy gate insulating film 18 may be omitted when the dummy gate electrode can be selectively removed from the semiconductor layer 3. .
[0084]
Then Si₃N₄RIE is performed under conditions having selectivity to the film to remove the dummy gate insulating film other than the portion under the dummy gate electrode, and then a PSG (phosphor glass) film 12 is entirely deposited to a thickness of 200 nm and etched by RIE. By backing, the side wall-shaped PSG film 12 is provided on the inner wall of the opening 10 and the side surface of the semiconductor layer. At this stage, cross-sectional views taken along the line A10-A10 ', the line B10-B10', and the line C10-C10 'in FIG. 10 are shown in FIG. 11, FIG. 12, and FIG. In this step, PSG is deposited by depositing PSG on the inner wall of the opening, diffusing high-concentration phosphorus from PSG into the semiconductor region adjacent to the opening on both sides of the gate electrode (or dummy gate electrode), High concentration (5 × 10¹⁸cm^-3Above, preferably 3 × 10¹⁹cm^-3Above) is to form the source / drain connection part 32 by introducing phosphorus. The heat treatment for diffusing phosphorus from PSG (for example, 800 ° C. for 10 seconds) may be performed immediately after the deposition of the PSG, or may be performed after some steps after the deposition of the PSG. A method in which phosphorus is diffused from PSG at the same time as another thermal process (eg, activation after ion implantation into the source / drain, gate oxidation) performed after the deposition of PSG may be used.
[0085]
FIG. 14 shows a case where the width of the opening in the source / drain direction is large, and the opening is not completely filled with PSG. In this case, however, the adhesion of PSG to the inner wall of the opening is guaranteed. There is no. FIG. 15 is a top view in a state corresponding to FIG. N due to thermal diffusion from PSG⁺FIG. 16 shows a cross-sectional view at a position corresponding to the cross section taken along line B10-B10 'in a state where the mold source / drain regions 4 are formed.
[0086]
In the case of a p-channel transistor, a diffusion source of a p-type impurity such as BSG (boron glass) is used instead of PSG. Also in the case of an n-channel transistor, an n-type impurity diffusion source (for example, arsenic glass) other than PSG may be used instead of PSG. In addition, BPSG (boron, phosphorus glass) containing both boron as a p-type impurity and phosphorus as an n-type impurity, in which one of boron and phosphorus is increased, is replaced with a p-type or n-type transistor, respectively. May be used for the production of
[0087]
Source / drain regions are formed in the semiconductor layer on both sides of the gate electrode and portions away from the opening by a normal process. For example, by ion implantation, plasma doping, or the like, an n-type transistor is highly doped with an n-type impurity in the case of an n-channel transistor, and¹⁹cm^-3Above, preferably 1 × 10²⁰cm^-3~ 3 × 10²⁰cm^-3). As the n-type impurity, an impurity forming a donor such as phosphorus or arsenic is used, and as the p-type impurity, an impurity forming an acceptor such as boron is used. Further, the source / drain regions may be epitaxially grown or may be silicided to reduce parasitic resistance.
[0088]
The mask film 9 on the semiconductor layer 3 is provided for the purpose of protecting the semiconductor layer 3 at the time of processing the dummy gate electrode 11 (or the gate electrode 5 in place of the dummy gate electrode 11). Is unnecessary in the step of introducing impurities or the step of silicidizing the source / drain regions. Therefore, after forming the dummy gate electrode 11 (or the gate electrode 5 in place of the dummy gate electrode 11) by RIE, the impurity is added to the source / drain regions. Is desirably removed by RIE or wet etching at any stage before the introduction. After the PSG is deposited, the PSG is etched back by RIE, and in the step of forming the side wall made of PSG, the mask film 9 and the pad oxide film 8 in the region excluding the lower part of the gate electrode and the lower part of the PSG side wall are simultaneously removed. A shape in which the upper surface of the semiconductor layer 3 is exposed in a region where the source / drain region is formed as shown in FIG. Also, the PSG side wall is formed while leaving the mask film 9 and the pad oxide film 8 (FIGS. 12 and 13), and after the impurity is diffused from the PSG and before the source / drain regions are formed, the mask film 9 and the pad oxide film are formed. RIE for the purpose of removing the film 8 may be performed (at this time, the upper portion of the PSG is also removed, but there is no problem since the impurity diffusion from the PSG has already been performed). Further, after processing the dummy gate electrode 11 (or the gate electrode 5 in place of the dummy gate electrode 11) by RIE, the mask film 9 and the pad oxide film 8 may be removed by an etching process such as RIE before depositing PSG. In this case, the element shape finally obtained through various steps is as shown in FIG. If the mask film 9 and the pad oxide film 8 are removed at any stage after the deposition of the PSG, the shape shown in FIG. 36 is finally obtained.
[0089]
After the deposition of PSG and etch back, the SiO₂Is deposited to form an interlayer insulating film 13, and the interlayer insulating film 13 is planarized by CMP using the dummy gate electrode 11 as a stopper. At this time, the upper portion of the dummy gate electrode 11 is simultaneously exposed. Subsequently, the dummy gate electrode 11 is removed by RIE, and then the dummy gate insulating film 18 is removed by RIE. Subsequently, a gate insulating film 14 is formed to a thickness of 2 nm by thermal oxidation, and a conductive material such as TiN is buried in a slit obtained by removing the dummy gate electrode 11 by a sputtering method to form a gate electrode 5 (FIG. 18). , 19). FIG. 19 shows a shape when the gate insulating film 14 is formed by thermal oxidation, and FIG. 18 shows a shape when the gate insulating film 14 is formed by CVD.
[0090]
Thereafter, openings (openings for forming the gate contacts 17 and openings for forming the source / drain contacts 16) are formed in the interlayer insulating film on the gate electrode and the source / drain regions, respectively, and a metal material such as Al is sputtered, CVD or the like. After being deposited and then patterned to provide the wiring 24, the field effect transistors shown in FIGS. 35 to 38 are obtained. Here, the wiring connected to the gate electrode 5 is not drawn, but the wiring is connected to the gate electrode 5 via the gate contact 17 in the same manner as the connection to the source / drain region 4 via the source / drain contact 16. . 36 and 38 show a cross section taken along line B41-B41 'in FIG. 35, and FIG. 37 shows a cross section taken along line C41-C41' in FIG. 36 shows the case where the mask film 9 and the pad oxide film 8 are removed before the deposition of the PSG, and FIG. 38 shows the case where the mask film 9 and the pad oxide film 8 are removed after the deposition of the PSG. FIG. 37 shows the case where the openings are not completely filled with PSG (FIG. 14).
[0091]
After the dummy gate insulating film is removed by RIE, the surface of the semiconductor layer forming the channel formation region is removed by dry etching in order to remove damage and contamination generated in the semiconductor layer when the dummy gate insulating film is removed by RIE. A part may be removed. For the dry etching at this time, isotropic etching is preferable. As an etching gas, Cl₂, CF₄, CHF₃, HCl or the like may be used. At the same time as performing the dry etching here, the semiconductor layer forming the channel formation region may be etched from both sides for the purpose of making the semiconductor layer thinner. For example, the thickness may be reduced until the width of the semiconductor layer becomes about 5 to 10 nm in order to suppress the short channel effect.
[0092]
Of course, in the step of forming the dummy gate insulating film 18 and the dummy gate electrode 11, if the gate oxide film 6 and the gate electrode 5 are formed instead of these, the conductive material is removed from the dummy gate insulating film. The above-described steps leading to the formation of the gate electrode 5 by filling are not required.
[0093]
Further, after the semiconductor layer is exposed, a heat treatment step for flattening and cleaning the side surface of the exposed semiconductor layer before forming the gate insulating film on the surface of the semiconductor layer may be added. For example, hydrogen annealing is performed. Typical hydrogen annealing conditions are 10 to 50,000 Pa, 850 to 1100 ° C., and about 5 to 60 minutes. However, especially when the distance between the openings is small and the semiconductor layer is thin, heat treatment may be performed in a shorter time or at a lower temperature to avoid aggregation of the semiconductor layer. Further, another gas such as HCl may be mixed in a hydrogen atmosphere.
[0094]
In the case where the width of the source / drain connection is large (for example, the structure shown in FIGS. 6 and 46 to 49), the impurity is introduced into the source / drain connection by performing normal ion implantation from above. May be. When ions are implanted into the source / drain connection from above, it is preferable to remove the mask film 9 and the pad film 8 (FIG. 49). The mask film 9 and the pad film 8 may be simultaneously removed from both the source / drain connection portion and the source / drain region, and impurities may be introduced simultaneously.
[0095]
In the case where ions are implanted into the source / drain region and the source / drain connection portion from above, ion implantation with different energies may be repeated a plurality of times in order to make the impurity concentration perpendicular to the substrate plane uniform.
[0096]
In the method of manufacturing a field-effect transistor described above, the mask layer (here, Si₃N₄The film is provided with a pattern in which extra openings are arranged in advance, and then the element layer is formed by patterning the semiconductor layer 3 in a region excluding the extra opening pattern, so that the width of the semiconductor layer forming the channel formation region is made uniform. Can be formed. Here, if the opening pattern and the pattern of the element region are to be formed simultaneously without providing an extra arrangement in the opening pattern, the channel forming region located at the end of the opening pattern arrangement (in FIG. The width of the resist pattern corresponding to the right and leftmost semiconductor regions is narrowed due to the influence of a light beam (or an electron beam or an X-ray beam) exposed to a wide region outside the element region. As a result, as shown in FIG. 51, the width of the semiconductor layer forming the channel forming region located at both ends of the opening pattern arrangement may be narrowed (proximity effect). In contrast, when the present manufacturing method is used, this problem does not occur, and an element region having a uniform width can be obtained as shown in FIG.
[0097]
Further, in the manufacturing method according to the present embodiment, a mask layer (here, SiO 2) is formed above the semiconductor layer in the channel formation region.₂Layer and Si₃N₄Since the two-layer film is provided, the semiconductor layer in the channel formation region is not damaged during the etching of the gate electrode (or the dummy gate electrode). The material of the mask layer may be any material as long as the entire mask layer is etched during the etching of the gate and does not disappear. For example, SiO₂Layer, Si₃N₄It is only necessary to select a material such as a layer that is not or hardly etched when the gate electrode or the dummy gate electrode is etched.
[0098]
After removing the dummy gate electrode and the dummy gate insulating film, an insulating sidewall material, for example, a second Si having a thickness of 5 nm is formed.₃N₄A film is deposited on the entire surface by CVD, and then the insulating material is etched back by RIE to form a sidewall made of the insulating material in a slit obtained by removing the dummy gate electrode and the dummy gate insulating film. May be added. At this time, when both the semiconductor layer forming the channel formation region and the dummy gate electrode have substantially vertical side surfaces, the height of the dummy gate electrode (the height from the lowermost end to the uppermost end in contact with the buried oxide film) ) Is at least twice as large as the semiconductor layer forming the channel formation region, the insulating sidewall material (here, the second Si₃N₄By performing RIE on the film) at least as thick as the thickness of the semiconductor layer forming the channel formation region, an insulating sidewall material (here, the second Si₃N₄There is no film, and only the inner wall of the slit has an insulating side wall material (here, the second Si₃N₄Film). When the side wall made of an insulating material is provided on the inner wall of the slit, the semiconductor in the slit can be cleaned or etched without damaging the material adjacent to the slit (here, PSG). For example, in order to remove contamination on the side surface of the semiconductor layer, or the width W of the semiconductor layer._siIn order to reduce the thickness, the semiconductor side surface is once thermally oxidized (10 times or less the gate oxide film thickness for the purpose of removing contamination, and there is no particular range for the purpose of thinning. This is called sacrificial oxidation), which is called dilute hydrofluoric acid or buffered hydrofluoric acid such as SiO₂Even if a step (sacrificial oxide film removing step) is performed by using an etchant, the both sides of the slit are covered with the insulating side wall material, so that damage to the material (PSG in this case) on both sides of the slit is small.
[0099]
As a method of providing a side wall on the gate electrode 5 (or the dummy gate electrode 11), the height h of the gate electrode 5 (or the dummy gate electrode 11) from the surface of the buried insulating layer in the opening formed in the semiconductor layer is used._gIs the height t of the semiconductor layer from the surface of the buried insulating layer._SiAfter forming the gate electrode 5 (or the dummy gate electrode 11) on the structure of FIG. 10, the insulating side wall material is coated so as to cover the surface of the gate electrode 5 (or the dummy gate electrode 11). Is deposited, and then_siAbove, (h_g-T_SiBy etching back over a thickness of less than), a side wall can be formed on the side surface of the gate electrode at a position from the lower end of the gate electrode to the height of the upper end of the semiconductor layer.
[0100]
However, in the method of forming an insulating sidewall on the inner wall of the slit described in the present embodiment and the method of forming an insulating sidewall on the gate electrode 5 (or the dummy gate electrode 11) also described in the present embodiment, FIG. At the time when the gate electrode 5 (or the dummy gate electrode 11) is formed on the structure, both side surfaces of the gate electrode 5 (or the dummy gate electrode 11) cannot be completely covered with the insulating side walls (the former method uses this method). The side wall of the gate electrode is partially exposed in the latter method). Therefore, when the semiconductor material is epitaxially grown on the source / drain regions, there is a problem that the semiconductor material also epitaxially grows on the side surfaces of the gate electrode. A solution to this problem is described in Embodiment 4.
[0101]
Note that each step in this embodiment can be used for manufacturing the field-effect transistor described in Embodiments 1 and 2 or the field-effect transistor involving various deformations described in Embodiments 1 and 2. Further, a part of each process in the present embodiment is combined with another general method for manufacturing a field-effect transistor, so that the field-effect transistor described in the first and second embodiments or the first and second embodiments can be combined. It is also possible to manufacture field-effect transistors involving various deformations described in (1).
[0102]
Further, the film thickness, dimensions, and material of each part in the present embodiment may be appropriately changed according to the description of the first and second embodiments.
[0103]
(Embodiment 4)
A method different from the method described at the end of Embodiment 3₃N₄A method for forming the side wall will be described with reference to FIGS. 20 to 22 correspond to the section taken along line B10-B10 'in FIG. 10, and FIGS. 23 to 25 correspond to the vicinity of the dummy gate electrode 11 in section taken along the line C10-C10' in FIG. The invention of the fourth embodiment is characterized in that the side wall is formed on the gate electrode 5 when the side wall is provided on the dummy gate electrode of the third embodiment or when the step of providing the gate electrode 5 is performed instead of the step of providing the dummy gate electrode of the third embodiment. It can be used when providing.
[0104]
First, a case where a sidewall is provided in the dummy gate electrode 11 will be described. After the formation of the dummy gate electrode 11, the second Si₃N₄A film 20 is deposited to a thickness of 10 nm by CVD. Subsequently, a second CVD SiO₂A film 21 is deposited to a thickness of 200 nm by the CVD method and is planarized by the CMP (FIGS. 20 and 23). Subsequently, the second Si₃N₄Film 20 and second CVD SiO₂The film 21 is etched by 15 nm by RIE, then polysilicon is deposited to 20 nm, and the polysilicon is etched back by RIE, and the first side wall 22 (in this case, the material is polysilicon) is placed on both upper and lower sides of the dummy gate electrode 11. (FIGS. 21 and 24). Subsequently, using the dummy gate electrode 11 and the first sidewall 22 as a mask, the second Si₃N₄Film 20 and second CVD SiO₂By etching back the film 21, the second Si₃N₄Film 20 and second CVD SiO₂A gate sidewall composed of a part of the film 21 is provided on a side surface of the dummy gate electrode 11 (FIGS. 22 and 25). Note that the second CVD SiO₂The second Si without the film 21₃N₄A gate sidewall in which the side surface of the film 20 is exposed may be provided (the effect of the invention is not changed). Second CVD SiO₂For example, in the case where the lateral protrusion of the first sidewall 22 is small, the sidewall without the film 21 is made of SiO 2 by hydrofluoric acid or the like after the formation of the gate sidewall.₂This occurs when is etched.
[0105]
When the gate sidewall is provided in this manner, when various processes (ion implantation, silicidation, epitaxial growth of semiconductor) are performed on the source / drain region after the formation of the dummy gate electrode, the gate electrode and the lower portion of the gate electrode are removed. Can be protected. In addition, since the oxide film and the PSG film are not exposed after removing the dummy gate electrode, the removal of the dummy gate oxide film can be performed by wet etching, and damage to the semiconductor layer forming the channel formation region is reduced. . In addition, when the dummy gate is removed and the slit is formed, the peripheral portion of the gate electrode protected by the gate sidewall remaining on the inner wall of the slit is not affected by wet etching, so that the semiconductor layer forming the channel formation region is thinned. This can be performed by sacrificial oxidation and subsequent wet etching of the sacrificial oxide film, and damage to the semiconductor layer forming the channel formation region (particularly damage due to etching) is reduced.
[0106]
When the dummy gate electrode is not formed, the invention of the present embodiment may be similarly applied to a gate electrode provided in place of the dummy gate electrode. When various processes (ion implantation, silicidation, epitaxial growth of a semiconductor) are performed on the source / drain regions after the formation of the gate electrode, the gate electrode and the lower portion of the gate electrode can be protected.
[0107]
(Embodiment 5)
Without providing the PSG film, impurities may be introduced into the semiconductor layer adjacent to the opening by a normal impurity introduction process other than solid-phase diffusion from the PSG film, such as ion implantation or plasma doping. In this case, after the impurities are introduced, SiOG is used instead of PSG.₂, Si₃N₄What is necessary is just to deposit an insulating material such as.
[0108]
(Embodiment 6)
Instead of providing a PSG film in the opening, after providing an insulating film side wall on the gate electrode 5 or the dummy gate electrode 11 according to the method of the fourth embodiment, an impurity of the same conductivity type as that of the channel type is contained at a high concentration by selective epitaxial growth. When a semiconductor (Si, silicon-germanium mixed crystal, etc.) is grown on the side surface of the source / drain connection, a source / drain connection having the shape shown in FIG. 33 is obtained. In this case, the shape of the source / drain connection portion is thickened while being inclined toward the source / drain region from a position separated from the connection point with the channel formation region by a thickness corresponding to the side wall of the gate electrode (or dummy gate electrode). Have a shape. Such a tilt is derived from a crystal habit (facet) formed during selective epitaxial growth. FIG. 34 shows an amorphous layer of a semiconductor (Si, silicon-germanium mixed crystal, or the like) containing a high concentration of impurities having the same conductivity type as that of a channel type when a crystal habit (facet) formed during selective epitaxial growth is not formed. Alternatively, this is a case where a layer made of polycrystal is selectively formed. Generally, when the flow rate of the growth gas is relatively small, and when the growth temperature is relatively high, facets are easily formed. Further, when the facet is not formed, a shape in which the source / drain connection portion is inclined and recedes from the gate electrode cannot be obtained, but in this case, as compared with the case where the facet is formed, the source / drain connection portion and the gate electrode are not formed. The parasitic capacitance between them increases. In order to avoid this problem, in FIG. 34 where facets are not formed, a method is adopted in which the side wall provided on the gate electrode (or the dummy gate electrode) is set to be thick to reduce the parasitic capacitance between the gate electrode and the source / drain connection. You may.
[0109]
When the selective epitaxial growth is performed, if the upper part of the source / drain region is exposed, the epitaxial growth proceeds upward also to the upper part of the source / drain region. If the upper portion of the source / drain region is covered with the mask film 9 and is not exposed, epitaxial growth does not occur on the upper portion of the source / drain region.
[0110]
To form the source / drain regions, first, after selective epitaxial (or polycrystalline, amorphous) growth, for example, a third CVD oxide film is deposited thickly (for example, 200 nm) on the entire surface and etched back to form a source / drain connection portion. Of these, a thick gate side wall (third CVD oxide film in this case) is provided to cover a part near the gate electrode (or dummy gate electrode) or the entire source / drain connection (the form is similar to the side wall of the PSG film). However, the removal of the mask film on the semiconductor layer may be performed before or after the formation of the CVD oxide film sidewall), and then the source / drain regions are formed using the thick gate sidewall (here, the third CVD oxide film) as a mask. , For example, ion implantation may be performed. Here, at least a part of the source / drain connection portion near the gate electrode (or the dummy gate electrode) is covered because the source / drain connection portion in this region is formed of a semiconductor layer having a small thickness in the substrate plane direction. This is to protect this portion from ion implantation because it is vulnerable to ion implantation damage.
[0111]
When it is necessary to form both an n-channel and a p-channel MOS in a circuit having a CMOS configuration, a resist is applied to a region where a transistor of the second channel type is formed, so that a transistor of the first channel type is formed. Only the steps related to the formation of the gate side wall and the exposure of the semiconductor layer (FIGS. 21, 22, 24, and 25) are carried out only for the epitaxial growth on the source / drain region connection and the formation of the source / drain. A series of steps are performed (however, the resist is once removed before the step of forming the shape of FIG. 20 and is provided again before the step of forming the shape of FIG. 21. Alternatively, the shape of FIG. After forming a transistor, the whole is covered with a thin CVD oxide film, for example, 10 nm in thickness, and then each channel is formed. Each time to build a type of transistor, a thin CVD oxide film formed on the surface of the transistor forming region of each channel type is removed, may be performed a step of preparing a 22 subsequent shape.). Thereafter, the whole is covered with a fourth CVD oxide film (there is no limitation on the film thickness; it may be as thin as about 10 nm, or may be as thick as about 200 nm to 500 nm in order to obtain flatness. The region in which the first channel type transistor is formed is covered with a resist, and the steps after the step of forming the shape of FIG. 21 (if the shape of FIG. 20 is separately formed for both channel types, (The step of forming the shape shown in FIG. 20 is also performed.)
[0112]
The manufacturing method of this embodiment may be used for manufacturing a vertical field-effect transistor (for example, the shape shown in FIG. 50) in which channel formation regions are not arranged in parallel (FIG. 40). Each manufacturing process is the same as the above-described manufacturing method described in the sixth embodiment, except that the semiconductor is patterned in such a manner that an element region including a single current path is formed (broken line portion in FIG. 40).
[0113]
(Embodiment 7)
When the manufacturing method of Embodiment 6 is used, the shape of the opening initially provided in the semiconductor layer is rectangular as shown in FIG. 32, and after forming the gate electrode 5 (or the dummy gate electrode 11), the opening is formed in the source / drain connection part 32. By performing the selective growth of the semiconductor, the width of the source / drain connection portion 32 is narrow on the channel forming region 7 side and wide on the source / drain region 4 side, and the width of the source / drain connection portion 32 is continuous between them. A shape that changes stepwise (FIGS. 33 and 34) can be obtained.
[0114]
In this case, a shape having a rectangular opening as shown in FIG. 32 can be formed as follows. One example will be described with reference to FIGS. 100 nm thick SiO 2 on silicon substrate 1₂An SOI (silicon-on-insulator) substrate having a buried insulating layer 2 and a semiconductor layer 3 made of a single-crystal silicon layer with a thickness of 120 nm is prepared on the buried insulating layer 2. Next, a pad oxide film 8 is provided by thermally oxidizing the upper portion of the semiconductor layer 3 by 20 nm, and a 50 nm thick Si is formed thereon by CVD.₃N₄A membrane 9 is provided. Next, a second mask material 41 is deposited thereon (here, polysilicon having a thickness of 20 nm is deposited as the second mask material 41 by a CVD method). Next, a resist pattern in which rectangles are arranged is provided by a lithography process, and the resist is used as a mask to pattern the second mask material 41, and the rectangular second mask material 41 (here, polysilicon) is arranged. Get. Here, the width of the second mask material 41 in the arrangement direction (the horizontal direction in FIG. 41) is, for example, 50 nm. Next, a resist pattern is provided in a region (region 44 in FIG. 41) covering the remaining second mask material 41 except for the second mask material 41 located at both ends of the array, and the resist is used as a mask to form a resist pattern on both ends of the array. The second mask material 41 located is removed by an etching process such as RIE, and then the resist pattern is removed. Next, at both ends of the rectangular second mask material 41, a resist pattern covering a certain area including one end of the plurality of second mask materials 41 is provided (the area surrounded by the dotted line in FIG. 41). Region 42). Next, using the resist pattern and the second mask material 41 as a mask (that is, selectively with respect to the resist pattern and the second mask material 41), a Si film serving as a mask film located thereunder is formed.₃N₄The film 9 is patterned. Here, if the resist is removed, the shape shown in FIG. 42 is obtained. Subsequently, if the semiconductor layer 3 (here, silicon) is etched by selective RIE using the mask material 9 and the second mask material 41 as a mask, the shape shown in FIG. 43 is obtained. Here, the second mask material 41 is lost during the etching of the semiconductor layer 3 since there is almost no selectivity between the polysilicon, which is the second mask material 41, and the silicon 3; Si located under the mask material 41₃N₄The film 9 is exposed and Si₃N₄The film 9 serves as a mask for etching. Thereafter, a field-effect transistor is formed in the same procedure as in the other embodiments. However, the procedure of the sixth embodiment is used for the step of selectively depositing a single-crystal, amorphous or polycrystalline semiconductor on the side surface of the source / drain region connecting portion and the step of forming the side wall preceding the step.
[0115]
In the step of FIG. 41, the purpose of removing the second mask materials 41 located at both ends of the array is as follows. At the time of exposure for forming a pattern, patterns located at both ends of the array may be formed to have a width different from that of other patterns due to the influence of the proximity effect. Since it is not preferable that the second mask materials 41 having different pattern widths coexist, it is desirable to remove those at both ends. However, when the proximity effect is small, it is not necessary to remove the patterns located at both ends of the array. On the other hand, when the influence of the proximity effect is large, a plurality of patterns may be appropriately removed from both ends of the array.
[0116]
In addition, the second mask material 41 at both ends of the array is not removed, and the resist pattern covering the region 42 is not applied to the second mask material 41 at both ends of the array. The semiconductor layer forming the channel formation region formed using the second mask material 41 as a mask is separated from the position where the source / drain region is formed (corresponding substantially to the region 42) so that the device characteristics are not affected. You can also.
[0117]
When removing one or a plurality of the second mask materials 41 from both ends of the array, the range (region 42) where the resist pattern covering one end of the plurality of the second mask materials 41 is provided from both ends of the array. If each one or a plurality of the second mask materials 41 are removed from each other, it is possible to apply to the range where each one or the plurality of the second mask materials 41 exist from both ends of the array. I don't care.
[0118]
Next, an embodiment for forming a thinner channel forming region will be described with reference to FIGS. As in the embodiment of FIGS. 41 to 43, a 100 nm thick SiO₂An SOI (silicon-on-insulator) substrate having a buried insulating layer 2 and a semiconductor layer 3 made of a single-crystal silicon layer with a thickness of 120 nm is prepared on the buried insulating layer 2. Next, a pad oxide film 8 is provided by thermally oxidizing the upper portion of the semiconductor layer 3 by 20 nm, and a 50 nm thick Si is formed thereon by CVD.₃N₄A membrane 9 is provided. Next, a 40 nm thick SiO₂By depositing a film by CVD and patterning the film, a second mask forming dummy pattern 43 (meaning a dummy pattern for forming a second mask, not a second dummy pattern for forming a mask). To form Next, a 30 nm-thick polysilicon is deposited as a second mask material on the whole, and this is etched back (etching equivalent to 30 nm to 50 nm), so that the polysilicon is formed around the second mask forming dummy pattern 43. After forming the side walls, the second dummy pattern 43 for mask formation is removed using diluted hydrofluoric acid, buffered hydrofluoric acid, or the like. Si₃N₄The polysilicon side wall remaining on the film 9 corresponds to the second mask material 41 in FIG. Thereafter, as in the steps of FIGS. 41 to 43, a resist pattern covering a certain area including one end of the second mask material 41 is provided (range 42 surrounded by a dotted line in FIG. 44). Next, using the resist pattern and the second mask material 41 as a mask, a mask film Si₃N₄The film 9 is patterned. Here, if the resist is removed, the shape shown in FIG. 45 is obtained. Subsequently, when the semiconductor layer 3 (here, silicon) is etched by selective RIE using the mask material 9 and the second mask material 41 as a mask, a shape similar to that of FIG. 43 is obtained. Thereafter, a field-effect transistor is formed in the same procedure as in the other embodiments. However, the procedure of the sixth embodiment is used for the step of selectively depositing a single-crystal, amorphous or polycrystalline semiconductor on the side surface of the source / drain region connecting portion and the step of forming the side wall preceding the step.
[0119]
In the steps described with reference to FIGS. 44 and 45, the width of the semiconductor layer forming the channel formation region is determined when the second mask material 41 is deposited on the side surface of the second mask formation dummy pattern 43. Although it depends on the thickness, generally, the thickness of the film deposited by CVD can be controlled with high precision, so that the width of the semiconductor layer forming the channel formation region can be controlled with high precision. Similarly, since the controllability of the thickness of the deposited film is good, it is advantageous for reducing the width of the semiconductor layer forming the channel formation region.
[0120]
Here, the semiconductor layer 3 can be selectively etched with respect to the mask film 9 and the second mask material 41, and the second mask forming dummy pattern 43 can be selectively etched with respect to the second mask material 41 and the mask film 9. Choose the material. For the second mask forming dummy pattern 43, a material that can be selectively etched with respect to the second mask material 41 is selected. However, the second mask material 41 and the mask film 9 are made of the same material, for example, Si₃N₄It can be a membrane. The second mask material 41 and the mask film 9 are made of the same material._mask1, T_mask2When the area indicated by reference numeral 42 in FIG. 41 or 44 is covered with a resist,_mask2That is, t_mask1+ T_mask2If RIE is performed under the condition that the film thickness is etched by the following amount, both of the second mask material 41 and the mask film 9 are not lost at the position of the conduction path. The second mask material 41 or the mask film 9 can be left.
[0121]
Each of the manufacturing methods described in the seventh embodiment with reference to FIGS. 41 to 45 does not perform the sidewall formation on the gate electrode described in the fourth embodiment or the source / drain connection described in the sixth embodiment. May be applied when the selective epitaxial growth is not performed. Further, it may be used for a case where a rectangular opening is provided as shown in FIG.
[0122]
Further, the respective manufacturing methods described with reference to FIGS. 41 to 45 in the seventh embodiment are replaced with the steps of providing a mask film in which openings are arranged in the respective embodiments described in the third and fifth embodiments. May be. However, it is not suitable when the boundary of the opening has a circular arc, when the opening is circular, or when the boundary of the opening is greatly inclined (specifically, near 45 degrees) with respect to the arrangement direction of the openings.
[0123]
【The invention's effect】
Although this field-effect transistor is a transistor having a channel formed on a side surface of a semiconductor layer substantially perpendicular to the substrate plane as a main conduction path, the shapes of the source / drain regions and the gate electrode are formed on the substrate surface. The shape when projected is the same as that of a normal field-effect transistor. The shape of the element region is the same as that of a normal field-effect transistor except for the arrangement of the openings crossing the center. Therefore, the contact with the source / drain region and the contact with the gate electrode can be formed by the same pattern and the same process as those of a normal field-effect transistor. Also, the source / drain regions are the same as ordinary SOI field-effect transistors except for the opening near the gate electrode. Therefore, the source / drain regions are formed to form source / drain regions, silicide, or reduce the resistance. In a step of epitaxially growing a semiconductor layer on a drain region, a process similar to that for a conventional field-effect transistor can be used. Therefore, except for adding an opening arrangement portion, almost the same pattern as that of a normal transistor can be used, and the formation of the opening and the processing around the opening (for example, processing of the gate electrode) are excluded. In a process (for example, formation of a contact to a gate and a source / drain), a feature is that the same process as that for a conventional field-effect transistor can be used.
[0124]
The channel formation region of this transistor is composed of a plurality of semiconductor regions connecting the source and the drain, and has a height h of the plurality of semiconductor layers.₃Is the width W of the semiconductor layer in the opening arrangement direction.₃Equal to or greater than. Since the potential of the channel formation region is controlled by the gate electrodes provided on both side surfaces of the semiconductor layer forming the channel formation region, the potential of the channel formation region can be easily controlled. Also, the width W of the semiconductor layer₃Is smaller than the sum of the widths of the two depletion layers on both sides formed in the semiconductor layer by the electric field from the gate electrodes disposed on both sides, so that the element can be operated in a fully depleted mode. And subthreshold characteristics (the degree to which a transistor turns off sharply when a gate voltage lower than the threshold voltage is applied) are improved, and the substrate floating effect (abnormal operation due to accumulation of excess carriers in the semiconductor layer) is suppressed. Is done.
[0125]
Also, the height h of the semiconductor layer₃And the width W of the semiconductor layer₃, The sum of the channel widths on both side surfaces (vertical direction in the cross section in FIG. 3) is twice the width of the channel formed on the upper surface of the semiconductor layer (horizontal direction in the cross section in FIG. 3). Height of semiconductor layer h₃Is the width W of the semiconductor layer₃If it is larger, the sum of the channel widths on both side surfaces (vertical direction in the cross section in FIG. 3) is twice or more as large as the width of the channel formed on the upper surface of the semiconductor layer (horizontal direction in the cross section in FIG. 3). Can be the dominant channel.
[0126]
When an opening is provided in the semiconductor layer, a structure in which the buried insulating layer is dug down to a certain depth in the opening and the gate electrode reaches a position slightly lower than the lower end of the semiconductor layer is used. Leakage current can be suppressed at a position below the semiconductor layer corresponding to an element region end in the effect transistor.
[0127]
In the manufacturing method of the present invention, a mask material (here, Si₃N₄Since a pattern in which openings are arranged is provided in advance on the film, and then the semiconductor layer 3 is patterned, the width of the semiconductor layer forming the channel formation region can be made uniform. Here, if the opening pattern and the pattern of the element region are to be formed simultaneously without providing an extra arrangement in the opening pattern, the channel forming region located at the end of the opening pattern arrangement (in FIG. The width of the resist pattern corresponding to the right and leftmost semiconductor regions is narrowed due to the influence of a light beam (or an electron beam or an X-ray beam) exposed to a wide region outside the element region. As a result, as shown in FIG. 51, the width of the semiconductor layer forming the channel forming region located at both ends of the opening pattern arrangement may be narrowed (proximity effect). In contrast, when the present manufacturing method is used, this problem does not occur, and an element region having a uniform width can be obtained.
[0128]
In the manufacturing method of the present invention, a mask layer (here, Si₃N₄Layer), the semiconductor layer in the channel formation region is not damaged during the etching of the gate.
[0129]
In the manufacturing method of the present invention, after removing the dummy gate electrode and the dummy gate insulating film, the second Si₃N₄A film is deposited by CVD, and a step of etching back by RIE is added to form a side wall. At this time, when both the semiconductor layer serving as a channel formation region and the dummy gate have substantially vertical side surfaces, the height of the dummy gate (the height from the lowermost edge to the uppermost edge in contact with the buried oxide film) is increased. If the thickness is at least twice as large as that of the semiconductor layer to be the channel formation region,₃N₄By performing RIE on the film at least as thick as the thickness of the semiconductor layer serving as a channel formation region, Si₃N₄There is no film side wall, and only the inner wall of the slit obtained by removing the dummy gate has an insulating side wall material (here, the second Si₃N₄Film).
[0130]
In the present invention, in the case of an n-channel transistor, PSG is adhered to the inner wall of the opening, high-concentration phosphorus is diffused from the PSG into the semiconductor region adjacent to the opening, and high-concentration phosphorus is applied to the semiconductor layers on both sides of the gate electrode. Phosphorus can be introduced. In the case of a p-channel transistor, a similar effect can be obtained by using a p-type impurity diffusion source such as BSG instead of PSG. Also in the case of an n-channel transistor, a similar effect can be obtained by replacing a p-type impurity diffusion source (for example, arsenic glass) other than PSG with PSG.
[0131]
In the manufacturing method of the present invention, hydrogen annealing is performed before the formation of the gate insulating film, so that the surface of the semiconductor layer forming the channel formation region can be planarized.
[0132]
According to the present invention, it is possible to form a sidewall on a dummy gate electrode or a gate electrode of a vertical field effect transistor FET, and to form various sidewalls on a source / drain region after forming a dummy gate electrode or after forming a gate electrode. When performing processing (ion implantation, silicidation, epitaxial growth of a semiconductor), the gate electrode and the lower portion of the gate electrode can be protected. Further, since the oxide film is not exposed after removing the dummy gate, the removal of the dummy gate oxide film can be performed by wet etching, and damage to the semiconductor layer forming the channel formation region is reduced. Further, at the time when the slit is formed by removing the dummy gate, the peripheral portion of the gate electrode protected by the sidewall remaining on the inner wall of the slit is not affected by wet etching, so that the semiconductor layer forming the channel formation region is thinned. At this time, it can be performed by sacrificial oxidation and subsequent wet etching of the sacrificial oxide film, and damage to the semiconductor layer forming the channel formation region (particularly, damage due to etching) is reduced.
[0133]
When a dummy gate is not formed, the invention of this embodiment may be applied to a gate electrode instead of the dummy gate. When various processes (ion implantation, silicidation, epitaxial growth of a semiconductor) are performed on the source / drain region after the gate is formed, the gate electrode and the lower portion of the gate electrode can be protected.
[Brief description of the drawings]
FIG. 1 is a bird's-eye view showing an embodiment of the present invention.
FIG. 2 is a top view showing the embodiment of the present invention.
FIG. 3 is a sectional view showing an embodiment of the present invention.
FIG. 4 is a sectional view showing an embodiment of the present invention.
FIG. 5 is a sectional view showing an embodiment of the present invention.
FIG. 6 is a top view showing the embodiment of the present invention.
FIG. 7 is a top view showing the embodiment of the present invention.
FIG. 8 is a sectional view showing an embodiment of the present invention.
FIG. 9 is a bird's-eye view showing an embodiment of the present invention.
FIG. 10 is a bird's-eye view showing an embodiment of the present invention.
FIG. 11 is a sectional view showing an embodiment of the present invention.
FIG. 12 is a sectional view showing an embodiment of the present invention.
FIG. 13 is a sectional view showing an embodiment of the present invention.
FIG. 14 is a sectional view showing an embodiment of the present invention.
FIG. 15 is a top view showing the embodiment of the present invention.
FIG. 16 is a sectional view showing an embodiment of the present invention.
FIG. 17 is a sectional view showing an embodiment of the present invention.
FIG. 18 is a sectional view showing an embodiment of the present invention.
FIG. 19 is a sectional view showing an embodiment of the present invention.
FIG. 20 is a sectional view showing an embodiment of the present invention.
FIG. 21 is a sectional view showing an embodiment of the present invention.
FIG. 22 is a sectional view showing an embodiment of the present invention.
FIG. 23 is a sectional view showing an embodiment of the present invention.
FIG. 24 is a sectional view showing an embodiment of the present invention.
FIG. 25 is a sectional view showing an embodiment of the present invention.
FIG. 26 is a sectional view showing an embodiment of the present invention.
FIG. 27 is a top view showing an embodiment of the present invention.
FIG. 28 is a top view showing the embodiment of the present invention.
FIG. 29 is a top view showing the embodiment of the present invention.
FIG. 30 is a top view showing the embodiment of the present invention.
FIG. 31 is a top view showing an embodiment of the present invention.
FIG. 32 is a top view showing the embodiment of the present invention.
FIG. 33 is a top view showing the embodiment of the present invention.
FIG. 34 is a top view showing the embodiment of the present invention.
FIG. 35 is a top view showing an embodiment of the present invention.
FIG. 36 is a sectional view showing an embodiment of the present invention.
FIG. 37 is a sectional view showing an embodiment of the present invention.
FIG. 38 is a sectional view showing an embodiment of the present invention.
FIG. 39 is a bird's-eye view showing an embodiment of the present invention.
FIG. 40 is a top view showing the embodiment of the present invention.
FIG. 41 is a top view showing an embodiment of the present invention.
FIG. 42 is a top view showing the embodiment of the present invention.
FIG. 43 is a top view showing the embodiment of the present invention.
FIG. 44 is a top view showing the embodiment of the present invention.
FIG. 45 is a top view showing the embodiment of the present invention.
FIG. 46 is a top view showing the embodiment of the present invention.
FIG. 47 is a top view showing the embodiment of the present invention.
FIG. 48 is a bird's-eye view showing an embodiment of the present invention.
FIG. 49 is a bird's-eye view showing an embodiment of the present invention.
FIG. 50 is a bird's-eye view illustrating a conventional technique.
FIG. 51 is a top view for explaining the effect of the manufacturing method of the present invention.
FIG. 52 is a top view showing a conventional element structure.
FIG. 53 is a cross-sectional view for explaining the element structure of the present invention.
FIG. 54 is a top view illustrating the effect of the present invention.
FIG. 55 is a top view illustrating the effect of the present invention.
FIG. 56 is a cross-sectional view illustrating an effect of the present invention.
FIG. 57 is a cross-sectional view illustrating an effect of the present invention.
[Explanation of symbols]
1 Silicon substrate
2 buried insulating layer
3 Semiconductor layer
4 Source / drain regions
5 Gate electrode
6 Gate insulating film
7 Channel formation area
8 Pad oxide film
9 Si₃N₄film
10 opening
11 Dummy gate electrode
12 PSG film
13 Interlayer insulation film
14 Gate insulating film
15 element area
16 source / drain contacts
17 Gate contact
18 Dummy gate insulating film
19 Opening formation area
20 Second Si₃N₄film
21 Second SiO₂film
22 First sidewall
23 Interlayer insulating film
24 metal wiring
31 Conduction path placement area
32 source / drain connection
33 conduction path
34 Opening arrangement area
35 One conduction path
36 Capacitance between gate side and source / drain side
41 Second mask material
42 Range of resist pattern (formation area)
43 Second Mask Forming Dummy Pattern
44 Range of resist pattern (formation area)
101 semiconductor substrate
102 Insulator
103 Semiconductor layer
104 Gate insulating film
105 Gate electrode

Claims (33)

A plurality of semiconductor conductive paths are arranged on the insulator in a predetermined direction, and source / drain regions are provided so as to face each other in a direction perpendicular to the arrangement direction of the conductive paths with the plurality of conductive paths interposed therebetween. The two source / drain regions are connected so as to be electrically connected by the plurality of conduction paths, and a gate electrode is formed via an insulating film in a region including at least a central portion of the semiconductor layer forming each of the conduction paths. A region in which a gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conduction paths forms a channel formation region, and the gate electrode is at least a central portion of the plurality of conduction paths. So as to straddle, provided along the arrangement direction of these conduction paths, in each of the conduction paths, both side surfaces of the semiconductor layer forming the conduction path are the main conduction paths,
The plurality of conduction paths are formed by semiconductor layer portions separated from each other by openings arranged in a predetermined direction in the semiconductor layer on the insulator,
A field-effect transistor wherein the width of each opening in the arrangement direction is smaller at a position closer to the source / drain region than at a position substantially equidistant from the two source / drain regions. As the distance from the position where the gate electrode is arranged is increased, at least a part of the shape of each of the openings projected onto the substrate plane has a shape in which the width of each of the openings in the arrangement direction has a constant slope and becomes narrow. The field effect transistor according to claim 1, wherein: 2. The field effect transistor according to claim 1, wherein the shape of each of the openings projected onto the plane of the substrate forms an arc at a position adjacent to the source / drain region. 2. The field effect transistor according to claim 1, wherein the shape of each of the openings projected onto the plane of the substrate is circular. 2. The field-effect transistor according to claim 1, wherein the shape of each of the openings projected onto the plane of the substrate is substantially square, and is inclined by about 45 degrees with respect to the arrangement direction of the openings. In a section perpendicular to the conduction direction connecting the two source / drain regions and covered by the gate electrode, the height of the semiconductor layer forming each of the conduction paths is the same as the width of the semiconductor layer. The field-effect transistor according to claim 1, wherein the field-effect transistor is larger. In a portion where a gate electrode is provided via an insulating film in a region including at least a central portion of the semiconductor layer forming each conduction path, an upper portion of the semiconductor layer forming a conduction path includes the semiconductor layer. The insulating film according to claim 1, wherein an insulating film thicker than a thickness of the insulating film formed on both side surfaces is provided, and a gate electrode is disposed above the thick insulating film. Field-effect transistor. In a portion where a gate electrode is provided via an insulating film in a region including at least a central portion of the semiconductor layer forming each of the conductive paths, a multilayer insulating film is provided above the semiconductor layer forming the conductive path. The field-effect transistor according to claim 1, wherein a gate electrode is provided on the insulating film. 8. The field effect transistor according to claim 7 , wherein at least a part of the thick insulating film formed on the semiconductor layer forming each of the conduction paths is made of a Si ₃ N ₄ film. .

10. The insulator under the gate electrode is dug down, and the lower surface of the gate electrode on the dug down insulator is located lower than the lower surface of each semiconductor layer forming the conduction path. Item 6. The field-effect transistor according to any one of Items 1 to 5. A plurality of semiconductor conductive paths are arranged on the insulator in a predetermined direction, and source / drain regions are provided so as to face each other in a direction perpendicular to the arrangement direction of the conductive paths with the plurality of conductive paths interposed therebetween. The two source / drain regions are connected so as to be electrically connected by the plurality of conduction paths, and a gate electrode is formed via an insulating film in a region including at least a central portion of the semiconductor layer forming each of the conduction paths. A region in which a gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conduction paths forms a channel formation region, and the gate electrode is at least a central portion of the plurality of conduction paths. Are provided along the direction in which the conductive paths are arranged, and in each of the conductive paths, both side surfaces of the semiconductor layer forming the conductive paths serve as main conductive paths. A method of manufacturing a field effect transistor having a
Forming a semiconductor layer on the insulator, providing at least one insulating mask film on the semiconductor layer, forming an opening pattern in which openings are arranged in a predetermined direction in the mask film; Patterning the mask film so that a region surrounding the opening remains, and patterning the semiconductor layer using the patterned mask film as a mask to form a semiconductor layer forming the conduction path and the source / drain regions A method for manufacturing a field-effect transistor, comprising: The opening pattern is a pattern in which extra openings are arranged at both ends in the opening arrangement direction, and in the step of patterning the mask film, patterning is performed so that the extra openings of the opening pattern do not remain. A method for manufacturing a field-effect transistor according to claim 11. A plurality of semiconductor conductive paths are arranged on the insulator in a predetermined direction, and source / drain regions are provided so as to face each other in a direction perpendicular to the arrangement direction of the conductive paths with the plurality of conductive paths interposed therebetween. The two source / drain regions are connected so as to be electrically connected by the plurality of conduction paths, and a gate electrode is formed via an insulating film in a region including at least a central portion of the semiconductor layer forming each of the conduction paths. A region in which a gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conduction paths forms a channel formation region, and the gate electrode is at least a central portion of the plurality of conduction paths. Are provided along the direction in which the conductive paths are arranged, and in each of the conductive paths, both side surfaces of the semiconductor layer forming the conductive paths serve as main conductive paths. A method of manufacturing a field effect transistor having a
Forming a semiconductor layer on an insulator, providing at least one insulating mask film on the semiconductor layer, and depositing a second mask material on the mask film; Processing the second mask material into a rectangular shape to be arranged, and a pattern of the second mask material to be arranged, with respect to a side perpendicular to the arrangement direction of the second mask material on the plane of projection onto the substrate. Providing two resist patterns extending in the direction of arrangement of the second mask material, covering a certain area including one end of each of both ends, and selecting both the resist pattern and the second mask material. Patterning the mask film so that the openings have an opening pattern arranged in a predetermined direction by etching the exposed mask film; and Film patterning the semiconductor layer as a mask, the conductive path and field effect method for producing a transistor, characterized in that it comprises a step of forming a semiconductor layer forming the source / drain regions. A plurality of semiconductor conductive paths are arranged on the insulator in a predetermined direction, and source / drain regions are provided so as to face each other in a direction perpendicular to the arrangement direction of the conductive paths with the plurality of conductive paths interposed therebetween. The two source / drain regions are connected so as to be electrically connected by the plurality of conduction paths, and a gate electrode is formed via an insulating film in a region including at least a central portion of the semiconductor layer forming each of the conduction paths. A region in which a gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conduction paths forms a channel formation region, and the gate electrode is at least a central portion of the plurality of conduction paths. Are provided along the direction in which the conductive paths are arranged, and in each of the conductive paths, both side surfaces of the semiconductor layer forming the conductive paths serve as main conductive paths. A method of manufacturing a field effect transistor having a
Forming a semiconductor layer on an insulator, providing at least one insulating mask film on the semiconductor layer, and providing a mask forming dummy pattern arranged on the mask film at regular intervals on the mask film; Depositing a second mask material on the mask forming dummy pattern and etching back the second mask material to form sidewalls of the second mask material around the mask forming dummy pattern, Removing the dummy pattern for mask formation and leaving the side wall on the mask film; and forming a second mask on a projection surface onto a substrate with respect to a pattern made of a second mask material arranged to form the side wall. Two resist patterns extending in the direction in which the second mask material is arranged, covering a certain area including one end of each of both ends of the side perpendicular to the direction in which the material is arranged. By selectively etching the exposed mask film with respect to both the resist pattern and the second mask material, the mask film is formed such that the openings have an opening pattern arranged in a certain direction. Patterning, and patterning the semiconductor layer using the patterned mask film as a mask to form a semiconductor layer forming the conduction path and the source / drain regions. Production method. A plurality of semiconductor conductive paths are arranged on the insulator in a predetermined direction, and source / drain regions are provided so as to face each other in a direction perpendicular to the arrangement direction of the conductive paths with the plurality of conductive paths interposed therebetween. The two source / drain regions are connected so as to be electrically connected by the plurality of conduction paths, and a gate electrode is formed via an insulating film in a region including at least a central portion of the semiconductor layer forming each of the conduction paths. A region in which a gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conduction paths forms a channel formation region, and the gate electrode is at least a central portion of the plurality of conduction paths. So as to straddle, provided along the arrangement direction of these conduction paths, in each of the conduction paths, both side surfaces of the semiconductor layer forming the conduction path are the main conduction paths,
A width of a semiconductor layer forming each conduction path in a direction parallel to a substrate surface in a cross section perpendicular to a conduction direction connecting the two source / drain regions is substantially equidistant from the two source / drain regions. A field-effect transistor, wherein a width near a source / drain region is larger than a width between positions. A plurality of semiconductor conductive paths are arranged on the insulator in a predetermined direction, and source / drain regions are provided so as to face each other in a direction perpendicular to the arrangement direction of the conductive paths with the plurality of conductive paths interposed therebetween. The two source / drain regions are connected so as to be electrically connected by the plurality of conduction paths, and a gate electrode is formed via an insulating film in a region including at least a central portion of the semiconductor layer forming each of the conduction paths. A region in which a gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conduction paths forms a channel formation region, and the gate electrode is at least a central portion of the plurality of conduction paths. So as to straddle, provided along the arrangement direction of these conduction paths, in each of the conduction paths, both side surfaces of the semiconductor layer forming the conduction path are the main conduction paths,
The width in the direction parallel to the substrate surface of the semiconductor layer forming each conduction path in a cross section perpendicular to the conduction direction connecting the two source / drain regions is constant at a position covered by the gate electrode. A field-effect transistor having a structure in which the width is larger at a position closer to the source / drain region than at the gate electrode, at a position covered by the gate electrode. A plurality of semiconductor conductive paths are arranged on the insulator in a predetermined direction, and source / drain regions are provided so as to face each other in a direction perpendicular to the arrangement direction of the conductive paths with the plurality of conductive paths interposed therebetween. The two source / drain regions are connected so as to be electrically connected by the plurality of conduction paths, and a gate electrode is formed via an insulating film in a region including at least a central portion of the semiconductor layer forming each of the conduction paths. A region in which a gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conduction paths forms a channel formation region, and the gate electrode is at least a central portion of the plurality of conduction paths. So as to straddle, provided along the arrangement direction of these conduction paths, in each of the conduction paths, both side surfaces of the semiconductor layer forming the conduction path are the main conduction paths,
The plurality of conduction paths are formed of semiconductor layer portions separated from each other by openings arranged in a predetermined direction in the semiconductor layer on the insulator,
A field-effect transistor, wherein the conduction path and the source / drain region are formed of a material integrally formed. A plurality of semiconductor conductive paths are arranged on the insulator in a predetermined direction, and source / drain regions are provided so as to face each other in a direction perpendicular to the arrangement direction of the conductive paths with the plurality of conductive paths interposed therebetween. The two source / drain regions are connected so as to be electrically connected by the plurality of conduction paths, and a gate electrode is formed via an insulating film in a region including at least a central portion of the semiconductor layer forming each of the conduction paths. A region in which a gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conduction paths forms a channel formation region, and the gate electrode is at least a central portion of the plurality of conduction paths. So as to straddle, provided along the arrangement direction of these conduction paths, in each of the conduction paths, both side surfaces of the semiconductor layer forming the conduction path are the main conduction paths,
The plurality of conduction paths are formed of semiconductor layer portions separated from each other by openings arranged in a predetermined direction in the semiconductor layer on the insulator,
A field-effect transistor, wherein a part of the opening that is in contact with the source / drain region is not covered with the gate electrode. A plurality of semiconductor conductive paths are arranged on the insulator in a predetermined direction, and source / drain regions are provided so as to face each other in a direction perpendicular to the arrangement direction of the conductive paths with the plurality of conductive paths interposed therebetween. The two source / drain regions are connected so as to be electrically connected by the plurality of conduction paths, and a gate electrode is formed via an insulating film in a region including at least a central portion of the semiconductor layer forming each of the conduction paths. A region in which a gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conduction paths forms a channel formation region, and the gate electrode is at least a central portion of the plurality of conduction paths. So as to straddle, provided along the arrangement direction of these conduction paths, in each of the conduction paths, both side surfaces of the semiconductor layer forming the conduction path are the main conduction paths, Serial plurality of conductive paths, a method of manufacturing a field-effect transistor made of a semiconductor layer portions separated from each other by an opening which is arranged and formed in a predetermined direction to the semiconductor layer on the insulator,
Providing a plurality of conductive paths connected to a semiconductor region common to the conductive paths and providing openings arranged in a single direction in a single semiconductor layer at positions where the conductive paths are separated from each other; A method for manufacturing a field effect transistor, comprising: The width of each of the openings in the arrangement direction is a width in the arrangement direction of each of the openings at a position at a predetermined distance from the source / drain region in a portion adjacent to a position where the source / drain region is formed. 20. The method for manufacturing a field effect transistor according to claim 19, wherein 21. The method for manufacturing a field-effect transistor according to claim 20, wherein the width of each of the openings in the arrangement direction is formed to be constant at a portion covered by the gate electrode. Providing a gate electrode or a dummy gate electrode so as to straddle a plurality of semiconductor layer portions separated from each other by the openings in a direction in which the openings formed in the semiconductor layer are arranged in the step of patterning the semiconductor layer. The method of manufacturing a field-effect transistor according to any one of claims 11 to 14, and 19 to 21. The introduction of impurities into the semiconductor layer portion forming the conduction path is performed by attaching a material containing a high concentration of impurities to the inner wall of each opening formed in the semiconductor layer in the step of patterning the semiconductor layer, and then performing heat treatment. The method of manufacturing a field-effect transistor according to any one of claims 11 to 14, and 19 to 21, wherein an impurity is diffused and introduced into the semiconductor layer portion from a material containing a high concentration of the impurity. 22. The insulator according to claim 11, wherein the insulator exposed in each opening formed in the step of patterning the semiconductor layer is etched to a predetermined depth. A method for manufacturing a field-effect transistor. 22. The method according to claim 11, wherein hydrogen annealing is performed on a side surface of the semiconductor layer exposed in each opening formed in the step of patterning the semiconductor layer. A method for manufacturing the field-effect transistor according to the above. 12. The semiconductor device according to claim 11, wherein a side surface of the semiconductor layer exposed in each of the openings formed in the step of patterning the semiconductor layer is covered with a SiO ₂ film, and heat treatment is performed at a temperature of 1200 ° C. or more for 1 hour or more. 22. The method of manufacturing a field-effect transistor according to any one of items 19 to 21. The side surface of the semiconductor layer exposed in each opening formed in the step of patterning the semiconductor layer is covered with an insulating film, and the side surface of the semiconductor layer covered with the insulating film or the conductive path is formed by a laser beam. 22. The method for manufacturing a field-effect transistor according to claim 11, wherein the semiconductor layer is melted, and the melted region is recrystallized. A side surface of the semiconductor layer exposed in each opening formed in the step of patterning the semiconductor layer is covered with an insulating film, and an electron beam forms the side surface of the semiconductor layer covered with the insulating film or the conduction path. 22. The method for manufacturing a field-effect transistor according to claim 11, wherein the semiconductor layer is melted, and the melted region is recrystallized. A side surface of the semiconductor layer exposed in each opening formed in the step of patterning the semiconductor layer is covered with an insulating film, and an electric heater forms the side surface of the semiconductor layer covered with the insulating film or the conduction path. 22. The method for manufacturing a field-effect transistor according to claim 11, wherein the semiconductor layer is melted, and the melted region is recrystallized. A plurality of semiconductor conductive paths are arranged on the insulator in a predetermined direction, and source / drain regions are provided so as to face each other in a direction perpendicular to the arrangement direction of the conductive paths with the plurality of conductive paths interposed therebetween. The two source / drain regions are connected so as to be electrically connected by the plurality of conduction paths, and a gate electrode is formed via an insulating film in a region including at least a central portion of the semiconductor layer forming each of the conduction paths. A region in which a gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conduction paths forms a channel formation region, and the gate electrode is at least a central portion of the plurality of conduction paths. So as to straddle, provided along the arrangement direction of these conduction paths, in each of the conduction paths, both side surfaces of the semiconductor layer forming the conduction path are the main conduction paths,
The width of the semiconductor layer forming each conduction path in a direction parallel to the substrate surface in a cross section perpendicular to the conduction direction connecting the two source / drain regions is substantially equidistant from the two source / drain regions. A field-effect transistor, wherein a width near a source / drain region is larger than a width between positions. A conduction path made of a semiconductor is arranged on an insulator, and source / drain regions are provided so as to face each other with the conduction path interposed therebetween, and these two source / drain regions are connected so as to conduct through the conduction path. A gate electrode is provided via an insulating film in a region including at least a central portion of the semiconductor layer forming the conductive path, and a gate electrode is formed on both side surfaces of the semiconductor layer forming the conductive path via an insulating film. The formed region forms a channel formation region, and the gate electrode is provided in a direction perpendicular to a direction connecting source / drain regions so as to straddle at least a central portion of the conduction path. , Both side surfaces of the semiconductor layer forming a conduction path become a main conduction path,
The width in the direction parallel to the substrate surface of the semiconductor layer forming each conduction path in a cross section perpendicular to the conduction direction connecting the two source / drain regions is larger than the width at the position covered by the gate electrode. A field-effect transistor having a structure that is larger at a position closer to a source / drain region than an electrode. A plurality of semiconductor conduction paths are arranged on the insulator in a predetermined direction, and source / drain regions are provided so as to face each other in a direction perpendicular to the arrangement direction of the conduction paths with the plurality of conduction paths interposed therebetween. The two source / drain regions are connected so as to be electrically connected by the plurality of conductive paths, and a gate electrode is formed via an insulating film in a region including at least a central portion of the semiconductor layer forming each of the conductive paths. A region in which a gate electrode is formed via an insulating film on both side surfaces of the semiconductor layer forming each of the conductive paths forms a channel forming region, and the gate electrode is at least a central portion of the plurality of conductive paths. As if straddling A method for manufacturing a field-effect transistor having a configuration in which the conductive paths are provided along the direction in which the conductive paths are arranged, and in each of the conductive paths, both side surfaces of the semiconductor layer forming the conductive path are main conductive paths. ,
Providing a first mask material on a semiconductor layer provided on the insulator;
Forming a dummy pattern on the first mask material, subsequently depositing a second mask material over the whole, and then etching it back to form sidewalls made of the second mask material around the dummy pattern. And subsequently removing the dummy pattern;
Patterning the first mask material using a side wall made of the second mask material remaining on the first mask material as a mask,
The semiconductor layer is etched using the first mask material and the second mask material remaining on the first mask material as a mask, and a shape in which a plurality of semiconductor conduction paths are arranged in a certain direction. Forming a field effect transistor. The semiconductor layer is SiO _Two The field-effect transistor according to any one of claims 1, 15 to 18, formed thereon. The semiconductor layer is Si _Three N _Four The field-effect transistor according to any one of claims 1, 15 to 18, formed thereon.

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