CN104465376B - Transistor and forming method thereof - Google Patents

Abstract

A transistor and its forming method, the forming method of the transistor includes: providing a semiconductor substrate; forming a gate structure on the surface of the semiconductor substrate, the top of the gate structure has a mask layer; The first sidewall and the second sidewall on the sidewall surfaces on both sides of the film layer; a semiconductor material layer is formed on the surface of the semiconductor substrate on both sides of the gate structure, and the surface of the semiconductor material layer is lower than the surface of the gate structure; Ion implantation is performed on the semiconductor material layer to form source and drain regions; the second sidewall is removed to form a groove between the source and drain region and the first sidewall of the gate; lightly doped ion implantation is performed on the semiconductor substrate at the bottom of the groove , forming a lightly doped region; removing the mask layer on the top of the gate structure to expose the top surface of the gate structure; forming a metal silicide layer on the surface of the source drain region and the lightly doped region. The above method can reduce the resistance of the source and drain regions of the transistor and improve the performance of the transistor.

Description

Transistors and methods of forming them

technical field

The invention relates to the technical field of semiconductors, in particular to a transistor and a forming method thereof.

Background technique

With the continuous development of semiconductor technology, the degree of integration of integrated circuits is getting higher and higher, and the size of devices is also decreasing. However, the continuous reduction of device size has greatly affected the performance of the device. For example, problems such as short channel effect, large power consumption, and large parasitic capacitance.

In the prior art, semiconductor devices are formed on SOI (silicon-on-insulator) substrates, and transistors are formed on SOI substrates, which can reduce the parasitic capacitance in the transistors, increase the operating speed, and the transistors have lower power consumption.

However, since the thickness of the top silicon layer of the SOI substrate is relatively thin, the thickness of the source-drain region of the transistor directly formed on the SOI substrate is relatively thin and has a high series resistance. A silicon layer with a certain thickness is epitaxially formed on the substrate on both sides of the gate structure, and then a raised source and drain region is formed in the silicon layer, and a metal silicide layer is formed on the surface of the source and drain region, thereby improving the source and drain region. The thickness of the region reduces the resistance of the source and drain regions.

However, the series resistance of the source-drain region of the transistor needs to be further reduced.

Contents of the invention

The problem to be solved by the present invention is to provide a transistor and its forming method to reduce the series resistance of the source and drain regions of the transistor.

In order to solve the above problems, the present invention provides a method for forming a transistor, comprising: providing a semiconductor substrate; forming a gate structure on the surface of the semiconductor substrate, and a mask layer is provided on the top of the gate structure; The structure and the sidewall surfaces on both sides of the mask layer form a sidewall structure, and the sidewall structure includes first sidewalls on the sidewall surfaces on both sides of the gate structure and the mask layer and a first sidewall on the first sidewall surface the second sidewall; form a semiconductor material layer on the surface of the semiconductor substrate on both sides of the gate structure, the surface of the semiconductor material layer is lower than the surface of the gate structure; perform ion implantation on the semiconductor material layer to form Source and drain regions; removing the second sidewall, forming a groove between the source and drain region and the first sidewall of the gate; performing lightly doped ion implantation on the semiconductor substrate at the bottom of the groove to form a light The doped region; removing the mask layer on the top of the gate structure to expose the top surface of the gate structure; forming a metal silicide layer on the surface of the source and drain regions and the surface of the lightly doped region at the bottom of the groove.

Optionally, the semiconductor substrate is silicon-on-insulator.

Optionally, the material of the mask layer is silicon oxide.

Optionally, the materials of the first side wall and the second side wall are different.

Optionally, the material of the first sidewall is silicon oxide, and the thickness of the first sidewall is greater than

Optionally, the material of the second sidewall is silicon nitride or silicon oxynitride

Optionally, the material of the semiconductor material layer is silicon, germanium or silicon germanium.

Optionally, the semiconductor material layer is formed by using a selective epitaxy process.

Optionally, the gate structure includes a gate dielectric layer located on the surface of the semiconductor substrate and a gate located on the surface of the gate dielectric layer, the material of the gate dielectric layer is silicon oxide, and the material of the gate is polysilicon .

Optionally, a metal silicide layer is also formed on the top of the gate structure.

Optionally, the method for forming the metal silicide includes: forming a metal layer on the surface of the source and drain regions, the lightly doped region at the bottom of the groove, the first sidewall, and the top of the gate structure; performing annealing treatment, A metal silicide layer is formed on the surface of the source and drain regions, the surface of the lightly doped region at the bottom of the groove, and the top surface of the gate structure; and the remaining metal layer is removed.

Optionally, the material of the metal layer includes at least one metal element selected from Ni, Ta, Ti, W, Co, Pt or Pd.

Optionally, the lightly doped region at the bottom of the groove is completely transformed into metal silicide.

Optionally, the method further includes: forming a dielectric layer on the surface of the metal silicide layer and the surface of the first sidewall.

Optionally, the material of the dielectric layer is a low-K dielectric material.

Optionally, the material of the dielectric layer includes at least one of: silicon carbide, silicon oxycarbide, organosiloxane polymer, and fluorocarbon.

The technical solution of the present invention also provides a transistor formed by the above method, including: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, the sidewall surface of the gate structure has a first side cavity; The source and drain regions in the semiconductor substrate on both sides of the electrode structure and the first sidewall, there is a groove between the source and drain region and the first sidewall, the surface of the source and drain region is higher than the surface of the semiconductor substrate and lower On the surface of the gate structure; the lightly doped region in the semiconductor substrate at the bottom of the groove between the source and drain regions and the first sidewall; the lightly doped region on the surface of the source and drain regions and at the bottom of the groove Surface metal silicide layer.

Optionally, the material of the lightly doped region at the bottom of the groove is metal silicide.

Optionally, a metal silicide layer on top of the gate structure is also included.

Optionally, a dielectric layer located on the surface of the metal silicide layer and the surface of the first sidewall and filling the groove.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the present invention, first sidewalls and second sidewalls are formed on both sides of the gate structure; then, using the gate structure, first sidewalls, and second sidewalls as masks, forming raised source and drain regions on both sides of the pole structure; then removing the second sidewall, forming a groove between the raised source and drain region and the first sidewall, exposing part of the surface of the semiconductor substrate; Lightly doped ion implantation is performed on the semiconductor substrate at the bottom of the groove to form a lightly doped region; a metal silicide layer is formed on the surface of the source and drain regions and the lightly doped region at the same time. Compared with forming a metal silicide layer on the surface of the region, it can further reduce the resistance of the lightly doped region and improve the performance of the transistor.

Further, after forming the metal silicide layer, a dielectric layer is formed on the surface of the metal silicide layer and in the groove. The material of the dielectric layer is a low-K dielectric material, which can reduce the parasitic capacitance between the source drain region and the gate, and improve the performance of the transistor.

Description of drawings

FIG. 1 is a schematic structural diagram of a transistor in the prior art of the present invention.

2 to 15 are structural schematic diagrams of the formation process of the transistor according to the embodiment of the present invention.

Detailed ways

As mentioned in the background art, the series resistance of the source-drain region of the transistor in the prior art needs to be further reduced.

Please refer to FIG. 1 , which is a schematic structural diagram of a transistor formed on an SOI substrate.

The transistor includes: a bottom silicon layer 10, an insulating layer 11 located on the surface of the bottom silicon layer, a raised source and drain region 12 located in the top silicon layer on the surface of the insulation layer; a gate dielectric located on the surface of the top silicon layer layer 21, the gate 22 located on the surface of the gate dielectric layer, the first spacer 23 located on the sidewall surfaces on both sides of the gate dielectric layer 21 and the gate 22, and the second side of the surface of the first spacer 23 wall 24. The transistor further includes a metal silicide layer 25 located on the top of the gate 22 and the surface of the source and drain regions 12 .

Since the top silicon layer of the SOI substrate is relatively thin, a silicon layer is formed on the surface of the top silicon layer on both sides of the gate structure, thereby forming a raised source and drain region 12, which can increase the thickness of the source and drain region 12 and reduce the thickness of the source and drain region 12. The series resistance of the source-drain region 12 ; forming the metal silicide layer 25 on the surface of the source-drain region 12 can also reduce the series resistance of the source-drain region 12 .

However, since the source-drain region 12 also has a part of the extension region (lightly doped region) located under the first sidewall 23, the second sidewall 24, and the gate dielectric layer 21, the thickness of the extension region is relatively thin, And the metal silicide layer cannot be formed on the surface, so the extended region still has a high resistance, which will affect the performance of the transistor.

In the embodiment of the present invention, a metal silicide layer is also formed on part of the surface of the extension region (lightly doped region) of the source and drain regions, so as to further reduce the series resistance of the source and drain regions of the transistor.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Referring to FIG. 2 , a semiconductor substrate 100 is provided.

The material of the semiconductor substrate 100 includes silicon, germanium, silicon germanium, gallium arsenide and other semiconductor materials, and the semiconductor substrate 100 may be a bulk material or a composite structure such as silicon-on-insulator. Those skilled in the art can select the type of the semiconductor substrate 100 according to the semiconductor devices formed on the semiconductor substrate 100 , so the type of the semiconductor substrate should not limit the protection scope of the present invention.

In this embodiment, the semiconductor substrate 100 is a silicon-on-insulator (SOI) substrate, and the semiconductor substrate 100 includes an underlying silicon layer 101, an insulating layer 102 located on the surface of the underlying silicon layer, and an insulating layer 102 located on the surface of the insulating layer 102. top silicon layer 103 .

Forming the transistor on the silicon-on-insulator (SOI) substrate can reduce the parasitic capacitance of the transistor, increase the switching rate of the transistor, and reduce the power consumption of the transistor.

Referring to FIG. 3, a gate dielectric material layer 201, a gate material layer 202 located on the surface of the gate dielectric material layer 201, and a mask located on the surface of the gate material layer 202 are formed on the surface of the semiconductor substrate 100. material layer 300 .

The gate dielectric material layer 201 is formed by a deposition process, the deposition process is chemical vapor deposition or atomic layer deposition process, and the thickness of the gate dielectric material layer 201 is 1 nm to 100 nm.

The gate material layer 202 is formed by a deposition process, and the thickness of the gate material layer is 10 nm˜200 nm.

In this embodiment, the material of the gate dielectric material layer 201 is silicon oxide or silicon oxynitride, and the material of the gate material layer 202 is polysilicon.

The material of the mask material layer 300 is silicon oxide or silicon nitride, and the thickness of the mask material layer 300 is 1 nm to 200 nm. The mask material layer 300 is subsequently patterned to form an etched gate material layer 202 and the mask of gate dielectric material layer 201.

Please refer to FIG. 4, etch the mask material layer 300 (please refer to FIG. 3) to form a mask layer 301; use the mask layer 301 as a mask to etch the gate material layer 202 (please refer to FIG. 3 ) and a gate dielectric material layer 201 (please refer to FIG. 3 ), forming a gate 212 and a gate dielectric layer 211 .

The method for forming the mask layer 301 includes: forming a photoresist layer on the surface of the mask material layer 300; developing and exposing the photoresist layer to form a patterned photoresist layer, and the patterned photoresist layer The layer defines the position and size of the subsequently formed gate structure; using the patterned photoresist layer as a mask, the mask material layer 300 (please refer to FIG. 3 ) is etched to form a mask layer 301 . The mask layer 301 serves as a mask for subsequent etching of the gate material layer 202 (please refer to FIG. 3 ) and the gate dielectric material layer 201 (please refer to FIG. 3 ).

The gate material layer 202 (please refer to FIG. 3 ) and the gate dielectric material layer 201 (please refer to FIG. 3 ) are etched by a dry etching process to form the gate 212 and the gate dielectric layer 211 respectively. The gate 212 and the gate dielectric layer 211 constitute the gate structure of the transistor.

Referring to FIG. 5 , a first sidewall material layer 302 is formed on the gate dielectric layer 211 , the gate electrode 212 , the sidewall surfaces of the mask layer 301 and the top silicon layer 103 .

The first sidewall material layer 302 may be formed by an oxidation process or a deposition process. In this embodiment, the material of the first side wall material layer 302 is silicon oxide, and the first side wall material layer 302 is formed by a thermal oxidation process, and the thickness of the first side wall material layer 302 is greater than

The first sidewall material layer 302 is subsequently used to form the first sidewall, the first sidewall can be used as an isolation structure on both sides of the gate structure, and can also repair the gate 212 during the etching process. the damage received.

In other embodiments of the present invention, the material of the first sidewall material layer 302 may also be silicon nitride or silicon oxynitride.

Referring to FIG. 6 , a second sidewall material layer 303 is formed on the surfaces of the first sidewall material layer 302 and the mask layer 301 .

The second sidewall material layer 303 can be formed by a chemical vapor deposition process, and the material of the second sidewall material layer 303 in this embodiment is silicon nitride.

The second sidewall material layer 303 is subsequently etched to form a second sidewall, and the second sidewall serves as a mask for ion implantation to form source and drain regions.

The thickness of the second side wall is 1 nm˜200 nm.

Referring to FIG. 7 , the second sidewall material layer 302 (please refer to FIG. 6 ) and the first sidewall material layer 301 are etched to form the second sidewall 313 and the first sidewall 312 respectively.

The first sidewall material layer 302 and the second sidewall material layer 303 located on the top of the mask layer 301 and part of the surface of the top silicon layer 103 are removed by a maskless etching process to form the second sidewall 313 and the first sidewall 312 .

The first sidewall 312 covers the mask layer 301 , the gate 212 , the sidewall surfaces of the gate dielectric layer 211 and part of the top silicon layer 103 , and the second sidewall 313 is located on the surface of the first sidewall 312 .

The first sidewall 313 serves as a mask for subsequent ion implantation to form source and drain regions, and is used to limit the distance between the source and drain regions and the gate.

Referring to FIG. 8 , a semiconductor material layer 400 is formed on the surface of the top silicon layer 103 on both sides of the gate 212 , the first sidewall 312 and the second sidewall 313 .

The semiconductor material layer 400 is formed by using a selective epitaxy process. In this embodiment, the material of the semiconductor material layer 400 is silicon, and in other examples of the present invention, the material of the semiconductor material layer 400 may also be semiconductor materials such as SiGe and Ge. The growth rate and thickness of the semiconductor material can be better controlled by using the selective epitaxy process, so that the surface of the finally formed semiconductor material layer 400 is lower than the surface of the gate 212 .

The semiconductor material layer 400 is used to increase the thickness of the semiconductor layers on both sides of the gate 212 , and subsequently form source and drain regions in the semiconductor material layer 400 and the top silicon layer 103 below it. The semiconductor material layer 400 increases the thickness of the source and drain regions, thereby reducing the series resistance of the formed source and drain regions.

Referring to FIG. 9 , heavily doped ion implantation is performed on the semiconductor material layer 400 and the top silicon layer 103 below to form source and drain regions 401 .

Using the mask layer 301, the first sidewall 312, and the second sidewall 313 as a mask, the semiconductor material layer 400 (please refer to FIG. 8 ) and the semiconductor material layer 400 (please refer to FIG. 8 ) A portion of the top silicon layer 103 directly below is implanted with heavily doped ions to form source and drain regions 401 .

The type of the heavily doped ion implantation is the same as that of the transistor to be formed.

Referring to FIG. 10 , the second side wall 313 (please refer to FIG. 9 ) is removed to form a groove 314 .

In this embodiment, a wet etching process is used to remove the second sidewall 313 (please refer to FIG. 9 ), and the etching solution of the wet etching is a phosphoric acid solution. In other embodiments of the present invention, the second sidewall 313 may also be removed by a dry etching process.

The groove 314 exposes part of the second measuring wall 312 on the surface of the top silicon layer 103 between the source and drain regions 401 and the gate 212 .

Referring to FIG. 11 , lightly doped ions are implanted into part of the top silicon layer 103 at the bottom of the groove 314 to form a lightly doped region 402 .

The ion type of the lightly doped ion implantation is the same as that of the transistor to be formed. Due to ion diffusion, part of the lightly doped region 402 is located under the gate dielectric layer 211 .

Forming the lightly doped region 402 can improve the short channel effect of the transistor.

Please refer to FIG. 12 , remove part of the first sidewall 312 at the bottom of the groove 314 and the mask layer 301 on the top of the gate 212 (please refer to FIG. 11 ), exposing part of the surface of the lightly doped region 402 and the gate 212 of the top surface.

After removing part of the first sidewall 312 and the mask layer 301 on the surface of the lightly doped region 402, the surface of the lightly doped region 402 and the gate 212 are exposed, which is convenient for the follow-up on the surface of the lightly doped region 402 and the gate. A metal silicide layer is formed on the top surface of the electrode 212 .

Referring to FIG. 13 , a metal layer 500 is formed on the surface of the source-drain region 401 , part of the lightly doped region 402 , the first sidewall 312 and the gate 212 .

The material of the metal layer 500 includes at least one metal element of Ni, Ta, Ti, W, Co, Pt or Pd. In this embodiment, the material of the metal layer 500 is Ni.

The metal layer 500 may be formed by evaporation or sputtering.

Referring to FIG. 14 , a metal silicide layer 501 is formed on the surface of the source-drain region 401 , the surface of a part of the lightly doped region 402 and the surface of the gate 212 .

In this embodiment, a two-step silicidation process is adopted using a furnace tube or rapid annealing equipment, in a high-purity nitrogen environment, low-temperature rapid annealing, for example, the reaction temperature is 260 ° C, and the duration is 30 seconds to form a nickel-rich phase silicide; subsequently, Wet etching is used to remove the excess Ni metal layer; finally, high-temperature rapid annealing is used, for example, the reaction temperature is 500° C., and the duration is 30 seconds, so that the nickel-rich phase silicide undergoes a phase transition, and the source and drain regions 401 A metal silicide layer 501 is formed on the surface, the surface of part of the lightly doped region 402 and the surface of the gate 212 .

In other embodiments of the present invention, a one-step silicidation process may also be adopted: a furnace tube or rapid annealing equipment is used to perform high-temperature rapid annealing in a high-purity nitrogen environment to directly form nickel silicide.

Since metal can only react with silicon to form a metal silicide layer, the metal silicide layer 501 can only be formed on the surface of the source and drain regions 401 , the surface of part of the lightly doped region 402 and the surface of the gate 212 .

After the metal silicide layer 501 is formed, a wet etching method is used to remove excess metal layer material.

In this embodiment, since the thickness of the lightly doped region 402 is relatively thin, the silicon in the lightly doped region 402 fully reacts with the metal, and completely transforms into metal silicide to reduce the resistance of the lightly doped region 402 .

Compared with the prior art, in this embodiment, not only a metal silicide layer is formed on the surface of the source and drain regions 401, but also a metal silicide layer is formed on the surface of the lightly doped region 402, which further reduces the resistance and avoids The thinner thickness causes the problem of larger resistance, which can improve the performance of the transistor.

Referring to FIG. 15 , a dielectric layer 600 is formed on the surface of the metal silicide layer 501 and the surface of the first spacer 312 .

The dielectric layer 600 fills the groove 314 (please refer to FIG. 14 ) and covers the source and drain regions 401 , part of the lightly doped region 402 , and the metal silicide layer 501 on the surface of the gate 212 . The dielectric layer 600 serves as an interlayer dielectric layer on the surface of the transistor, and metal plugs may be formed in the dielectric layer 600 to connect the source and drain regions 401 and the gate 212 of the transistor.

The material of the dielectric layer 600 is a low-K dielectric material, including at least one of silicon carbide, silicon oxycarbide, organosiloxane polymer, and fluorocarbon. The K value of the low-K dielectric material is relatively low, which can effectively reduce the parasitic capacitance between the gate 211 and the source-drain region 401, increase the operating speed of the transistor, and improve the performance of the transistor. In this embodiment, the material of the dielectric layer 600 is silicon carbide, and the dielectric layer 600 is formed by a chemical vapor deposition process.

This embodiment also provides a transistor formed by the above method.

Please refer to FIG. 15 , which is a schematic structural diagram of the transistor.

The transistor includes: a semiconductor substrate. In this embodiment, the semiconductor substrate is a silicon-on-insulator (SOI) substrate, and the semiconductor substrate includes an underlying silicon layer 101, an insulating layer 102 located on the surface of the underlying silicon layer, a top silicon layer 103 on the surface of the insulating layer 102;

A gate structure located on the surface of the top silicon layer 103 of the semiconductor substrate, the gate structure includes a gate dielectric layer 211 and a gate 212, and the sidewall surface of the gate structure has a first sidewall 312;

The source and drain regions 401 in the semiconductor substrate located on both sides of the gate structure and the first sidewall 312 have grooves between the source and drain regions 401 and the first sidewalls 312, and the source and drain regions 401 the surface is higher than the surface of the semiconductor substrate and lower than the surface of the gate structure;

a lightly doped region 402 in the semiconductor substrate at the bottom of the groove between the source and drain region 401 and the first sidewall 312;

The metal silicide layer 501 is located on the surface of the source and drain regions 401 and the surface of the lightly doped region 402 at the bottom of the groove.

In this embodiment, the lightly doped region 402 at the bottom of the groove is made of metal silicide, and the top of the gate structure also has a metal silicide layer 501 .

In this embodiment, the transistor further includes a dielectric layer 600 located on the surface of the metal silicide layer 501 and the surface of the first sidewall 312 and filling the groove, and the material of the dielectric layer is a low-K dielectric material. At least include: one of silicon carbide, silicon carbide, organosiloxane polymer, and fluorocarbon.

The surface of the source and drain regions 401 and the lightly doped region 402 of the transistor provided by this embodiment is formed with a metal silicide layer, which can reduce the resistance of the source and drain regions and the lightly doped region at the same time, and improve the performance of the transistor. Moreover, a low-K dielectric layer is filled between the gate structure and the source-drain region, which can reduce the parasitic capacitance between the gate and the source-drain region, increase the operating speed of the transistor, and improve the performance of the transistor.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (15)

1. A method for forming a transistor, comprising: providing a semiconductor substrate, the semiconductor substrate being silicon-on-insulator; forming a gate structure on the surface of the semiconductor substrate, with a mask layer on top of the gate structure; forming a first sidewall and a second sidewall on the surface of the first sidewall on the sidewall surfaces on both sides of the gate structure and the mask layer; Forming a semiconductor material layer on the surface of the semiconductor substrate on both sides of the gate structure, the surface of the semiconductor material layer is lower than the surface of the gate structure; performing ion implantation on the semiconductor material layer to form source and drain regions; removing the second sidewall to form a groove between the source-drain region and the first sidewall; Performing lightly doped ion implantation to the semiconductor substrate at the bottom of the groove to form a lightly doped region; removing part of the first sidewall at the bottom of the groove and the mask layer on the top of the gate structure, exposing part of the surface of the lightly doped region and the top surface of the gate structure; A metal silicide layer is formed on the surface of the source and drain regions and the surface of the lightly doped region at the bottom of the groove. 2. The method for forming a transistor according to claim 1, wherein the material of the mask layer is silicon oxide. 3 . The method for forming a transistor according to claim 1 , wherein the materials of the first sidewall and the second sidewall are different. 4 . 4. The method for forming a transistor according to claim 3, wherein the material of the first sidewall is silicon oxide, and the thickness of the first sidewall is greater than 5 . The method for forming a transistor according to claim 4 , wherein the material of the second sidewall is silicon nitride or silicon oxynitride. 6 . The method for forming a transistor according to claim 1 , wherein the material of the semiconductor material layer is silicon, germanium or silicon germanium. 7 . The method for forming a transistor according to claim 6 , wherein the semiconductor material layer is formed by using a selective epitaxy process. 8. The method for forming a transistor according to claim 1, wherein the gate structure comprises a gate dielectric layer located on the surface of the semiconductor substrate and a gate located on the surface of the gate dielectric layer, the gate dielectric layer The material of the gate is silicon oxide, and the material of the gate is polysilicon. 9. The method for forming a transistor according to claim 8, further comprising forming a metal silicide layer on top of the gate structure. 10. The method for forming a transistor according to claim 9, wherein the method for forming the metal silicide comprises: lightly doped regions at the bottom of the source and drain regions, groove bottoms, first sidewalls and gate forming a metal layer on the top surface of the pole structure; performing annealing treatment to form a metal silicide layer on the surface of the source and drain regions, the surface of the lightly doped region at the bottom of the groove, and the top surface of the gate structure; and removing the remaining metal layer. 11. The method for forming a transistor according to claim 10, wherein the material of the metal layer includes at least one metal element of Ni, Ta, Ti, W, Co, Pt or Pd. 12 . The method for forming a transistor according to claim 11 , wherein the lightly doped region at the bottom of the groove is completely transformed into metal silicide. 13 . 13. The method for forming a transistor according to claim 1, further comprising: forming a dielectric layer on the surface of the metal silicide layer and the surface of the first sidewall. 14. The method for forming a transistor according to claim 13, wherein the material of the dielectric layer is a low-K dielectric material. 15 . The method for forming a transistor according to claim 14 , wherein the material of the dielectric layer includes at least one of: silicon carbide, silicon oxycarbide, organosiloxane polymer, and fluorocarbon.