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CN101071823A - Semiconductor element and its manufacturing method - Google Patents

Semiconductor element and its manufacturing method Download PDF

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Publication number
CN101071823A
CN101071823A CN 200610077851 CN200610077851A CN101071823A CN 101071823 A CN101071823 A CN 101071823A CN 200610077851 CN200610077851 CN 200610077851 CN 200610077851 A CN200610077851 A CN 200610077851A CN 101071823 A CN101071823 A CN 101071823A
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semiconductor device
gate
layer
substrate
manufacturing
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Inventor
张惠贞
林建廷
许哲华
陈亮玮
李孟麟
萧维沧
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN 200610077851 priority Critical patent/CN101071823A/en
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Abstract

A semiconductor device comprises a substrate, a gate dielectric layer, a gate, a source/drain region and a stress layer. The grid dielectric layer is arranged on the substrate, the grid electrode is arranged on the grid dielectric layer, and the top area of the grid electrode is larger than the bottom area. In addition, the source/drain region is configured in the substrate at two sides of the grid, and the stress layer is configured on the substrate and covers the grid and the source/drain region.

Description

Semiconductor element and manufacture method thereof
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, relate in particular to a kind of semiconductor element and manufacture method thereof of promoting operation usefulness by the local mechanical Stress Control.
Background technology
In semiconductor element, often reach the purpose of high speed operation and low power consumption by dwindling component size.Yet, under the situation that the element integrated level constantly promotes, make present component size minimization degree near the limit, other dwindles the method for component size to need development, reaches the purpose of high speed operation and low power consumption.
Therefore, propose a kind of mode of utilizing the stress of control semiconductor transistor channel region in the prior art, solve component size minimization degree near the problem of the limit.This method is to utilize the stress changes spacing of lattice, increases the mobility of charge carrier rate.
The common method of control channel region stress, for utilization has the germanium-silicon layer of compression stress (compressive-stressedSi-Ge layer) as the transistorized channel region of PMOS, and utilization has the channel region of the silicon layer (tensile-strained Si layer) of tensile stress as NMOS, to change spacing of lattice, increase the mobility of charge carrier rate.Yet, in CMOS technology, in the time of forming above-mentioned channel region simultaneously, quite complicated on making.And, when carrying out high heat treatment and form germanium-silicon layer, can produce the phenomenon of dislocation (dislocation) or cause the separation of germanium, and make the characteristic degradation of gate breakdown voltage.
So, recently in the prior art, a kind of method of local mechanical Stress Control is arranged, be to utilize the silicon nitride layer that stops layer as contact hole etching, produce stress in channel region, influence the size of drive current and improve the mobility of charge carrier rate.
Though, above-mentioned local mechanical stress control method simple to operate, the stress that can improve channel region at present is limited.
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of semiconductor element, can effectively promote electron mobility, to reach the purpose of high speed operation and low power consumption.
A further object of the present invention provides a kind of manufacture method of semiconductor element, can increase the stress of channel region, to reach the purpose of high speed operation and low power consumption.
The present invention proposes a kind of semiconductor element, comprises substrate, gate dielectric layer, grid, source/drain regions and stressor layers.Wherein, gate dielectric layer is disposed in the substrate, and gate configuration is on gate dielectric layer, and the topside area of grid is greater than bottom area.In addition, source/drain regions is disposed in the grid substrate on two sides, and stressor layers is disposed in the substrate, and is covered on grid and the source/drain regions.
Described according to a preferred embodiment of the present invention, in above-mentioned semiconductor element, also comprise shallow doped region, be disposed in the substrate between source/drain regions and the grid.
Described according to a preferred embodiment of the present invention, in above-mentioned semiconductor element, also comprise ring-type injection region (halo implant region), be disposed in the substrate of shallow doped region below.
Described according to a preferred embodiment of the present invention, in above-mentioned semiconductor element, also comprise metal silicide, be disposed between grid and the stressor layers, and between source/drain regions and the stressor layers.
Described according to a preferred embodiment of the present invention, in above-mentioned semiconductor element, the material of metal silicide is titanium silicide, tungsten silicide, cobalt silicide, nickle silicide, molybdenum silicide or platinum silicide.
Described according to a preferred embodiment of the present invention, in above-mentioned semiconductor element, the material of stressor layers is silicon nitride, silica or silicon oxynitride.
Described according to a preferred embodiment of the present invention, in above-mentioned semiconductor element, also comprise lining oxide layer, be disposed on the sidewall of grid.
Described according to a preferred embodiment of the present invention, in above-mentioned semiconductor element, the material of lining oxide layer comprises silica.
Described according to a preferred embodiment of the present invention, in above-mentioned semiconductor element, the material of grid comprises doped polycrystalline silicon.
Described according to a preferred embodiment of the present invention, in above-mentioned semiconductor element, substrate is that silicon (silicon on insulator, substrate SOI) are arranged on silicon base or the insulating barrier.
The present invention proposes a kind of manufacture method of semiconductor element, and substrate at first is provided, and from bottom to top has been formed with gate dielectric layer and conductor layer in substrate, forms patterning photoresist layer again on conductor layer.Then, be mask with patterning photoresist layer, carry out etch process, remove the segment conductor layer with the formation grid, and remove the part gate dielectric layer, wherein the topside area of grid is greater than bottom area.Then, remove patterning photoresist layer, on the sidewall of grid, form clearance wall again.Next, in the clearance wall substrate on two sides, form source/drain regions, remove clearance wall again.Afterwards, in substrate, form stressor layers, and cover gate and source/drain regions.
Described according to a preferred embodiment of the present invention, in the manufacture method of above-mentioned semiconductor element, etch process is to use two groups of etching gas ratios variations to carry out the segmentation etching.
Described according to a preferred embodiment of the present invention, in the manufacture method of above-mentioned semiconductor element, these etching gass, one group is chlorine (Cl 2) and oxygen (O 2), another group is perfluoroethane (C 2F 6), hydrogen bromide (HBr) and helium (He).
Described according to a preferred embodiment of the present invention, in the manufacture method of above-mentioned semiconductor element, after removing patterning photoresist layer, also be included in and form shallow doped region in the grid substrate on two sides.
Described according to a preferred embodiment of the present invention, in the manufacture method of above-mentioned semiconductor element, the formation method of shallow doped region comprises ion implantation.
Described according to a preferred embodiment of the present invention, in the manufacture method of above-mentioned semiconductor element, after shallow doped region forms, also be included in the substrate of shallow doped region below and form the ring-type injection region.
Described according to a preferred embodiment of the present invention, in the manufacture method of above-mentioned semiconductor element, the formation method of ring-type injection region comprises the inclination angle ion implantation.
Described according to a preferred embodiment of the present invention, in the manufacture method of above-mentioned semiconductor element, after removing patterning photoresist layer, also be included on the sidewall of grid and form lining oxide layer.
Described according to a preferred embodiment of the present invention, in the manufacture method of above-mentioned semiconductor element, the formation method of lining oxide layer comprises thermal oxidation method.
Described according to a preferred embodiment of the present invention, in the manufacture method of above-mentioned semiconductor element, after source/drain regions formed, clearance wall also was included on grid and the source/drain regions and forms metal silicide before forming.
Described according to a preferred embodiment of the present invention, in the manufacture method of above-mentioned semiconductor element, the formation method of stressor layers comprises chemical vapour deposition technique.
Because in the semiconductor element and manufacture method thereof that the invention described above proposed, formed stressor layers can effectively improve the stress of channel region, can reach the purpose of high speed operation and low power consumption.In addition, semiconductor component structure of the present invention, the contact area of its grid and gate dielectric layer reduces, and can reduce the crossover electric capacity (overlap capacitance) between grid and the source/drain.On the other hand, the manufacture method of the semiconductor element that the present invention proposes can form the ring-type doped region, with effective inhibition short-channel effect in substrate.
For above and other objects of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Fig. 1 is the profile according to the semiconductor element that one embodiment of the invention illustrated;
Fig. 2 A～Fig. 2 E is the manufacturing process profile of the semiconductor element that illustrates according to one embodiment of the invention.
The simple symbol explanation
100,200: the semiconductor-based end
102,202: gate dielectric layer
104,208: grid
106,218: source/drain regions
108,222: stressor layers
110,210: lining oxide layer
112,212: shallow doped region
114,214: the ring-type injection region
116,220: metal silicide
204: conductor layer
206: patterning photoresist layer
216: clearance wall
Embodiment
Fig. 1 is the profile according to the semiconductor element that one embodiment of the invention illustrated.At first, please refer to Fig. 1, this semiconductor element for example is a nmos pass transistor, comprises semiconductor substrate 100, one deck gate dielectric layer 102, a grid 104, source 106, one deck stressor layers 108, one deck lining oxide layer 110, one shallow doped region 112, a ring-type injection region 114 and metal silicide 116.
Wherein, the semiconductor-based end 100 for example is the substrate that silicon is arranged on silicon base or the insulating barrier, and gate dielectric layer 102 is disposed at at semiconductor-based the end 100, and its material for example is a silica.
Grid 104 is disposed on the gate dielectric layer 102, and its material for example is a doped polycrystalline silicon, and the topside area of grid 104 is greater than bottom area.Thus, because the contact area of grid 104 and gate dielectric layer 102 reduces, can reduce the crossover electric capacity between grid and the source/drain.In this embodiment, though grid 104 sections be shaped as hexagon, not in order to restriction the present invention.In other words, so long as the topside area of grid is greater than bottom area, the shape of section there is no special qualification, and for example the section shape of grid can be for trapezoidal.
Source/drain regions 106 is disposed at at the semiconductor-based end 100 of grid 104 both sides, and its formation method for example is to be alloy with phosphorus, carries out an ion implantation technology.
Stressor layers 108 is disposed at at semiconductor-based the end 100, and is covered on grid 104 and the source/drain regions 106, and its material for example is silicon nitride, silica or silicon oxynitride, and its formation method for example is a chemical vapour deposition technique.Be to be example with the nmos pass transistor in this embodiment, then stressor layers is the rete with tensile stress.In another embodiment, if this semiconductor element is the PMOS transistor, then stressor layers is the rete with compression stress.
Lining oxide layer 110 is disposed on the sidewall of grid 104, and its material for example is a silica, and its formation method for example is a thermal oxidation method.
Shallow doped region 112 is disposed at at the semiconductor-based end 100 between source/drain regions 106 and the grid 104, and its formation method for example is to be alloy with phosphorus, carries out an ion implantation technology.
Ring-type injection region 114 is disposed at at the semiconductor-based end 100 of shallow doped region 108 belows, and its formation method for example is to be alloy with boron, carries out an inclination angle ion implantation technology, and it can be in order to suppress short-channel effect.
Metal silicide 116 is disposed between grid 104 and the stressor layers 108, and between source/drain regions 106 and the stressor layers 108, its material for example is titanium silicide, tungsten silicide, cobalt silicide, nickle silicide, molybdenum silicide or platinum silicide, can be in order to reduce resistance.
In the semiconductor element that the invention described above proposed, because the topside area of grid 104 greater than bottom area, makes the shape of grid 104 belows present recess.Thus, the direct stress application of stressor layers 108 energy can make the stress of channel region increase, to reach the purpose of high speed operation and low power consumption on channel region (indicating).
Then, will be in the formation method that semiconductor element proposed by the invention hereinafter is described in detail in detail.
Fig. 2 A～Fig. 2 E is the manufacturing process profile of the semiconductor element that illustrates according to one embodiment of the invention.
Please refer to Fig. 2 A, semiconductor element proposed by the invention is an example with the nmos pass transistor, and semiconductor substrate 200 at first is provided, on the semiconductor-based end 200, from bottom to top be formed with gate dielectric layer 202 and conductor layer 204, on conductor layer 204, formed patterning photoresist layer 206 again.Wherein, the material of gate dielectric layer 202 for example is a silica, and its formation method for example is a thermal oxidation method.The material of conductor layer 204 for example is a doped polycrystalline silicon, and its formation method for example is the mode of mixing with original position (In-situ), utilizes chemical vapour deposition technique to form it.
Then, please refer to Fig. 2 B, is mask with patterning photoresist layer 206, carries out an etch process, removes segment conductor layer 204 with formation grid 208, and removes part gate dielectric layer 202, and wherein the topside area of grid 204 is greater than bottom area.Wherein, this etch process for example is to use two groups of etching gass to carry out etching, and one group is chlorine (Cl 2) and oxygen (O 2), another group is perfluoroethane (C 2F 6), hydrogen bromide (HBr) and helium (He), by in etch process, adjusting the ratio of these two groups of etching gass, to form shape as grid 208 among Fig. 2 B.Thus, grid 208 reduces with the contact area of gate dielectric layer 202, can reduce the crossover electric capacity between grid and the source/drain.Yet, in this embodiment, though grid 208 sections be shaped as hexagon, not in order to restriction the present invention.In addition, can after forming, grid 208 remove patterning photoresist layer 206.Next, form lining oxide layer 210 on grid 208 sidewalls, its material for example is a silica, and its formation method for example is a thermal oxidation method.
Then, please refer to Fig. 2 C, form shallow doped region 212 in the semiconductor-based end 200 of grid 208 both sides, its formation method for example is to be alloy with phosphorus, carries out an ion implantation technology.
Then, form ring-type injection region 214 in the semiconductor-based end 200 of shallow doped region 212 belows, its formation method for example is to be that alloy carries out an inclination angle ion implantation technology with boron, and ring-type injection region 214 can effectively suppress short-channel effect.Continue it, form clearance wall 216 on the sidewall of grid 208, its material for example is a silicon nitride.
Then, please refer to Fig. 2 D, form source 218 respectively in the semiconductor-based end 200 of clearance wall 216 both sides, the method for formation for example is to be alloy with phosphorus, carries out an ion implantation technology.In addition, can carry out a rapid thermal anneal process to semiconductor substrate 200, so that the silicon crystal lattice on surface, the semiconductor-based ends 200 rearranges, the lattice defect that is caused when carrying out ion implantation technology again to remedy simultaneously can be with shallow doped region 212 and ring-type injection region 214 by diffusing into (drive in) grid 208 belows.
Subsequently, form metal silicide 220 on grid 208 and source/drain regions 218, its material for example is titanium silicide, tungsten silicide, cobalt silicide, nickle silicide, molybdenum silicide or platinum silicide.And the formation method of metal silicide 220 for example is prior to forming conformal metal material layer (not illustrating) at semiconductor-based the end 200, carry out a thermal process again, and on grid 208 and source/drain regions 218, form self aligned metal silicide 220, remove the unreacted metal material layer again and form it.
Next, please refer to Fig. 2 E, remove clearance wall 216, the method that removes for example is a wet etching.Continue it, on the semiconductor-based end 200, form stressor layers 222, and cover gate 208 and source/drain regions 218, its material for example is silicon nitride, silica or silicon oxynitride, its formation method for example is a chemical vapour deposition technique.Semiconductor element among this embodiment is a nmos pass transistor, and employed stressor layers is the rete with tensile stress, if semiconductor element is the PMOS transistor, employed stressor layers is the rete with compression stress.As for stressor layers is tension stress layer or compressive stress layers, can decide by the condition that the proof stress layer forms, for example be control temperature, pressure and process gas ratio etc., this is known by those having an ordinary knowledge in this technical field, repeats no more in this.
In the manufacture method of the semiconductor element that the invention described above proposed, because of formed grid 208, its topside area is greater than bottom area, make follow-up formation stressor layers 222 directly stress application on channel region, can make the stress of channel region increase, accelerate the mobility of charge carrier rate, to reach the purpose of high speed operation and low power consumption.
Though the above embodiment of the present invention is to be example with the nmos pass transistor, not in order to restriction the present invention.So, have in this technical field and to know the knowledgeable usually, can know by inference easily by the foregoing description, the present invention can be applicable in other semiconductor elements such as PMOS transistor and CMOS transistor.
In sum, the present invention has following advantage at least:
1. in semiconductor element and manufacture method thereof proposed by the invention, formed stressor layers can effectively improve the stress of channel region, can reach the purpose of high speed operation and low power consumption.
2. utilize the manufacture method of semiconductor element proposed by the invention, can form the ring-type doped region, can effectively suppress short-channel effect.
3. the semiconductor element proposed by the invention and the contact area of gate dielectric layer can effectively reduce, and can reduce the crossover electric capacity between grid and the source/drain regions.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art under the premise without departing from the spirit and scope of the present invention; can do a little change and retouching, thus protection scope of the present invention should with claims the person of being defined be as the criterion.

Claims (21)

1、一种半导体元件，包括：1. A semiconductor component, comprising: 基底；base; 栅介电层，配置于该基底上；a gate dielectric layer configured on the substrate; 栅极，配置于该栅介电层上，而该栅极的顶部面积大于底部面积；a gate configured on the gate dielectric layer, and the top area of the gate is larger than the bottom area; 源极/漏极区，配置于该栅极两侧的该基底中；以及source/drain regions disposed in the substrate on both sides of the gate; and 应力层，配置于该基底上，并覆盖于该栅极与该源极/漏极区上。The stress layer is configured on the base and covers the gate and the source/drain region. 2、如权利要求1所述的半导体元件，还包括浅掺杂区，配置于该源极/漏极区与该栅极之间的该基底中。2. The semiconductor device as claimed in claim 1, further comprising a lightly doped region disposed in the substrate between the source/drain region and the gate. 3、如权利要求2所述的半导体元件，还包括环状注入区，配置于该浅掺杂区下方的该基底中。3. The semiconductor device as claimed in claim 2, further comprising a ring-shaped implantation region disposed in the substrate below the lightly doped region. 4、如权利要求1所述的半导体元件，还包括金属硅化物，配置于该栅极与该应力层之间，及该源极/漏极区与该应力层之间。4. The semiconductor device as claimed in claim 1, further comprising a metal silicide disposed between the gate and the stress layer, and between the source/drain region and the stress layer. 5、如权利要求4所述的半导体元件，其中该金属硅化物的材料为硅化钛、硅化钨、硅化钴、硅化镍、硅化钼或硅化铂。5. The semiconductor device as claimed in claim 4, wherein the material of the metal silicide is titanium silicide, tungsten silicide, cobalt silicide, nickel silicide, molybdenum silicide or platinum silicide. 6、如权利要求1所述的半导体元件，其中该应力层的材料为氮化硅、氧化硅或氮氧化硅。6. The semiconductor device as claimed in claim 1, wherein the material of the stress layer is silicon nitride, silicon oxide or silicon oxynitride. 7、如权利要求1所述的半导体元件，还包括衬氧化层，配置于该栅极的侧壁上。7. The semiconductor device as claimed in claim 1, further comprising a liner oxide layer disposed on the sidewall of the gate. 8、如权利要求1所述的半导体元件，其中该衬氧化层的材料包括氧化硅。8. The semiconductor device as claimed in claim 1, wherein the material of the lining oxide layer comprises silicon oxide. 9、如权利要求1所述的半导体元件，其中该栅极的材料包括掺杂多晶硅。9. The semiconductor device as claimed in claim 1, wherein the material of the gate comprises doped polysilicon. 10、如权利要求1所述的半导体元件，其中该基底为硅基底或绝缘层上有硅的基底。10. The semiconductor device as claimed in claim 1, wherein the substrate is a silicon substrate or a silicon-on-insulator substrate. 11、一种半导体元件的制造方法，包括：11. A method of manufacturing a semiconductor element, comprising: 提供基底，在该基底上由下而上已形成有栅介电层及导体层；providing a substrate on which a gate dielectric layer and a conductor layer have been formed from bottom to top; 于该导体层上形成图案化光致抗蚀剂层；forming a patterned photoresist layer on the conductor layer; 以该图案化光致抗蚀剂层为掩模，进行蚀刻工艺，移除部分该导体层以形成栅极，并移除部分该栅介电层，其中该栅极的顶部面积大于底部面积；Using the patterned photoresist layer as a mask, performing an etching process, removing part of the conductor layer to form a gate, and removing part of the gate dielectric layer, wherein the top area of the gate is larger than the bottom area; 移除该图案化光致抗蚀剂层；removing the patterned photoresist layer; 于该栅极的侧壁上形成间隙壁；forming a spacer on the sidewall of the gate; 于该间隙壁两侧的该基底中形成源极/漏极区；forming source/drain regions in the substrate on both sides of the spacer; 移除该间隙壁；以及remove the spacer; and 于该基底上形成应力层，并覆盖该栅极及该源极/漏极区。A stress layer is formed on the base and covers the gate and the source/drain region. 12、如权利要求11所述的半导体元件的制造方法，其中该蚀刻工艺是使用二组蚀刻气体进行蚀刻。12. The method of manufacturing a semiconductor device as claimed in claim 11, wherein the etching process uses two sets of etching gases for etching. 13、如权利要求12所述的半导体元件的制造方法，其中该些蚀刻气体，一组为氯气及氧气，另一组为六氟乙烷、溴化氢及氦气。13. The method for manufacturing a semiconductor device as claimed in claim 12, wherein one group of the etching gases is chlorine and oxygen, and the other group is hexafluoroethane, hydrogen bromide and helium. 14、如权利要求11所述的半导体元件的制造方法，于移除该图案化光致抗蚀剂层之后，还包括于该栅极两侧的该基底中形成浅掺杂区。14. The method for manufacturing a semiconductor device as claimed in claim 11, further comprising forming shallowly doped regions in the substrate on both sides of the gate after removing the patterned photoresist layer. 15、如权利要求14所述的半导体元件的制造方法，其中该浅掺杂区的形成方法包括离子注入法。15. The method for manufacturing a semiconductor device as claimed in claim 14, wherein the method for forming the shallowly doped region comprises ion implantation. 16、如权利要求14所述的半导体元件的制造方法，于该浅掺杂区形成之后，还包括于该浅掺杂区下方的该基底中形成环状注入区。16. The method for manufacturing a semiconductor device as claimed in claim 14, further comprising forming a ring-shaped implantation region in the substrate below the shallowly doped region after the shallowly doped region is formed. 17、如权利要求16所述的半导体元件的制造方法，其中该环状注入区的形成方法包括倾斜角离子注入法。17. The method for manufacturing a semiconductor device as claimed in claim 16, wherein the method for forming the ring-shaped implanted region comprises an oblique-angle ion implantation method. 18、如权利要求11所述的半导体元件的制造方法，于移除该图案化光致抗蚀剂层之后，还包括于该栅极的侧壁上形成衬氧化层。18. The method for manufacturing a semiconductor device as claimed in claim 11, further comprising forming a liner oxide layer on the sidewall of the gate after removing the patterned photoresist layer. 19、如权利要求18所述的半导体元件的制造方法，其中该衬氧化层的形成方法包括热氧化法。19. The method of manufacturing a semiconductor device as claimed in claim 18, wherein the formation method of the liner oxide layer comprises a thermal oxidation method. 20、如权利要求11所述的半导体元件的制造方法，于该源极/漏极区形成之后，该间隙壁形成之前，还包括于该栅极与该源极/漏极区上形成金属硅化物。20. The method for manufacturing a semiconductor device according to claim 11, further comprising forming a metal silicide on the gate and the source/drain region after the source/drain region is formed and before the spacer is formed. thing. 21、如权利要求11所述的半导体元件的制造方法，其中该应力层的形成方法包括化学气相沉积法。21. The method for manufacturing a semiconductor device as claimed in claim 11, wherein the method for forming the stress layer includes chemical vapor deposition.
CN 200610077851 2006-05-08 2006-05-08 Semiconductor element and its manufacturing method Pending CN101071823A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102790085A (en) * 2011-05-20 2012-11-21 中芯国际集成电路制造(上海)有限公司 Semi-conductor device and production method thereof
CN103915389A (en) * 2014-04-10 2014-07-09 苏州东微半导体有限公司 Manufacturing method for semiconductor memory and semiconductor memory

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102790085A (en) * 2011-05-20 2012-11-21 中芯国际集成电路制造(上海)有限公司 Semi-conductor device and production method thereof
US9111862B2 (en) 2011-05-20 2015-08-18 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor apparatus and manufacturing method thereof
CN102790085B (en) * 2011-05-20 2016-04-20 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacture method thereof
CN103915389A (en) * 2014-04-10 2014-07-09 苏州东微半导体有限公司 Manufacturing method for semiconductor memory and semiconductor memory
CN103915389B (en) * 2014-04-10 2016-08-24 苏州东微半导体有限公司 The manufacture method of a kind of semiconductor memory and semiconductor memory thereof

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