CN103377894B - Method for manufacturing metal silicide - Google Patents

Abstract

The invention discloses a metal silicide manufacturing method, comprising the steps of: forming characteristic lines on a silicon-containing substrate; forming a nickel-based metal layer on the silicon-containing substrate and the characteristic lines, wherein the thickness of the nickel-based metal layer is greater than that obtained by the The minimum thickness required to form nickel-based metal silicide determined by the drain junction depth; perform a first anneal so that the nickel-based metal layer reacts with the silicon-containing substrate to form a uniform thickness of the first nickel-based metal silicide; remove unreacted metal Afterwards, a second annealing is performed, so that the first nickel-based metal silicide is transformed into a second nickel-based metal silicide with a uniform thickness. According to the semiconductor device manufacturing method of the present invention, by increasing the thickness of the metal thin layer, using the metal silicide self-alignment process and controlling the process parameters, a metal silicide with a uniform thickness is formed by annealing in two steps, thereby uniformly reducing the source leakage resistance, which further improves the performance of the device.

Description

Metal silicide manufacturing method

technical field

The invention relates to a metal silicide manufacturing method, in particular to a method capable of effectively improving the film uniformity of the metal silicide film.

Background technique

The continuous increase of IC integration requires the continuous reduction of device size according to this example. However, the operating voltage of electrical appliances sometimes remains unchanged, so that the electric field strength in the actual MOS device continues to increase. The high electric field brings a series of reliability problems, which degrades the performance of the device. For example, parasitic series resistance between the source and drain regions of a MOSFET will cause the equivalent operating voltage to drop. In particular, when the physical gate length of a semiconductor device such as MOSFET is close to sub-30nm, the source-drain parasitic resistance exceeds the channel resistance and becomes an important part of the equivalent resistance of the entire device. Therefore, it is necessary to use metal silicide on and/or in the source and drain regions to effectively reduce the source and drain contact resistance and parasitic series resistance, thereby improving the device performance of the MOSFET.

1A to 1C are cross-sectional views of the prior art silicide self-alignment process steps. As shown in FIG. 1A, a plurality of gate stack structures composed of a gate insulating layer 2 and a gate conductive layer 3 are sequentially formed on a substrate 1 containing Si, and gate sides are formed on both sides of each gate stack structure. wall 4, and then form a thin metal layer 5 on the entire structure, the material of which is Ni-based metal, such as Ni, NiPt, NiCo, NiPtCo and so on. It is worth noting that since the process of forming the thin metal layer 5 is usually sputtering, limited by the process conditions and the principle of sputtering, the narrow area between adjacent gate stack structures (shown by the dotted line box in the figure) Above, the thickness of the metal thin layer 5 is smaller than the thickness of the wider area outside this area, that is, there is a thickness difference of the metal thin layer 5 between the narrow line and the wide line of the device. Below the sub-32nm CMOS process node, this difference in thickness becomes more obvious, and sometimes may even cause missing and breaking of the thin metal layer 5 on the narrow lines. As shown in FIG. 1B, the first rapid annealing is performed at a lower temperature such as 250-300° C., so that the thin metal layer 5 reacts with the Si contained in the substrate 1 to form a nickel-based metal silicide 6 in a Ni-rich phase, For example Ni ₂ Si, Ni ₂ PtSi, Ni ₂ CoSi, Ni ₂ PtCoSi. Due to the thickness difference of the aforementioned metal thin layer 5, the thickness of the Ni-rich phase nickel-based metal silicide 6 on the narrow line is reduced, and may even be completely missing or fractured, that is, no Ni-rich phase is formed in this region. Nickel-based metal silicide 6. As shown in Figure 1C, after stripping off the unreacted metal thin layer 5, the second rapid annealing is performed at a higher temperature such as 450-500° C., so that the nickel-based metal silicide 6 of the Ni-rich phase is transformed into a Resistive nickel-based metal silicide 7, such as NiSi, NiPtSi, NiCoSi, NiPtCoSi. Due to the above-mentioned difference in thickness, the thickness of the finally formed nickel-based metal silicide 7 on narrow lines and wide lines is not uniform, that is, the thickness of the part between the dense gate stack lines is obviously smaller, while other wider parts The upper thickness is significantly larger. The denser and narrower the lines, the thinner the metal silicide film thickness on this area, and the greater the resistance. However, on different dies or different regions of the wafer, narrow lines are usually accompanied by wide lines, so the metal silicide film thickness distribution is not uniform. Such thickness inhomogeneity will cause inconsistencies in device contact and parasitic resistance, resulting in undesired changes in the electrical properties of the device.

It can be seen that the existing metal silicide process makes the thickness of the film uneven, which reduces the electrical performance and reliability of the device.

Contents of the invention

From the above, the purpose of the present invention is to provide a semiconductor device manufacturing method that can effectively improve the thickness uniformity of the metal silicide film.

For this reason, the present invention provides a kind of metal silicide manufacturing method, comprises the steps: form characteristic line on silicon-containing substrate; Form nickel-based metal layer on silicon-containing substrate and characteristic line, wherein the thickness of nickel-based metal layer greater than the minimum thickness required to form the nickel-based metal silicide determined by the depth of the source-drain junction; perform the first annealing, so that the nickel-based metal layer reacts with the silicon-containing substrate to form a first nickel-based metal silicide with a uniform thickness; After reacting the metal, a second anneal is performed so that the first Ni-based metal silicide is converted into a second Ni-based metal silicide with a uniform thickness.

Wherein, the thickness of the nickel-based metal layer is 7-200nm.

Wherein, the nickel-based metal layer includes Ni, Ni-Pt, Ni-Co, Ni-Pt-Co. Wherein, the content of non-Ni metal is 1%-50%.

Wherein, the temperature of the second annealing is higher than the temperature of the first annealing. Wherein, the first annealing temperature is 150-300°C, and the second annealing temperature is 450-550°C.

Wherein, the Ni content in the first nickel-based metal silicide is greater than the Ni content in the second nickel-based metal silicide. Wherein, the first nickel-based metal silicide includes Ni ₂ Si, Ni ₂ PtSi, Ni ₂ CoSi, Ni ₂ PtCoSi, and the second nickel-based metal silicide includes NiSi, NiPtSi, NiCoSi, NiPtCoSi.

According to the metal silicide manufacturing method of the present invention, by increasing the thickness of the metal thin layer, using the metal silicide self-alignment process and controlling the process parameters, a metal silicide with a uniform thickness is formed by annealing in two steps, thereby uniformly reducing The source-drain resistance further improves the performance of the device.

Description of drawings

Describe technical scheme of the present invention in detail below with reference to accompanying drawing, wherein:

1A to 1C are schematic cross-sectional views of a metal silicide manufacturing method in the prior art; and

2 to 4 are schematic cross-sectional views of various steps of the metal silicide manufacturing method that can effectively improve the uniformity of the film according to the present invention.

detailed description

The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in combination with schematic embodiments, and a metal silicide manufacturing method that can effectively improve the uniformity of the film is disclosed. It should be pointed out that similar reference numerals represent similar structures, and the terms "first", "second", "upper", "lower" and the like used in this application can be used to modify various device structures or manufacturing processes . These modifications do not imply spatial, sequential or hierarchical relationships of the modified device structures or fabrication processes unless specifically stated.

2 to 4 are schematic cross-sectional views of various steps of the metal silicide manufacturing method that can effectively improve the uniformity of the film according to the present invention.

With reference to accompanying drawing 2, form basic structure. Figure 2 is a schematic cross-sectional view of the basic structure.

Firstly, a substrate 1 is provided, and the substrate 1 contains at least Si element, such as bulk Si, Si on insulator (SOI), SiGe, SiC, etc., preferably, the substrate 1 is bulk Si or SOI.

Second, a plurality of feature lines are formed on the substrate 1 . For MOSFET fabrication, the gate insulating layer 2 and the gate conductive layer 3 are sequentially deposited on the substrate 1 by conventional methods such as LPCVD, PECVD, HDPCVD, MOCVD, and MBE, and etched to form multiple gate stacks. structure. For the front-gate process, the gate stack structure is not removed after formation, as the final gate stack, so the gate insulating layer 2 is silicon oxide, silicon oxynitride or a high-k material, and the high-k material includes but not limited to nitrogen Compounds (such as SiN, AIN, TiN), metal oxides (mainly subgroup and lanthanide metal element oxides, such as Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , ZnO, ZrO ₂ , HfO ₂ , CeO ₂ , Y ₂ O ₃ ), perovskite phase oxides (such as PbZr _x Ti _1-x O ₃ (PZT), Ba _x Sr _1-x TiO ₃ (BST)); correspondingly, the gate conductive layer 3 is doped Heteropolysilicon, metal, metal alloy, metal nitride, wherein the metal includes W, Cu, Mo, Ti, Al, Ta, etc. and combinations thereof. For the gate-last process, the gate stack is a dummy gate stack, which will be removed in a later process to form a gate trench for later refilling to form a gate, so the gate insulating layer 2 is silicon oxide, Silicon oxynitride, the gate conductive layer 3 is polysilicon, microcrystalline silicon, or amorphous silicon. An insulating medium is deposited on the gate stack structures 2 and 3 and etched to form a gate spacer 4, the material of which is, for example, silicon nitride, silicon oxynitride, diamond-like amorphous carbon (DLC), metal oxide (preferably with High stress, such as greater than 1 GPa, to apply stress to the channel to improve driving capability). For other device structures, the characteristic lines may be Si lines of fin-shaped structures, dense SRAM cell patterns, and the like.

Then, deposit a metal layer 5 on the entire device, that is, on the substrate 1 and the feature lines formed by the gate spacer 4 and the gate conductive layer 3 by, for example, sputtering to form a metal silicide Precursor. The thickness H1 of the metal layer 5 is thick enough to exceed the thickness H0 required to form the metal silicide by using the metal silicide self-alignment process in the prior art in FIG. 1 (indicated by the dotted horizontal line in FIG. 2 ). H0 usually depends on the depth of the source-drain junction (that is, the minimum thickness of the metal layer 5 required for a given depth of the source-drain junction after the metal silicide is formed in the future), for example, 1 to 5 nm; and H1, for example, is greater than or equal to 1.4 times H0 is, for example, 7 to 200 nm. The material of the metal layer 5 is a nickel-based metal, that is, a metal or a metal alloy containing at least Ni, such as Ni, Ni-Pt, Ni-Co, Ni-Pt-Co, wherein non-Ni metal elements (Pt and/or Co ) The total content (number of atoms) is preferably 1% to 50%, that is, the corresponding Ni content is relatively high 50% to 99%.

Referring to FIG. 3 , the first annealing is performed so that the metal of the metal layer 5 reacts with the Si in the substrate 1 to form a first metal silicide 6 , that is, a metal-rich phase silicide 6 with higher resistance. For example, if the rapid annealing process is adopted, the annealing temperature is the lower first annealing temperature, which is 150-300° C., and the annealing time is 5 seconds to 5 minutes. The formed metal-rich silicide 6 is nickel-rich silicide, such as Ni ₂ Si, Ni ₂ PtSi, Ni ₂ CoSi, Ni ₂ PtCoSi. At this lower first annealing temperature, the diffusion of Ni atoms rich in the metal layer 5 is limited and self-saturated, so the nickel-rich phase silicide 6 will not grow too thick, and the Ni-based metal with the thickness above H0 will be consumed After the layer 5, the reaction is stopped, so the thickness H2 of the nickel-rich phase silicide 6 is above the substrate surface, and the part H2' is equal to or close to the metal layer thickness required by the metal silicide process determined by the depth of the source-drain junction. H0 is, for example, 1.0 to 1.1 times H0 (although it is shown as equal in FIG. 3 , it can actually fluctuate up and down). The thickness of the nickel-rich phase silicide 6 is limited by the annealing temperature and time, and the silicide process is self-saturated, and is no longer limited by the thickness of the metal layer 5 (because the thickness H1 of the metal layer 5 is greater than the required thickness H0), Therefore, the nickel-rich phase silicide 6 has an equal and uniform thickness H2 on the entire wafer, thereby ensuring the uniformity of the film when the low-resistance metal silicide is subsequently formed.

Referring to FIG. 4 , after removing the unreacted metal, a second annealing is performed so that the first metal silicide 6 is transformed into a second metal silicide 7 , that is, a metal silicide 7 with lower resistance. The unreacted metal layer 5 in FIG. 3 is peeled off, that is, the part whose thickness exceeds H0 (its thickness is H1-H0). The rapid annealing process is adopted, the annealing temperature is a higher second annealing temperature (that is, the second annealing temperature is higher than the first annealing temperature), which is 450-550° C., and the annealing time is 5 seconds to 3 minutes. The metal silicide 7 is a nickel-based metal silicide, and the Ni content in the second metal silicide 7 is lower than that in the first metal silicide 6 . Specifically, the metal silicide 7 is, for example, NiSi, NiPtSi, NiCoSi, NiPtCoSi. Since the formation process of the first metal silicide 6 in FIG. 3 is self-saturated and forms a thin film with uniform thickness, the thickness of the second metal silicide 7 in FIG. 4 also maintains uniformity correspondingly, that is, it has the same thickness H3 . Depending on the annealing temperature and time, H3 may be greater than or equal to H2, for example, 1.1-1.2 times H2.

It can be seen from FIG. 4 that the finally formed low-resistance Ni-based metal silicide 7 has a uniform film thickness, so it also has the same film resistance, which improves the uniformity and reliability of the device.

According to the semiconductor device manufacturing method of the present invention, by increasing the thickness of the metal thin layer, using the metal silicide self-alignment process and controlling the process parameters, a metal silicide with a uniform thickness is formed by annealing in two steps, thereby uniformly reducing the source Leakage resistance, which further improves the performance of the device.

While the invention has been described with reference to one or more exemplary embodiments, those skilled in the art will recognize various suitable changes and equivalents in device structures that do not depart from the scope of the invention. In addition, many modifications, possibly suited to a particular situation or material, may be made from the disclosed teaching without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode for carrying out this invention, but that the disclosed device structures and methods of making the same will include all embodiments falling within the scope of the invention .

Claims (10)

1. A metal silicide manufacturing method, comprising the steps of: forming a plurality of feature lines on a silicon-containing substrate; forming a nickel-based metal layer on a silicon-containing substrate and a plurality of feature lines, wherein the thickness of the nickel-based metal layer is greater than 1.4 times the minimum thickness required to form a nickel-based metal silicide determined by the depth of the source-drain junction; performing a first annealing so that the nickel-based metal layer reacts with the silicon-containing substrate to form a first nickel-based metal silicide with a uniform thickness; After removing the unreacted metal, a second annealing is performed so that the first nickel-based metal silicide is transformed into a second nickel-based metal silicide with a uniform thickness. 2. The method for producing a metal silicide according to claim 1, wherein the nickel-based metal layer has a thickness of 7 to 200 nm. 3. The metal silicide manufacturing method according to claim 1, wherein the nickel-based metal layer comprises Ni, Ni-Pt, Ni-Co, Ni-Pt-Co. 4. The method for producing a metal silicide according to claim 3, wherein the content of the non-Ni metal is 1% to 50%. 5. The metal silicide manufacturing method according to claim 1, wherein a temperature of the second annealing is higher than a temperature of the first annealing. 6. The metal silicide manufacturing method according to claim 5, wherein the first annealing temperature is 150-300°C. 7. The metal silicide manufacturing method according to claim 5, wherein the second annealing temperature is 450-550°C. 8. The metal silicide manufacturing method according to claim 1, wherein the Ni content in the first nickel-based metal silicide is greater than the Ni content in the second nickel-based metal silicide. 9. The metal silicide manufacturing method according to claim 7, wherein the first nickel-based metal silicide comprises Ni ₂ Si, Ni ₂ PtSi, Ni ₂ CoSi, Ni ₂ PtCoSi. 10. The metal silicide manufacturing method according to claim 7, wherein the second nickel-based metal silicide comprises NiSi, NiPtSi, NiCoSi, NiPtCoSi.